)]}'
{
  "commit": "d8df1b394a7bcb8c4d2ae60455ced043889b607e",
  "tree": "a73c0e96d645f83d07fc33cbbc4a1518f30398ab",
  "parents": [
    "826d0d54632751949c149b689d5444a23efc47c9"
  ],
  "author": {
    "name": "Cindy Chen",
    "email": "chencindy@opentitan.org",
    "time": "Tue Feb 07 15:41:04 2023 -0800"
  },
  "committer": {
    "name": "Greg Chadwick",
    "email": "mail@gregchadwick.co.uk",
    "time": "Thu Feb 23 10:57:22 2023 +0000"
  },
  "message": "[dv/sysrst_ctrl] Fix low power test failure\n\nThe ulp test failure is reported in issue #17238. As explained in the\ndiscussion, I think the failure is a testbench issue.\nThe test did not set to 0 long enough to pass the debounce timer. So DUT\ncombined both request and triggers unexpected wake up pins.\n\nSigned-off-by: Cindy Chen \u003cchencindy@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6d04414ecd3b3c2b255f45fdb1ab62fe6e075b6a",
      "old_mode": 33188,
      "old_path": "hw/ip/sysrst_ctrl/dv/env/seq_lib/sysrst_ctrl_ultra_low_pwr_vseq.sv",
      "new_id": "d95eb9dbc613db886d3b7dfbc219745338d8d1ca",
      "new_mode": 33188,
      "new_path": "hw/ip/sysrst_ctrl/dv/env/seq_lib/sysrst_ctrl_ultra_low_pwr_vseq.sv"
    }
  ]
}