| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module adc_ctrl_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input clk_aon_i, |
| input rst_aon_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| // To HW |
| output adc_ctrl_reg_pkg::adc_ctrl_reg2hw_t reg2hw, // Write |
| input adc_ctrl_reg_pkg::adc_ctrl_hw2reg_t hw2reg, // Read |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import adc_ctrl_reg_pkg::* ; |
| |
| localparam int AW = 7; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [30:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(31) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(1) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| assign tl_reg_h2d = tl_i; |
| assign tl_o_pre = tl_reg_d2h; |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(0) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic intr_state_we; |
| logic intr_state_qs; |
| logic intr_state_wd; |
| logic intr_enable_we; |
| logic intr_enable_qs; |
| logic intr_enable_wd; |
| logic intr_test_we; |
| logic intr_test_wd; |
| logic alert_test_we; |
| logic alert_test_wd; |
| logic adc_en_ctl_we; |
| logic [1:0] adc_en_ctl_qs; |
| logic adc_en_ctl_busy; |
| logic adc_pd_ctl_we; |
| logic [31:0] adc_pd_ctl_qs; |
| logic adc_pd_ctl_busy; |
| logic adc_lp_sample_ctl_we; |
| logic [7:0] adc_lp_sample_ctl_qs; |
| logic adc_lp_sample_ctl_busy; |
| logic adc_sample_ctl_we; |
| logic [15:0] adc_sample_ctl_qs; |
| logic adc_sample_ctl_busy; |
| logic adc_fsm_rst_we; |
| logic [0:0] adc_fsm_rst_qs; |
| logic adc_fsm_rst_busy; |
| logic adc_chn0_filter_ctl_0_we; |
| logic [31:0] adc_chn0_filter_ctl_0_qs; |
| logic adc_chn0_filter_ctl_0_busy; |
| logic adc_chn0_filter_ctl_1_we; |
| logic [31:0] adc_chn0_filter_ctl_1_qs; |
| logic adc_chn0_filter_ctl_1_busy; |
| logic adc_chn0_filter_ctl_2_we; |
| logic [31:0] adc_chn0_filter_ctl_2_qs; |
| logic adc_chn0_filter_ctl_2_busy; |
| logic adc_chn0_filter_ctl_3_we; |
| logic [31:0] adc_chn0_filter_ctl_3_qs; |
| logic adc_chn0_filter_ctl_3_busy; |
| logic adc_chn0_filter_ctl_4_we; |
| logic [31:0] adc_chn0_filter_ctl_4_qs; |
| logic adc_chn0_filter_ctl_4_busy; |
| logic adc_chn0_filter_ctl_5_we; |
| logic [31:0] adc_chn0_filter_ctl_5_qs; |
| logic adc_chn0_filter_ctl_5_busy; |
| logic adc_chn0_filter_ctl_6_we; |
| logic [31:0] adc_chn0_filter_ctl_6_qs; |
| logic adc_chn0_filter_ctl_6_busy; |
| logic adc_chn0_filter_ctl_7_we; |
| logic [31:0] adc_chn0_filter_ctl_7_qs; |
| logic adc_chn0_filter_ctl_7_busy; |
| logic adc_chn1_filter_ctl_0_we; |
| logic [31:0] adc_chn1_filter_ctl_0_qs; |
| logic adc_chn1_filter_ctl_0_busy; |
| logic adc_chn1_filter_ctl_1_we; |
| logic [31:0] adc_chn1_filter_ctl_1_qs; |
| logic adc_chn1_filter_ctl_1_busy; |
| logic adc_chn1_filter_ctl_2_we; |
| logic [31:0] adc_chn1_filter_ctl_2_qs; |
| logic adc_chn1_filter_ctl_2_busy; |
| logic adc_chn1_filter_ctl_3_we; |
| logic [31:0] adc_chn1_filter_ctl_3_qs; |
| logic adc_chn1_filter_ctl_3_busy; |
| logic adc_chn1_filter_ctl_4_we; |
| logic [31:0] adc_chn1_filter_ctl_4_qs; |
| logic adc_chn1_filter_ctl_4_busy; |
| logic adc_chn1_filter_ctl_5_we; |
| logic [31:0] adc_chn1_filter_ctl_5_qs; |
| logic adc_chn1_filter_ctl_5_busy; |
| logic adc_chn1_filter_ctl_6_we; |
| logic [31:0] adc_chn1_filter_ctl_6_qs; |
| logic adc_chn1_filter_ctl_6_busy; |
| logic adc_chn1_filter_ctl_7_we; |
| logic [31:0] adc_chn1_filter_ctl_7_qs; |
| logic adc_chn1_filter_ctl_7_busy; |
| logic [27:0] adc_chn_val_0_qs; |
| logic adc_chn_val_0_busy; |
| logic [27:0] adc_chn_val_1_qs; |
| logic adc_chn_val_1_busy; |
| logic adc_wakeup_ctl_we; |
| logic [7:0] adc_wakeup_ctl_qs; |
| logic adc_wakeup_ctl_busy; |
| logic filter_status_we; |
| logic [7:0] filter_status_qs; |
| logic filter_status_busy; |
| logic adc_intr_ctl_we; |
| logic [8:0] adc_intr_ctl_qs; |
| logic [8:0] adc_intr_ctl_wd; |
| logic adc_intr_status_we; |
| logic [7:0] adc_intr_status_filter_match_qs; |
| logic [7:0] adc_intr_status_filter_match_wd; |
| logic adc_intr_status_oneshot_qs; |
| logic adc_intr_status_oneshot_wd; |
| // Define register CDC handling. |
| // CDC handling is done on a per-reg instead of per-field boundary. |
| |
| logic aon_adc_en_ctl_adc_enable_qs_int; |
| logic aon_adc_en_ctl_oneshot_mode_qs_int; |
| logic [1:0] aon_adc_en_ctl_qs; |
| logic [1:0] aon_adc_en_ctl_wdata; |
| logic aon_adc_en_ctl_we; |
| logic unused_aon_adc_en_ctl_wdata; |
| |
| always_comb begin |
| aon_adc_en_ctl_qs = 2'h0; |
| aon_adc_en_ctl_qs[0] = aon_adc_en_ctl_adc_enable_qs_int; |
| aon_adc_en_ctl_qs[1] = aon_adc_en_ctl_oneshot_mode_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(2), |
| .ResetVal(2'h0), |
| .BitMask(2'h3), |
| .DstWrReq(0) |
| ) u_adc_en_ctl_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_en_ctl_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[1:0]), |
| .src_busy_o (adc_en_ctl_busy), |
| .src_qs_o (adc_en_ctl_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_en_ctl_qs), |
| .dst_we_o (aon_adc_en_ctl_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_en_ctl_wdata) |
| ); |
| assign unused_aon_adc_en_ctl_wdata = |
| ^aon_adc_en_ctl_wdata; |
| |
| logic aon_adc_pd_ctl_lp_mode_qs_int; |
| logic [3:0] aon_adc_pd_ctl_pwrup_time_qs_int; |
| logic [23:0] aon_adc_pd_ctl_wakeup_time_qs_int; |
| logic [31:0] aon_adc_pd_ctl_qs; |
| logic [31:0] aon_adc_pd_ctl_wdata; |
| logic aon_adc_pd_ctl_we; |
| logic unused_aon_adc_pd_ctl_wdata; |
| |
| always_comb begin |
| aon_adc_pd_ctl_qs = 32'h64060; |
| aon_adc_pd_ctl_qs[0] = aon_adc_pd_ctl_lp_mode_qs_int; |
| aon_adc_pd_ctl_qs[7:4] = aon_adc_pd_ctl_pwrup_time_qs_int; |
| aon_adc_pd_ctl_qs[31:8] = aon_adc_pd_ctl_wakeup_time_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h64060), |
| .BitMask(32'hfffffff1), |
| .DstWrReq(0) |
| ) u_adc_pd_ctl_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_pd_ctl_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_pd_ctl_busy), |
| .src_qs_o (adc_pd_ctl_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_pd_ctl_qs), |
| .dst_we_o (aon_adc_pd_ctl_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_pd_ctl_wdata) |
| ); |
| assign unused_aon_adc_pd_ctl_wdata = |
| ^aon_adc_pd_ctl_wdata; |
| |
| logic [7:0] aon_adc_lp_sample_ctl_qs_int; |
| logic [7:0] aon_adc_lp_sample_ctl_qs; |
| logic [7:0] aon_adc_lp_sample_ctl_wdata; |
| logic aon_adc_lp_sample_ctl_we; |
| logic unused_aon_adc_lp_sample_ctl_wdata; |
| |
| always_comb begin |
| aon_adc_lp_sample_ctl_qs = 8'h4; |
| aon_adc_lp_sample_ctl_qs = aon_adc_lp_sample_ctl_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h4), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_adc_lp_sample_ctl_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_lp_sample_ctl_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (adc_lp_sample_ctl_busy), |
| .src_qs_o (adc_lp_sample_ctl_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_lp_sample_ctl_qs), |
| .dst_we_o (aon_adc_lp_sample_ctl_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_lp_sample_ctl_wdata) |
| ); |
| assign unused_aon_adc_lp_sample_ctl_wdata = |
| ^aon_adc_lp_sample_ctl_wdata; |
| |
| logic [15:0] aon_adc_sample_ctl_qs_int; |
| logic [15:0] aon_adc_sample_ctl_qs; |
| logic [15:0] aon_adc_sample_ctl_wdata; |
| logic aon_adc_sample_ctl_we; |
| logic unused_aon_adc_sample_ctl_wdata; |
| |
| always_comb begin |
| aon_adc_sample_ctl_qs = 16'h9b; |
| aon_adc_sample_ctl_qs = aon_adc_sample_ctl_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(16), |
| .ResetVal(16'h9b), |
| .BitMask(16'hffff), |
| .DstWrReq(0) |
| ) u_adc_sample_ctl_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_sample_ctl_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[15:0]), |
| .src_busy_o (adc_sample_ctl_busy), |
| .src_qs_o (adc_sample_ctl_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_sample_ctl_qs), |
| .dst_we_o (aon_adc_sample_ctl_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_sample_ctl_wdata) |
| ); |
| assign unused_aon_adc_sample_ctl_wdata = |
| ^aon_adc_sample_ctl_wdata; |
| |
| logic aon_adc_fsm_rst_qs_int; |
| logic [0:0] aon_adc_fsm_rst_qs; |
| logic [0:0] aon_adc_fsm_rst_wdata; |
| logic aon_adc_fsm_rst_we; |
| logic unused_aon_adc_fsm_rst_wdata; |
| |
| always_comb begin |
| aon_adc_fsm_rst_qs = 1'h0; |
| aon_adc_fsm_rst_qs = aon_adc_fsm_rst_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_adc_fsm_rst_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_fsm_rst_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (adc_fsm_rst_busy), |
| .src_qs_o (adc_fsm_rst_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_fsm_rst_qs), |
| .dst_we_o (aon_adc_fsm_rst_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_fsm_rst_wdata) |
| ); |
| assign unused_aon_adc_fsm_rst_wdata = |
| ^aon_adc_fsm_rst_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_0_min_v_0_qs_int; |
| logic aon_adc_chn0_filter_ctl_0_cond_0_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_0_max_v_0_qs_int; |
| logic aon_adc_chn0_filter_ctl_0_en_0_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_0_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_0_wdata; |
| logic aon_adc_chn0_filter_ctl_0_we; |
| logic unused_aon_adc_chn0_filter_ctl_0_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_0_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_0_qs[11:2] = aon_adc_chn0_filter_ctl_0_min_v_0_qs_int; |
| aon_adc_chn0_filter_ctl_0_qs[12] = aon_adc_chn0_filter_ctl_0_cond_0_qs_int; |
| aon_adc_chn0_filter_ctl_0_qs[27:18] = aon_adc_chn0_filter_ctl_0_max_v_0_qs_int; |
| aon_adc_chn0_filter_ctl_0_qs[31] = aon_adc_chn0_filter_ctl_0_en_0_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_0_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_0_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_0_busy), |
| .src_qs_o (adc_chn0_filter_ctl_0_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_0_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_0_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_0_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_0_wdata = |
| ^aon_adc_chn0_filter_ctl_0_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_1_min_v_1_qs_int; |
| logic aon_adc_chn0_filter_ctl_1_cond_1_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_1_max_v_1_qs_int; |
| logic aon_adc_chn0_filter_ctl_1_en_1_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_1_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_1_wdata; |
| logic aon_adc_chn0_filter_ctl_1_we; |
| logic unused_aon_adc_chn0_filter_ctl_1_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_1_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_1_qs[11:2] = aon_adc_chn0_filter_ctl_1_min_v_1_qs_int; |
| aon_adc_chn0_filter_ctl_1_qs[12] = aon_adc_chn0_filter_ctl_1_cond_1_qs_int; |
| aon_adc_chn0_filter_ctl_1_qs[27:18] = aon_adc_chn0_filter_ctl_1_max_v_1_qs_int; |
| aon_adc_chn0_filter_ctl_1_qs[31] = aon_adc_chn0_filter_ctl_1_en_1_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_1_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_1_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_1_busy), |
| .src_qs_o (adc_chn0_filter_ctl_1_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_1_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_1_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_1_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_1_wdata = |
| ^aon_adc_chn0_filter_ctl_1_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_2_min_v_2_qs_int; |
| logic aon_adc_chn0_filter_ctl_2_cond_2_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_2_max_v_2_qs_int; |
| logic aon_adc_chn0_filter_ctl_2_en_2_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_2_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_2_wdata; |
| logic aon_adc_chn0_filter_ctl_2_we; |
| logic unused_aon_adc_chn0_filter_ctl_2_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_2_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_2_qs[11:2] = aon_adc_chn0_filter_ctl_2_min_v_2_qs_int; |
| aon_adc_chn0_filter_ctl_2_qs[12] = aon_adc_chn0_filter_ctl_2_cond_2_qs_int; |
| aon_adc_chn0_filter_ctl_2_qs[27:18] = aon_adc_chn0_filter_ctl_2_max_v_2_qs_int; |
| aon_adc_chn0_filter_ctl_2_qs[31] = aon_adc_chn0_filter_ctl_2_en_2_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_2_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_2_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_2_busy), |
| .src_qs_o (adc_chn0_filter_ctl_2_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_2_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_2_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_2_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_2_wdata = |
| ^aon_adc_chn0_filter_ctl_2_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_3_min_v_3_qs_int; |
| logic aon_adc_chn0_filter_ctl_3_cond_3_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_3_max_v_3_qs_int; |
| logic aon_adc_chn0_filter_ctl_3_en_3_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_3_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_3_wdata; |
| logic aon_adc_chn0_filter_ctl_3_we; |
| logic unused_aon_adc_chn0_filter_ctl_3_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_3_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_3_qs[11:2] = aon_adc_chn0_filter_ctl_3_min_v_3_qs_int; |
| aon_adc_chn0_filter_ctl_3_qs[12] = aon_adc_chn0_filter_ctl_3_cond_3_qs_int; |
| aon_adc_chn0_filter_ctl_3_qs[27:18] = aon_adc_chn0_filter_ctl_3_max_v_3_qs_int; |
| aon_adc_chn0_filter_ctl_3_qs[31] = aon_adc_chn0_filter_ctl_3_en_3_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_3_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_3_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_3_busy), |
| .src_qs_o (adc_chn0_filter_ctl_3_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_3_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_3_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_3_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_3_wdata = |
| ^aon_adc_chn0_filter_ctl_3_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_4_min_v_4_qs_int; |
| logic aon_adc_chn0_filter_ctl_4_cond_4_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_4_max_v_4_qs_int; |
| logic aon_adc_chn0_filter_ctl_4_en_4_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_4_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_4_wdata; |
| logic aon_adc_chn0_filter_ctl_4_we; |
| logic unused_aon_adc_chn0_filter_ctl_4_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_4_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_4_qs[11:2] = aon_adc_chn0_filter_ctl_4_min_v_4_qs_int; |
| aon_adc_chn0_filter_ctl_4_qs[12] = aon_adc_chn0_filter_ctl_4_cond_4_qs_int; |
| aon_adc_chn0_filter_ctl_4_qs[27:18] = aon_adc_chn0_filter_ctl_4_max_v_4_qs_int; |
| aon_adc_chn0_filter_ctl_4_qs[31] = aon_adc_chn0_filter_ctl_4_en_4_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_4_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_4_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_4_busy), |
| .src_qs_o (adc_chn0_filter_ctl_4_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_4_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_4_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_4_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_4_wdata = |
| ^aon_adc_chn0_filter_ctl_4_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_5_min_v_5_qs_int; |
| logic aon_adc_chn0_filter_ctl_5_cond_5_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_5_max_v_5_qs_int; |
| logic aon_adc_chn0_filter_ctl_5_en_5_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_5_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_5_wdata; |
| logic aon_adc_chn0_filter_ctl_5_we; |
| logic unused_aon_adc_chn0_filter_ctl_5_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_5_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_5_qs[11:2] = aon_adc_chn0_filter_ctl_5_min_v_5_qs_int; |
| aon_adc_chn0_filter_ctl_5_qs[12] = aon_adc_chn0_filter_ctl_5_cond_5_qs_int; |
| aon_adc_chn0_filter_ctl_5_qs[27:18] = aon_adc_chn0_filter_ctl_5_max_v_5_qs_int; |
| aon_adc_chn0_filter_ctl_5_qs[31] = aon_adc_chn0_filter_ctl_5_en_5_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_5_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_5_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_5_busy), |
| .src_qs_o (adc_chn0_filter_ctl_5_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_5_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_5_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_5_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_5_wdata = |
| ^aon_adc_chn0_filter_ctl_5_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_6_min_v_6_qs_int; |
| logic aon_adc_chn0_filter_ctl_6_cond_6_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_6_max_v_6_qs_int; |
| logic aon_adc_chn0_filter_ctl_6_en_6_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_6_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_6_wdata; |
| logic aon_adc_chn0_filter_ctl_6_we; |
| logic unused_aon_adc_chn0_filter_ctl_6_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_6_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_6_qs[11:2] = aon_adc_chn0_filter_ctl_6_min_v_6_qs_int; |
| aon_adc_chn0_filter_ctl_6_qs[12] = aon_adc_chn0_filter_ctl_6_cond_6_qs_int; |
| aon_adc_chn0_filter_ctl_6_qs[27:18] = aon_adc_chn0_filter_ctl_6_max_v_6_qs_int; |
| aon_adc_chn0_filter_ctl_6_qs[31] = aon_adc_chn0_filter_ctl_6_en_6_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_6_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_6_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_6_busy), |
| .src_qs_o (adc_chn0_filter_ctl_6_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_6_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_6_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_6_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_6_wdata = |
| ^aon_adc_chn0_filter_ctl_6_wdata; |
| |
| logic [9:0] aon_adc_chn0_filter_ctl_7_min_v_7_qs_int; |
| logic aon_adc_chn0_filter_ctl_7_cond_7_qs_int; |
| logic [9:0] aon_adc_chn0_filter_ctl_7_max_v_7_qs_int; |
| logic aon_adc_chn0_filter_ctl_7_en_7_qs_int; |
| logic [31:0] aon_adc_chn0_filter_ctl_7_qs; |
| logic [31:0] aon_adc_chn0_filter_ctl_7_wdata; |
| logic aon_adc_chn0_filter_ctl_7_we; |
| logic unused_aon_adc_chn0_filter_ctl_7_wdata; |
| |
| always_comb begin |
| aon_adc_chn0_filter_ctl_7_qs = 32'h0; |
| aon_adc_chn0_filter_ctl_7_qs[11:2] = aon_adc_chn0_filter_ctl_7_min_v_7_qs_int; |
| aon_adc_chn0_filter_ctl_7_qs[12] = aon_adc_chn0_filter_ctl_7_cond_7_qs_int; |
| aon_adc_chn0_filter_ctl_7_qs[27:18] = aon_adc_chn0_filter_ctl_7_max_v_7_qs_int; |
| aon_adc_chn0_filter_ctl_7_qs[31] = aon_adc_chn0_filter_ctl_7_en_7_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn0_filter_ctl_7_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn0_filter_ctl_7_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn0_filter_ctl_7_busy), |
| .src_qs_o (adc_chn0_filter_ctl_7_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn0_filter_ctl_7_qs), |
| .dst_we_o (aon_adc_chn0_filter_ctl_7_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn0_filter_ctl_7_wdata) |
| ); |
| assign unused_aon_adc_chn0_filter_ctl_7_wdata = |
| ^aon_adc_chn0_filter_ctl_7_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_0_min_v_0_qs_int; |
| logic aon_adc_chn1_filter_ctl_0_cond_0_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_0_max_v_0_qs_int; |
| logic aon_adc_chn1_filter_ctl_0_en_0_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_0_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_0_wdata; |
| logic aon_adc_chn1_filter_ctl_0_we; |
| logic unused_aon_adc_chn1_filter_ctl_0_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_0_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_0_qs[11:2] = aon_adc_chn1_filter_ctl_0_min_v_0_qs_int; |
| aon_adc_chn1_filter_ctl_0_qs[12] = aon_adc_chn1_filter_ctl_0_cond_0_qs_int; |
| aon_adc_chn1_filter_ctl_0_qs[27:18] = aon_adc_chn1_filter_ctl_0_max_v_0_qs_int; |
| aon_adc_chn1_filter_ctl_0_qs[31] = aon_adc_chn1_filter_ctl_0_en_0_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_0_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_0_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_0_busy), |
| .src_qs_o (adc_chn1_filter_ctl_0_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_0_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_0_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_0_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_0_wdata = |
| ^aon_adc_chn1_filter_ctl_0_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_1_min_v_1_qs_int; |
| logic aon_adc_chn1_filter_ctl_1_cond_1_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_1_max_v_1_qs_int; |
| logic aon_adc_chn1_filter_ctl_1_en_1_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_1_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_1_wdata; |
| logic aon_adc_chn1_filter_ctl_1_we; |
| logic unused_aon_adc_chn1_filter_ctl_1_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_1_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_1_qs[11:2] = aon_adc_chn1_filter_ctl_1_min_v_1_qs_int; |
| aon_adc_chn1_filter_ctl_1_qs[12] = aon_adc_chn1_filter_ctl_1_cond_1_qs_int; |
| aon_adc_chn1_filter_ctl_1_qs[27:18] = aon_adc_chn1_filter_ctl_1_max_v_1_qs_int; |
| aon_adc_chn1_filter_ctl_1_qs[31] = aon_adc_chn1_filter_ctl_1_en_1_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_1_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_1_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_1_busy), |
| .src_qs_o (adc_chn1_filter_ctl_1_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_1_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_1_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_1_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_1_wdata = |
| ^aon_adc_chn1_filter_ctl_1_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_2_min_v_2_qs_int; |
| logic aon_adc_chn1_filter_ctl_2_cond_2_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_2_max_v_2_qs_int; |
| logic aon_adc_chn1_filter_ctl_2_en_2_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_2_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_2_wdata; |
| logic aon_adc_chn1_filter_ctl_2_we; |
| logic unused_aon_adc_chn1_filter_ctl_2_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_2_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_2_qs[11:2] = aon_adc_chn1_filter_ctl_2_min_v_2_qs_int; |
| aon_adc_chn1_filter_ctl_2_qs[12] = aon_adc_chn1_filter_ctl_2_cond_2_qs_int; |
| aon_adc_chn1_filter_ctl_2_qs[27:18] = aon_adc_chn1_filter_ctl_2_max_v_2_qs_int; |
| aon_adc_chn1_filter_ctl_2_qs[31] = aon_adc_chn1_filter_ctl_2_en_2_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_2_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_2_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_2_busy), |
| .src_qs_o (adc_chn1_filter_ctl_2_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_2_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_2_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_2_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_2_wdata = |
| ^aon_adc_chn1_filter_ctl_2_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_3_min_v_3_qs_int; |
| logic aon_adc_chn1_filter_ctl_3_cond_3_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_3_max_v_3_qs_int; |
| logic aon_adc_chn1_filter_ctl_3_en_3_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_3_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_3_wdata; |
| logic aon_adc_chn1_filter_ctl_3_we; |
| logic unused_aon_adc_chn1_filter_ctl_3_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_3_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_3_qs[11:2] = aon_adc_chn1_filter_ctl_3_min_v_3_qs_int; |
| aon_adc_chn1_filter_ctl_3_qs[12] = aon_adc_chn1_filter_ctl_3_cond_3_qs_int; |
| aon_adc_chn1_filter_ctl_3_qs[27:18] = aon_adc_chn1_filter_ctl_3_max_v_3_qs_int; |
| aon_adc_chn1_filter_ctl_3_qs[31] = aon_adc_chn1_filter_ctl_3_en_3_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_3_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_3_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_3_busy), |
| .src_qs_o (adc_chn1_filter_ctl_3_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_3_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_3_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_3_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_3_wdata = |
| ^aon_adc_chn1_filter_ctl_3_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_4_min_v_4_qs_int; |
| logic aon_adc_chn1_filter_ctl_4_cond_4_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_4_max_v_4_qs_int; |
| logic aon_adc_chn1_filter_ctl_4_en_4_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_4_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_4_wdata; |
| logic aon_adc_chn1_filter_ctl_4_we; |
| logic unused_aon_adc_chn1_filter_ctl_4_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_4_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_4_qs[11:2] = aon_adc_chn1_filter_ctl_4_min_v_4_qs_int; |
| aon_adc_chn1_filter_ctl_4_qs[12] = aon_adc_chn1_filter_ctl_4_cond_4_qs_int; |
| aon_adc_chn1_filter_ctl_4_qs[27:18] = aon_adc_chn1_filter_ctl_4_max_v_4_qs_int; |
| aon_adc_chn1_filter_ctl_4_qs[31] = aon_adc_chn1_filter_ctl_4_en_4_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_4_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_4_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_4_busy), |
| .src_qs_o (adc_chn1_filter_ctl_4_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_4_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_4_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_4_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_4_wdata = |
| ^aon_adc_chn1_filter_ctl_4_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_5_min_v_5_qs_int; |
| logic aon_adc_chn1_filter_ctl_5_cond_5_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_5_max_v_5_qs_int; |
| logic aon_adc_chn1_filter_ctl_5_en_5_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_5_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_5_wdata; |
| logic aon_adc_chn1_filter_ctl_5_we; |
| logic unused_aon_adc_chn1_filter_ctl_5_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_5_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_5_qs[11:2] = aon_adc_chn1_filter_ctl_5_min_v_5_qs_int; |
| aon_adc_chn1_filter_ctl_5_qs[12] = aon_adc_chn1_filter_ctl_5_cond_5_qs_int; |
| aon_adc_chn1_filter_ctl_5_qs[27:18] = aon_adc_chn1_filter_ctl_5_max_v_5_qs_int; |
| aon_adc_chn1_filter_ctl_5_qs[31] = aon_adc_chn1_filter_ctl_5_en_5_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_5_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_5_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_5_busy), |
| .src_qs_o (adc_chn1_filter_ctl_5_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_5_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_5_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_5_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_5_wdata = |
| ^aon_adc_chn1_filter_ctl_5_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_6_min_v_6_qs_int; |
| logic aon_adc_chn1_filter_ctl_6_cond_6_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_6_max_v_6_qs_int; |
| logic aon_adc_chn1_filter_ctl_6_en_6_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_6_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_6_wdata; |
| logic aon_adc_chn1_filter_ctl_6_we; |
| logic unused_aon_adc_chn1_filter_ctl_6_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_6_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_6_qs[11:2] = aon_adc_chn1_filter_ctl_6_min_v_6_qs_int; |
| aon_adc_chn1_filter_ctl_6_qs[12] = aon_adc_chn1_filter_ctl_6_cond_6_qs_int; |
| aon_adc_chn1_filter_ctl_6_qs[27:18] = aon_adc_chn1_filter_ctl_6_max_v_6_qs_int; |
| aon_adc_chn1_filter_ctl_6_qs[31] = aon_adc_chn1_filter_ctl_6_en_6_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_6_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_6_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_6_busy), |
| .src_qs_o (adc_chn1_filter_ctl_6_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_6_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_6_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_6_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_6_wdata = |
| ^aon_adc_chn1_filter_ctl_6_wdata; |
| |
| logic [9:0] aon_adc_chn1_filter_ctl_7_min_v_7_qs_int; |
| logic aon_adc_chn1_filter_ctl_7_cond_7_qs_int; |
| logic [9:0] aon_adc_chn1_filter_ctl_7_max_v_7_qs_int; |
| logic aon_adc_chn1_filter_ctl_7_en_7_qs_int; |
| logic [31:0] aon_adc_chn1_filter_ctl_7_qs; |
| logic [31:0] aon_adc_chn1_filter_ctl_7_wdata; |
| logic aon_adc_chn1_filter_ctl_7_we; |
| logic unused_aon_adc_chn1_filter_ctl_7_wdata; |
| |
| always_comb begin |
| aon_adc_chn1_filter_ctl_7_qs = 32'h0; |
| aon_adc_chn1_filter_ctl_7_qs[11:2] = aon_adc_chn1_filter_ctl_7_min_v_7_qs_int; |
| aon_adc_chn1_filter_ctl_7_qs[12] = aon_adc_chn1_filter_ctl_7_cond_7_qs_int; |
| aon_adc_chn1_filter_ctl_7_qs[27:18] = aon_adc_chn1_filter_ctl_7_max_v_7_qs_int; |
| aon_adc_chn1_filter_ctl_7_qs[31] = aon_adc_chn1_filter_ctl_7_en_7_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(32), |
| .ResetVal(32'h0), |
| .BitMask(32'h8ffc1ffc), |
| .DstWrReq(0) |
| ) u_adc_chn1_filter_ctl_7_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_chn1_filter_ctl_7_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[31:0]), |
| .src_busy_o (adc_chn1_filter_ctl_7_busy), |
| .src_qs_o (adc_chn1_filter_ctl_7_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_chn1_filter_ctl_7_qs), |
| .dst_we_o (aon_adc_chn1_filter_ctl_7_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_chn1_filter_ctl_7_wdata) |
| ); |
| assign unused_aon_adc_chn1_filter_ctl_7_wdata = |
| ^aon_adc_chn1_filter_ctl_7_wdata; |
| |
| logic [1:0] aon_adc_chn_val_0_adc_chn_value_ext_0_ds_int; |
| logic [1:0] aon_adc_chn_val_0_adc_chn_value_ext_0_qs_int; |
| logic [9:0] aon_adc_chn_val_0_adc_chn_value_0_ds_int; |
| logic [9:0] aon_adc_chn_val_0_adc_chn_value_0_qs_int; |
| logic [1:0] aon_adc_chn_val_0_adc_chn_value_intr_ext_0_ds_int; |
| logic [1:0] aon_adc_chn_val_0_adc_chn_value_intr_ext_0_qs_int; |
| logic [9:0] aon_adc_chn_val_0_adc_chn_value_intr_0_ds_int; |
| logic [9:0] aon_adc_chn_val_0_adc_chn_value_intr_0_qs_int; |
| logic [27:0] aon_adc_chn_val_0_ds; |
| logic aon_adc_chn_val_0_qe; |
| logic [27:0] aon_adc_chn_val_0_qs; |
| |
| always_comb begin |
| aon_adc_chn_val_0_qs = 28'h0; |
| aon_adc_chn_val_0_ds = 28'h0; |
| aon_adc_chn_val_0_ds[1:0] = aon_adc_chn_val_0_adc_chn_value_ext_0_ds_int; |
| aon_adc_chn_val_0_qs[1:0] = aon_adc_chn_val_0_adc_chn_value_ext_0_qs_int; |
| aon_adc_chn_val_0_ds[11:2] = aon_adc_chn_val_0_adc_chn_value_0_ds_int; |
| aon_adc_chn_val_0_qs[11:2] = aon_adc_chn_val_0_adc_chn_value_0_qs_int; |
| aon_adc_chn_val_0_ds[17:16] = aon_adc_chn_val_0_adc_chn_value_intr_ext_0_ds_int; |
| aon_adc_chn_val_0_qs[17:16] = aon_adc_chn_val_0_adc_chn_value_intr_ext_0_qs_int; |
| aon_adc_chn_val_0_ds[27:18] = aon_adc_chn_val_0_adc_chn_value_intr_0_ds_int; |
| aon_adc_chn_val_0_qs[27:18] = aon_adc_chn_val_0_adc_chn_value_intr_0_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(28), |
| .ResetVal(28'h0), |
| .BitMask(28'hfff0fff), |
| .DstWrReq(1) |
| ) u_adc_chn_val_0_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i ('0), |
| .src_re_i ('0), |
| .src_wd_i ('0), |
| .src_busy_o (adc_chn_val_0_busy), |
| .src_qs_o (adc_chn_val_0_qs), // for software read back |
| .dst_update_i (aon_adc_chn_val_0_qe), |
| .dst_ds_i (aon_adc_chn_val_0_ds), |
| .dst_qs_i (aon_adc_chn_val_0_qs), |
| .dst_we_o (), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o () |
| ); |
| |
| logic [1:0] aon_adc_chn_val_1_adc_chn_value_ext_1_ds_int; |
| logic [1:0] aon_adc_chn_val_1_adc_chn_value_ext_1_qs_int; |
| logic [9:0] aon_adc_chn_val_1_adc_chn_value_1_ds_int; |
| logic [9:0] aon_adc_chn_val_1_adc_chn_value_1_qs_int; |
| logic [1:0] aon_adc_chn_val_1_adc_chn_value_intr_ext_1_ds_int; |
| logic [1:0] aon_adc_chn_val_1_adc_chn_value_intr_ext_1_qs_int; |
| logic [9:0] aon_adc_chn_val_1_adc_chn_value_intr_1_ds_int; |
| logic [9:0] aon_adc_chn_val_1_adc_chn_value_intr_1_qs_int; |
| logic [27:0] aon_adc_chn_val_1_ds; |
| logic aon_adc_chn_val_1_qe; |
| logic [27:0] aon_adc_chn_val_1_qs; |
| |
| always_comb begin |
| aon_adc_chn_val_1_qs = 28'h0; |
| aon_adc_chn_val_1_ds = 28'h0; |
| aon_adc_chn_val_1_ds[1:0] = aon_adc_chn_val_1_adc_chn_value_ext_1_ds_int; |
| aon_adc_chn_val_1_qs[1:0] = aon_adc_chn_val_1_adc_chn_value_ext_1_qs_int; |
| aon_adc_chn_val_1_ds[11:2] = aon_adc_chn_val_1_adc_chn_value_1_ds_int; |
| aon_adc_chn_val_1_qs[11:2] = aon_adc_chn_val_1_adc_chn_value_1_qs_int; |
| aon_adc_chn_val_1_ds[17:16] = aon_adc_chn_val_1_adc_chn_value_intr_ext_1_ds_int; |
| aon_adc_chn_val_1_qs[17:16] = aon_adc_chn_val_1_adc_chn_value_intr_ext_1_qs_int; |
| aon_adc_chn_val_1_ds[27:18] = aon_adc_chn_val_1_adc_chn_value_intr_1_ds_int; |
| aon_adc_chn_val_1_qs[27:18] = aon_adc_chn_val_1_adc_chn_value_intr_1_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(28), |
| .ResetVal(28'h0), |
| .BitMask(28'hfff0fff), |
| .DstWrReq(1) |
| ) u_adc_chn_val_1_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i ('0), |
| .src_re_i ('0), |
| .src_wd_i ('0), |
| .src_busy_o (adc_chn_val_1_busy), |
| .src_qs_o (adc_chn_val_1_qs), // for software read back |
| .dst_update_i (aon_adc_chn_val_1_qe), |
| .dst_ds_i (aon_adc_chn_val_1_ds), |
| .dst_qs_i (aon_adc_chn_val_1_qs), |
| .dst_we_o (), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o () |
| ); |
| |
| logic [7:0] aon_adc_wakeup_ctl_qs_int; |
| logic [7:0] aon_adc_wakeup_ctl_qs; |
| logic [7:0] aon_adc_wakeup_ctl_wdata; |
| logic aon_adc_wakeup_ctl_we; |
| logic unused_aon_adc_wakeup_ctl_wdata; |
| |
| always_comb begin |
| aon_adc_wakeup_ctl_qs = 8'h0; |
| aon_adc_wakeup_ctl_qs = aon_adc_wakeup_ctl_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_adc_wakeup_ctl_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (adc_wakeup_ctl_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (adc_wakeup_ctl_busy), |
| .src_qs_o (adc_wakeup_ctl_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_adc_wakeup_ctl_qs), |
| .dst_we_o (aon_adc_wakeup_ctl_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_adc_wakeup_ctl_wdata) |
| ); |
| assign unused_aon_adc_wakeup_ctl_wdata = |
| ^aon_adc_wakeup_ctl_wdata; |
| |
| logic [7:0] aon_filter_status_ds_int; |
| logic [7:0] aon_filter_status_qs_int; |
| logic [7:0] aon_filter_status_ds; |
| logic aon_filter_status_qe; |
| logic [7:0] aon_filter_status_qs; |
| logic [7:0] aon_filter_status_wdata; |
| logic aon_filter_status_we; |
| logic unused_aon_filter_status_wdata; |
| |
| always_comb begin |
| aon_filter_status_qs = 8'h0; |
| aon_filter_status_ds = 8'h0; |
| aon_filter_status_ds = aon_filter_status_ds_int; |
| aon_filter_status_qs = aon_filter_status_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(1) |
| ) u_filter_status_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (filter_status_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (filter_status_busy), |
| .src_qs_o (filter_status_qs), // for software read back |
| .dst_update_i (aon_filter_status_qe), |
| .dst_ds_i (aon_filter_status_ds), |
| .dst_qs_i (aon_filter_status_qs), |
| .dst_we_o (aon_filter_status_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_filter_status_wdata) |
| ); |
| assign unused_aon_filter_status_wdata = |
| ^aon_filter_status_wdata; |
| |
| // Register instances |
| // R[intr_state]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.de), |
| .d (hw2reg.intr_state.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_qs) |
| ); |
| |
| |
| // R[intr_enable]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_qs) |
| ); |
| |
| |
| // R[intr_test]: V(True) |
| logic intr_test_qe; |
| logic [0:0] intr_test_flds_we; |
| assign intr_test_qe = &intr_test_flds_we; |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[0]), |
| .q (reg2hw.intr_test.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.qe = intr_test_qe; |
| |
| |
| // R[alert_test]: V(True) |
| logic alert_test_qe; |
| logic [0:0] alert_test_flds_we; |
| assign alert_test_qe = &alert_test_flds_we; |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[0]), |
| .q (reg2hw.alert_test.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.qe = alert_test_qe; |
| |
| |
| // R[adc_en_ctl]: V(False) |
| // F[adc_enable]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_en_ctl_adc_enable ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_en_ctl_we), |
| .wd (aon_adc_en_ctl_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_en_ctl.adc_enable.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_en_ctl_adc_enable_qs_int) |
| ); |
| |
| // F[oneshot_mode]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_en_ctl_oneshot_mode ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_en_ctl_we), |
| .wd (aon_adc_en_ctl_wdata[1]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_en_ctl.oneshot_mode.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_en_ctl_oneshot_mode_qs_int) |
| ); |
| |
| |
| // R[adc_pd_ctl]: V(False) |
| // F[lp_mode]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_pd_ctl_lp_mode ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_pd_ctl_we), |
| .wd (aon_adc_pd_ctl_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_pd_ctl.lp_mode.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_pd_ctl_lp_mode_qs_int) |
| ); |
| |
| // F[pwrup_time]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h6) |
| ) u_adc_pd_ctl_pwrup_time ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_pd_ctl_we), |
| .wd (aon_adc_pd_ctl_wdata[7:4]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_pd_ctl.pwrup_time.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_pd_ctl_pwrup_time_qs_int) |
| ); |
| |
| // F[wakeup_time]: 31:8 |
| prim_subreg #( |
| .DW (24), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (24'h640) |
| ) u_adc_pd_ctl_wakeup_time ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_pd_ctl_we), |
| .wd (aon_adc_pd_ctl_wdata[31:8]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_pd_ctl.wakeup_time.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_pd_ctl_wakeup_time_qs_int) |
| ); |
| |
| |
| // R[adc_lp_sample_ctl]: V(False) |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (8'h4) |
| ) u_adc_lp_sample_ctl ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_lp_sample_ctl_we), |
| .wd (aon_adc_lp_sample_ctl_wdata[7:0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_lp_sample_ctl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_lp_sample_ctl_qs_int) |
| ); |
| |
| |
| // R[adc_sample_ctl]: V(False) |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h9b) |
| ) u_adc_sample_ctl ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_sample_ctl_we), |
| .wd (aon_adc_sample_ctl_wdata[15:0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_sample_ctl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_sample_ctl_qs_int) |
| ); |
| |
| |
| // R[adc_fsm_rst]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_fsm_rst ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_fsm_rst_we), |
| .wd (aon_adc_fsm_rst_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_fsm_rst.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_fsm_rst_qs_int) |
| ); |
| |
| |
| // Subregister 0 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_0]: V(False) |
| // F[min_v_0]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_0_min_v_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_0_we), |
| .wd (aon_adc_chn0_filter_ctl_0_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[0].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_0_min_v_0_qs_int) |
| ); |
| |
| // F[cond_0]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_0_cond_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_0_we), |
| .wd (aon_adc_chn0_filter_ctl_0_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[0].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_0_cond_0_qs_int) |
| ); |
| |
| // F[max_v_0]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_0_max_v_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_0_we), |
| .wd (aon_adc_chn0_filter_ctl_0_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[0].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_0_max_v_0_qs_int) |
| ); |
| |
| // F[en_0]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_0_en_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_0_we), |
| .wd (aon_adc_chn0_filter_ctl_0_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[0].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_0_en_0_qs_int) |
| ); |
| |
| |
| // Subregister 1 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_1]: V(False) |
| // F[min_v_1]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_1_min_v_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_1_we), |
| .wd (aon_adc_chn0_filter_ctl_1_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[1].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_1_min_v_1_qs_int) |
| ); |
| |
| // F[cond_1]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_1_cond_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_1_we), |
| .wd (aon_adc_chn0_filter_ctl_1_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[1].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_1_cond_1_qs_int) |
| ); |
| |
| // F[max_v_1]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_1_max_v_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_1_we), |
| .wd (aon_adc_chn0_filter_ctl_1_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[1].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_1_max_v_1_qs_int) |
| ); |
| |
| // F[en_1]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_1_en_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_1_we), |
| .wd (aon_adc_chn0_filter_ctl_1_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[1].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_1_en_1_qs_int) |
| ); |
| |
| |
| // Subregister 2 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_2]: V(False) |
| // F[min_v_2]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_2_min_v_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_2_we), |
| .wd (aon_adc_chn0_filter_ctl_2_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[2].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_2_min_v_2_qs_int) |
| ); |
| |
| // F[cond_2]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_2_cond_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_2_we), |
| .wd (aon_adc_chn0_filter_ctl_2_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[2].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_2_cond_2_qs_int) |
| ); |
| |
| // F[max_v_2]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_2_max_v_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_2_we), |
| .wd (aon_adc_chn0_filter_ctl_2_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[2].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_2_max_v_2_qs_int) |
| ); |
| |
| // F[en_2]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_2_en_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_2_we), |
| .wd (aon_adc_chn0_filter_ctl_2_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[2].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_2_en_2_qs_int) |
| ); |
| |
| |
| // Subregister 3 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_3]: V(False) |
| // F[min_v_3]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_3_min_v_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_3_we), |
| .wd (aon_adc_chn0_filter_ctl_3_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[3].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_3_min_v_3_qs_int) |
| ); |
| |
| // F[cond_3]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_3_cond_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_3_we), |
| .wd (aon_adc_chn0_filter_ctl_3_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[3].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_3_cond_3_qs_int) |
| ); |
| |
| // F[max_v_3]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_3_max_v_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_3_we), |
| .wd (aon_adc_chn0_filter_ctl_3_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[3].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_3_max_v_3_qs_int) |
| ); |
| |
| // F[en_3]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_3_en_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_3_we), |
| .wd (aon_adc_chn0_filter_ctl_3_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[3].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_3_en_3_qs_int) |
| ); |
| |
| |
| // Subregister 4 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_4]: V(False) |
| // F[min_v_4]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_4_min_v_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_4_we), |
| .wd (aon_adc_chn0_filter_ctl_4_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[4].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_4_min_v_4_qs_int) |
| ); |
| |
| // F[cond_4]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_4_cond_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_4_we), |
| .wd (aon_adc_chn0_filter_ctl_4_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[4].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_4_cond_4_qs_int) |
| ); |
| |
| // F[max_v_4]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_4_max_v_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_4_we), |
| .wd (aon_adc_chn0_filter_ctl_4_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[4].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_4_max_v_4_qs_int) |
| ); |
| |
| // F[en_4]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_4_en_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_4_we), |
| .wd (aon_adc_chn0_filter_ctl_4_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[4].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_4_en_4_qs_int) |
| ); |
| |
| |
| // Subregister 5 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_5]: V(False) |
| // F[min_v_5]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_5_min_v_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_5_we), |
| .wd (aon_adc_chn0_filter_ctl_5_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[5].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_5_min_v_5_qs_int) |
| ); |
| |
| // F[cond_5]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_5_cond_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_5_we), |
| .wd (aon_adc_chn0_filter_ctl_5_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[5].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_5_cond_5_qs_int) |
| ); |
| |
| // F[max_v_5]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_5_max_v_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_5_we), |
| .wd (aon_adc_chn0_filter_ctl_5_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[5].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_5_max_v_5_qs_int) |
| ); |
| |
| // F[en_5]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_5_en_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_5_we), |
| .wd (aon_adc_chn0_filter_ctl_5_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[5].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_5_en_5_qs_int) |
| ); |
| |
| |
| // Subregister 6 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_6]: V(False) |
| // F[min_v_6]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_6_min_v_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_6_we), |
| .wd (aon_adc_chn0_filter_ctl_6_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[6].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_6_min_v_6_qs_int) |
| ); |
| |
| // F[cond_6]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_6_cond_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_6_we), |
| .wd (aon_adc_chn0_filter_ctl_6_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[6].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_6_cond_6_qs_int) |
| ); |
| |
| // F[max_v_6]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_6_max_v_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_6_we), |
| .wd (aon_adc_chn0_filter_ctl_6_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[6].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_6_max_v_6_qs_int) |
| ); |
| |
| // F[en_6]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_6_en_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_6_we), |
| .wd (aon_adc_chn0_filter_ctl_6_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[6].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_6_en_6_qs_int) |
| ); |
| |
| |
| // Subregister 7 of Multireg adc_chn0_filter_ctl |
| // R[adc_chn0_filter_ctl_7]: V(False) |
| // F[min_v_7]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_7_min_v_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_7_we), |
| .wd (aon_adc_chn0_filter_ctl_7_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[7].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_7_min_v_7_qs_int) |
| ); |
| |
| // F[cond_7]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_7_cond_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_7_we), |
| .wd (aon_adc_chn0_filter_ctl_7_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[7].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_7_cond_7_qs_int) |
| ); |
| |
| // F[max_v_7]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn0_filter_ctl_7_max_v_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_7_we), |
| .wd (aon_adc_chn0_filter_ctl_7_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[7].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_7_max_v_7_qs_int) |
| ); |
| |
| // F[en_7]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn0_filter_ctl_7_en_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn0_filter_ctl_7_we), |
| .wd (aon_adc_chn0_filter_ctl_7_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn0_filter_ctl[7].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn0_filter_ctl_7_en_7_qs_int) |
| ); |
| |
| |
| // Subregister 0 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_0]: V(False) |
| // F[min_v_0]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_0_min_v_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_0_we), |
| .wd (aon_adc_chn1_filter_ctl_0_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[0].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_0_min_v_0_qs_int) |
| ); |
| |
| // F[cond_0]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_0_cond_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_0_we), |
| .wd (aon_adc_chn1_filter_ctl_0_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[0].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_0_cond_0_qs_int) |
| ); |
| |
| // F[max_v_0]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_0_max_v_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_0_we), |
| .wd (aon_adc_chn1_filter_ctl_0_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[0].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_0_max_v_0_qs_int) |
| ); |
| |
| // F[en_0]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_0_en_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_0_we), |
| .wd (aon_adc_chn1_filter_ctl_0_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[0].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_0_en_0_qs_int) |
| ); |
| |
| |
| // Subregister 1 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_1]: V(False) |
| // F[min_v_1]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_1_min_v_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_1_we), |
| .wd (aon_adc_chn1_filter_ctl_1_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[1].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_1_min_v_1_qs_int) |
| ); |
| |
| // F[cond_1]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_1_cond_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_1_we), |
| .wd (aon_adc_chn1_filter_ctl_1_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[1].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_1_cond_1_qs_int) |
| ); |
| |
| // F[max_v_1]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_1_max_v_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_1_we), |
| .wd (aon_adc_chn1_filter_ctl_1_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[1].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_1_max_v_1_qs_int) |
| ); |
| |
| // F[en_1]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_1_en_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_1_we), |
| .wd (aon_adc_chn1_filter_ctl_1_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[1].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_1_en_1_qs_int) |
| ); |
| |
| |
| // Subregister 2 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_2]: V(False) |
| // F[min_v_2]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_2_min_v_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_2_we), |
| .wd (aon_adc_chn1_filter_ctl_2_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[2].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_2_min_v_2_qs_int) |
| ); |
| |
| // F[cond_2]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_2_cond_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_2_we), |
| .wd (aon_adc_chn1_filter_ctl_2_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[2].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_2_cond_2_qs_int) |
| ); |
| |
| // F[max_v_2]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_2_max_v_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_2_we), |
| .wd (aon_adc_chn1_filter_ctl_2_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[2].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_2_max_v_2_qs_int) |
| ); |
| |
| // F[en_2]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_2_en_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_2_we), |
| .wd (aon_adc_chn1_filter_ctl_2_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[2].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_2_en_2_qs_int) |
| ); |
| |
| |
| // Subregister 3 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_3]: V(False) |
| // F[min_v_3]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_3_min_v_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_3_we), |
| .wd (aon_adc_chn1_filter_ctl_3_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[3].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_3_min_v_3_qs_int) |
| ); |
| |
| // F[cond_3]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_3_cond_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_3_we), |
| .wd (aon_adc_chn1_filter_ctl_3_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[3].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_3_cond_3_qs_int) |
| ); |
| |
| // F[max_v_3]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_3_max_v_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_3_we), |
| .wd (aon_adc_chn1_filter_ctl_3_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[3].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_3_max_v_3_qs_int) |
| ); |
| |
| // F[en_3]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_3_en_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_3_we), |
| .wd (aon_adc_chn1_filter_ctl_3_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[3].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_3_en_3_qs_int) |
| ); |
| |
| |
| // Subregister 4 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_4]: V(False) |
| // F[min_v_4]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_4_min_v_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_4_we), |
| .wd (aon_adc_chn1_filter_ctl_4_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[4].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_4_min_v_4_qs_int) |
| ); |
| |
| // F[cond_4]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_4_cond_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_4_we), |
| .wd (aon_adc_chn1_filter_ctl_4_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[4].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_4_cond_4_qs_int) |
| ); |
| |
| // F[max_v_4]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_4_max_v_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_4_we), |
| .wd (aon_adc_chn1_filter_ctl_4_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[4].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_4_max_v_4_qs_int) |
| ); |
| |
| // F[en_4]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_4_en_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_4_we), |
| .wd (aon_adc_chn1_filter_ctl_4_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[4].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_4_en_4_qs_int) |
| ); |
| |
| |
| // Subregister 5 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_5]: V(False) |
| // F[min_v_5]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_5_min_v_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_5_we), |
| .wd (aon_adc_chn1_filter_ctl_5_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[5].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_5_min_v_5_qs_int) |
| ); |
| |
| // F[cond_5]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_5_cond_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_5_we), |
| .wd (aon_adc_chn1_filter_ctl_5_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[5].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_5_cond_5_qs_int) |
| ); |
| |
| // F[max_v_5]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_5_max_v_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_5_we), |
| .wd (aon_adc_chn1_filter_ctl_5_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[5].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_5_max_v_5_qs_int) |
| ); |
| |
| // F[en_5]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_5_en_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_5_we), |
| .wd (aon_adc_chn1_filter_ctl_5_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[5].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_5_en_5_qs_int) |
| ); |
| |
| |
| // Subregister 6 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_6]: V(False) |
| // F[min_v_6]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_6_min_v_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_6_we), |
| .wd (aon_adc_chn1_filter_ctl_6_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[6].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_6_min_v_6_qs_int) |
| ); |
| |
| // F[cond_6]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_6_cond_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_6_we), |
| .wd (aon_adc_chn1_filter_ctl_6_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[6].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_6_cond_6_qs_int) |
| ); |
| |
| // F[max_v_6]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_6_max_v_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_6_we), |
| .wd (aon_adc_chn1_filter_ctl_6_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[6].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_6_max_v_6_qs_int) |
| ); |
| |
| // F[en_6]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_6_en_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_6_we), |
| .wd (aon_adc_chn1_filter_ctl_6_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[6].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_6_en_6_qs_int) |
| ); |
| |
| |
| // Subregister 7 of Multireg adc_chn1_filter_ctl |
| // R[adc_chn1_filter_ctl_7]: V(False) |
| // F[min_v_7]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_7_min_v_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_7_we), |
| .wd (aon_adc_chn1_filter_ctl_7_wdata[11:2]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[7].min_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_7_min_v_7_qs_int) |
| ); |
| |
| // F[cond_7]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_7_cond_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_7_we), |
| .wd (aon_adc_chn1_filter_ctl_7_wdata[12]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[7].cond.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_7_cond_7_qs_int) |
| ); |
| |
| // F[max_v_7]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_adc_chn1_filter_ctl_7_max_v_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_7_we), |
| .wd (aon_adc_chn1_filter_ctl_7_wdata[27:18]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[7].max_v.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_7_max_v_7_qs_int) |
| ); |
| |
| // F[en_7]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_adc_chn1_filter_ctl_7_en_7 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_chn1_filter_ctl_7_we), |
| .wd (aon_adc_chn1_filter_ctl_7_wdata[31]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_chn1_filter_ctl[7].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn1_filter_ctl_7_en_7_qs_int) |
| ); |
| |
| |
| // Subregister 0 of Multireg adc_chn_val |
| // R[adc_chn_val_0]: V(False) |
| logic [3:0] adc_chn_val_0_flds_we; |
| assign aon_adc_chn_val_0_qe = |adc_chn_val_0_flds_we; |
| // F[adc_chn_value_ext_0]: 1:0 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (2'h0) |
| ) u_adc_chn_val_0_adc_chn_value_ext_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[0].adc_chn_value_ext.de), |
| .d (hw2reg.adc_chn_val[0].adc_chn_value_ext.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_0_flds_we[0]), |
| .q (), |
| .ds (aon_adc_chn_val_0_adc_chn_value_ext_0_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_0_adc_chn_value_ext_0_qs_int) |
| ); |
| |
| // F[adc_chn_value_0]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (10'h0) |
| ) u_adc_chn_val_0_adc_chn_value_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[0].adc_chn_value.de), |
| .d (hw2reg.adc_chn_val[0].adc_chn_value.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_0_flds_we[1]), |
| .q (), |
| .ds (aon_adc_chn_val_0_adc_chn_value_0_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_0_adc_chn_value_0_qs_int) |
| ); |
| |
| // F[adc_chn_value_intr_ext_0]: 17:16 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (2'h0) |
| ) u_adc_chn_val_0_adc_chn_value_intr_ext_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[0].adc_chn_value_intr_ext.de), |
| .d (hw2reg.adc_chn_val[0].adc_chn_value_intr_ext.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_0_flds_we[2]), |
| .q (), |
| .ds (aon_adc_chn_val_0_adc_chn_value_intr_ext_0_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_0_adc_chn_value_intr_ext_0_qs_int) |
| ); |
| |
| // F[adc_chn_value_intr_0]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (10'h0) |
| ) u_adc_chn_val_0_adc_chn_value_intr_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[0].adc_chn_value_intr.de), |
| .d (hw2reg.adc_chn_val[0].adc_chn_value_intr.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_0_flds_we[3]), |
| .q (), |
| .ds (aon_adc_chn_val_0_adc_chn_value_intr_0_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_0_adc_chn_value_intr_0_qs_int) |
| ); |
| |
| |
| // Subregister 1 of Multireg adc_chn_val |
| // R[adc_chn_val_1]: V(False) |
| logic [3:0] adc_chn_val_1_flds_we; |
| assign aon_adc_chn_val_1_qe = |adc_chn_val_1_flds_we; |
| // F[adc_chn_value_ext_1]: 1:0 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (2'h0) |
| ) u_adc_chn_val_1_adc_chn_value_ext_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[1].adc_chn_value_ext.de), |
| .d (hw2reg.adc_chn_val[1].adc_chn_value_ext.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_1_flds_we[0]), |
| .q (), |
| .ds (aon_adc_chn_val_1_adc_chn_value_ext_1_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_1_adc_chn_value_ext_1_qs_int) |
| ); |
| |
| // F[adc_chn_value_1]: 11:2 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (10'h0) |
| ) u_adc_chn_val_1_adc_chn_value_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[1].adc_chn_value.de), |
| .d (hw2reg.adc_chn_val[1].adc_chn_value.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_1_flds_we[1]), |
| .q (), |
| .ds (aon_adc_chn_val_1_adc_chn_value_1_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_1_adc_chn_value_1_qs_int) |
| ); |
| |
| // F[adc_chn_value_intr_ext_1]: 17:16 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (2'h0) |
| ) u_adc_chn_val_1_adc_chn_value_intr_ext_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[1].adc_chn_value_intr_ext.de), |
| .d (hw2reg.adc_chn_val[1].adc_chn_value_intr_ext.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_1_flds_we[2]), |
| .q (), |
| .ds (aon_adc_chn_val_1_adc_chn_value_intr_ext_1_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_1_adc_chn_value_intr_ext_1_qs_int) |
| ); |
| |
| // F[adc_chn_value_intr_1]: 27:18 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (10'h0) |
| ) u_adc_chn_val_1_adc_chn_value_intr_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.adc_chn_val[1].adc_chn_value_intr.de), |
| .d (hw2reg.adc_chn_val[1].adc_chn_value_intr.d), |
| |
| // to internal hardware |
| .qe (adc_chn_val_1_flds_we[3]), |
| .q (), |
| .ds (aon_adc_chn_val_1_adc_chn_value_intr_1_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_adc_chn_val_1_adc_chn_value_intr_1_qs_int) |
| ); |
| |
| |
| // R[adc_wakeup_ctl]: V(False) |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (8'h0) |
| ) u_adc_wakeup_ctl ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_adc_wakeup_ctl_we), |
| .wd (aon_adc_wakeup_ctl_wdata[7:0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_wakeup_ctl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_adc_wakeup_ctl_qs_int) |
| ); |
| |
| |
| // R[filter_status]: V(False) |
| logic [0:0] filter_status_flds_we; |
| assign aon_filter_status_qe = |filter_status_flds_we; |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (8'h0) |
| ) u_filter_status ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_filter_status_we), |
| .wd (aon_filter_status_wdata[7:0]), |
| |
| // from internal hardware |
| .de (hw2reg.filter_status.de), |
| .d (hw2reg.filter_status.d), |
| |
| // to internal hardware |
| .qe (filter_status_flds_we[0]), |
| .q (reg2hw.filter_status.q), |
| .ds (aon_filter_status_ds_int), |
| |
| // to register interface (read) |
| .qs (aon_filter_status_qs_int) |
| ); |
| |
| |
| // R[adc_intr_ctl]: V(False) |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_adc_intr_ctl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (adc_intr_ctl_we), |
| .wd (adc_intr_ctl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_intr_ctl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (adc_intr_ctl_qs) |
| ); |
| |
| |
| // R[adc_intr_status]: V(False) |
| // F[filter_match]: 7:0 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (8'h0) |
| ) u_adc_intr_status_filter_match ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (adc_intr_status_we), |
| .wd (adc_intr_status_filter_match_wd), |
| |
| // from internal hardware |
| .de (hw2reg.adc_intr_status.filter_match.de), |
| .d (hw2reg.adc_intr_status.filter_match.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_intr_status.filter_match.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (adc_intr_status_filter_match_qs) |
| ); |
| |
| // F[oneshot]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_adc_intr_status_oneshot ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (adc_intr_status_we), |
| .wd (adc_intr_status_oneshot_wd), |
| |
| // from internal hardware |
| .de (hw2reg.adc_intr_status.oneshot.de), |
| .d (hw2reg.adc_intr_status.oneshot.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.adc_intr_status.oneshot.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (adc_intr_status_oneshot_qs) |
| ); |
| |
| |
| |
| logic [30:0] addr_hit; |
| always_comb begin |
| addr_hit = '0; |
| addr_hit[ 0] = (reg_addr == ADC_CTRL_INTR_STATE_OFFSET); |
| addr_hit[ 1] = (reg_addr == ADC_CTRL_INTR_ENABLE_OFFSET); |
| addr_hit[ 2] = (reg_addr == ADC_CTRL_INTR_TEST_OFFSET); |
| addr_hit[ 3] = (reg_addr == ADC_CTRL_ALERT_TEST_OFFSET); |
| addr_hit[ 4] = (reg_addr == ADC_CTRL_ADC_EN_CTL_OFFSET); |
| addr_hit[ 5] = (reg_addr == ADC_CTRL_ADC_PD_CTL_OFFSET); |
| addr_hit[ 6] = (reg_addr == ADC_CTRL_ADC_LP_SAMPLE_CTL_OFFSET); |
| addr_hit[ 7] = (reg_addr == ADC_CTRL_ADC_SAMPLE_CTL_OFFSET); |
| addr_hit[ 8] = (reg_addr == ADC_CTRL_ADC_FSM_RST_OFFSET); |
| addr_hit[ 9] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_0_OFFSET); |
| addr_hit[10] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_1_OFFSET); |
| addr_hit[11] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_2_OFFSET); |
| addr_hit[12] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_3_OFFSET); |
| addr_hit[13] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_4_OFFSET); |
| addr_hit[14] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_5_OFFSET); |
| addr_hit[15] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_6_OFFSET); |
| addr_hit[16] = (reg_addr == ADC_CTRL_ADC_CHN0_FILTER_CTL_7_OFFSET); |
| addr_hit[17] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_0_OFFSET); |
| addr_hit[18] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_1_OFFSET); |
| addr_hit[19] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_2_OFFSET); |
| addr_hit[20] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_3_OFFSET); |
| addr_hit[21] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_4_OFFSET); |
| addr_hit[22] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_5_OFFSET); |
| addr_hit[23] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_6_OFFSET); |
| addr_hit[24] = (reg_addr == ADC_CTRL_ADC_CHN1_FILTER_CTL_7_OFFSET); |
| addr_hit[25] = (reg_addr == ADC_CTRL_ADC_CHN_VAL_0_OFFSET); |
| addr_hit[26] = (reg_addr == ADC_CTRL_ADC_CHN_VAL_1_OFFSET); |
| addr_hit[27] = (reg_addr == ADC_CTRL_ADC_WAKEUP_CTL_OFFSET); |
| addr_hit[28] = (reg_addr == ADC_CTRL_FILTER_STATUS_OFFSET); |
| addr_hit[29] = (reg_addr == ADC_CTRL_ADC_INTR_CTL_OFFSET); |
| addr_hit[30] = (reg_addr == ADC_CTRL_ADC_INTR_STATUS_OFFSET); |
| end |
| |
| assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; |
| |
| // Check sub-word write is permitted |
| always_comb begin |
| wr_err = (reg_we & |
| ((addr_hit[ 0] & (|(ADC_CTRL_PERMIT[ 0] & ~reg_be))) | |
| (addr_hit[ 1] & (|(ADC_CTRL_PERMIT[ 1] & ~reg_be))) | |
| (addr_hit[ 2] & (|(ADC_CTRL_PERMIT[ 2] & ~reg_be))) | |
| (addr_hit[ 3] & (|(ADC_CTRL_PERMIT[ 3] & ~reg_be))) | |
| (addr_hit[ 4] & (|(ADC_CTRL_PERMIT[ 4] & ~reg_be))) | |
| (addr_hit[ 5] & (|(ADC_CTRL_PERMIT[ 5] & ~reg_be))) | |
| (addr_hit[ 6] & (|(ADC_CTRL_PERMIT[ 6] & ~reg_be))) | |
| (addr_hit[ 7] & (|(ADC_CTRL_PERMIT[ 7] & ~reg_be))) | |
| (addr_hit[ 8] & (|(ADC_CTRL_PERMIT[ 8] & ~reg_be))) | |
| (addr_hit[ 9] & (|(ADC_CTRL_PERMIT[ 9] & ~reg_be))) | |
| (addr_hit[10] & (|(ADC_CTRL_PERMIT[10] & ~reg_be))) | |
| (addr_hit[11] & (|(ADC_CTRL_PERMIT[11] & ~reg_be))) | |
| (addr_hit[12] & (|(ADC_CTRL_PERMIT[12] & ~reg_be))) | |
| (addr_hit[13] & (|(ADC_CTRL_PERMIT[13] & ~reg_be))) | |
| (addr_hit[14] & (|(ADC_CTRL_PERMIT[14] & ~reg_be))) | |
| (addr_hit[15] & (|(ADC_CTRL_PERMIT[15] & ~reg_be))) | |
| (addr_hit[16] & (|(ADC_CTRL_PERMIT[16] & ~reg_be))) | |
| (addr_hit[17] & (|(ADC_CTRL_PERMIT[17] & ~reg_be))) | |
| (addr_hit[18] & (|(ADC_CTRL_PERMIT[18] & ~reg_be))) | |
| (addr_hit[19] & (|(ADC_CTRL_PERMIT[19] & ~reg_be))) | |
| (addr_hit[20] & (|(ADC_CTRL_PERMIT[20] & ~reg_be))) | |
| (addr_hit[21] & (|(ADC_CTRL_PERMIT[21] & ~reg_be))) | |
| (addr_hit[22] & (|(ADC_CTRL_PERMIT[22] & ~reg_be))) | |
| (addr_hit[23] & (|(ADC_CTRL_PERMIT[23] & ~reg_be))) | |
| (addr_hit[24] & (|(ADC_CTRL_PERMIT[24] & ~reg_be))) | |
| (addr_hit[25] & (|(ADC_CTRL_PERMIT[25] & ~reg_be))) | |
| (addr_hit[26] & (|(ADC_CTRL_PERMIT[26] & ~reg_be))) | |
| (addr_hit[27] & (|(ADC_CTRL_PERMIT[27] & ~reg_be))) | |
| (addr_hit[28] & (|(ADC_CTRL_PERMIT[28] & ~reg_be))) | |
| (addr_hit[29] & (|(ADC_CTRL_PERMIT[29] & ~reg_be))) | |
| (addr_hit[30] & (|(ADC_CTRL_PERMIT[30] & ~reg_be))))); |
| end |
| |
| // Generate write-enables |
| assign intr_state_we = addr_hit[0] & reg_we & !reg_error; |
| |
| assign intr_state_wd = reg_wdata[0]; |
| assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; |
| |
| assign intr_enable_wd = reg_wdata[0]; |
| assign intr_test_we = addr_hit[2] & reg_we & !reg_error; |
| |
| assign intr_test_wd = reg_wdata[0]; |
| assign alert_test_we = addr_hit[3] & reg_we & !reg_error; |
| |
| assign alert_test_wd = reg_wdata[0]; |
| assign adc_en_ctl_we = addr_hit[4] & reg_we & !reg_error; |
| |
| |
| assign adc_pd_ctl_we = addr_hit[5] & reg_we & !reg_error; |
| |
| |
| |
| assign adc_lp_sample_ctl_we = addr_hit[6] & reg_we & !reg_error; |
| |
| assign adc_sample_ctl_we = addr_hit[7] & reg_we & !reg_error; |
| |
| assign adc_fsm_rst_we = addr_hit[8] & reg_we & !reg_error; |
| |
| assign adc_chn0_filter_ctl_0_we = addr_hit[9] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_1_we = addr_hit[10] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_2_we = addr_hit[11] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_3_we = addr_hit[12] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_4_we = addr_hit[13] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_5_we = addr_hit[14] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_6_we = addr_hit[15] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn0_filter_ctl_7_we = addr_hit[16] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_0_we = addr_hit[17] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_1_we = addr_hit[18] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_2_we = addr_hit[19] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_3_we = addr_hit[20] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_4_we = addr_hit[21] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_5_we = addr_hit[22] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_6_we = addr_hit[23] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_chn1_filter_ctl_7_we = addr_hit[24] & reg_we & !reg_error; |
| |
| |
| |
| |
| assign adc_wakeup_ctl_we = addr_hit[27] & reg_we & !reg_error; |
| |
| assign filter_status_we = addr_hit[28] & reg_we & !reg_error; |
| |
| assign adc_intr_ctl_we = addr_hit[29] & reg_we & !reg_error; |
| |
| assign adc_intr_ctl_wd = reg_wdata[8:0]; |
| assign adc_intr_status_we = addr_hit[30] & reg_we & !reg_error; |
| |
| assign adc_intr_status_filter_match_wd = reg_wdata[7:0]; |
| |
| assign adc_intr_status_oneshot_wd = reg_wdata[8]; |
| |
| // Assign write-enables to checker logic vector. |
| always_comb begin |
| reg_we_check = '0; |
| reg_we_check[0] = intr_state_we; |
| reg_we_check[1] = intr_enable_we; |
| reg_we_check[2] = intr_test_we; |
| reg_we_check[3] = alert_test_we; |
| reg_we_check[4] = adc_en_ctl_we; |
| reg_we_check[5] = adc_pd_ctl_we; |
| reg_we_check[6] = adc_lp_sample_ctl_we; |
| reg_we_check[7] = adc_sample_ctl_we; |
| reg_we_check[8] = adc_fsm_rst_we; |
| reg_we_check[9] = adc_chn0_filter_ctl_0_we; |
| reg_we_check[10] = adc_chn0_filter_ctl_1_we; |
| reg_we_check[11] = adc_chn0_filter_ctl_2_we; |
| reg_we_check[12] = adc_chn0_filter_ctl_3_we; |
| reg_we_check[13] = adc_chn0_filter_ctl_4_we; |
| reg_we_check[14] = adc_chn0_filter_ctl_5_we; |
| reg_we_check[15] = adc_chn0_filter_ctl_6_we; |
| reg_we_check[16] = adc_chn0_filter_ctl_7_we; |
| reg_we_check[17] = adc_chn1_filter_ctl_0_we; |
| reg_we_check[18] = adc_chn1_filter_ctl_1_we; |
| reg_we_check[19] = adc_chn1_filter_ctl_2_we; |
| reg_we_check[20] = adc_chn1_filter_ctl_3_we; |
| reg_we_check[21] = adc_chn1_filter_ctl_4_we; |
| reg_we_check[22] = adc_chn1_filter_ctl_5_we; |
| reg_we_check[23] = adc_chn1_filter_ctl_6_we; |
| reg_we_check[24] = adc_chn1_filter_ctl_7_we; |
| reg_we_check[25] = 1'b0; |
| reg_we_check[26] = 1'b0; |
| reg_we_check[27] = adc_wakeup_ctl_we; |
| reg_we_check[28] = filter_status_we; |
| reg_we_check[29] = adc_intr_ctl_we; |
| reg_we_check[30] = adc_intr_status_we; |
| end |
| |
| // Read data return |
| always_comb begin |
| reg_rdata_next = '0; |
| unique case (1'b1) |
| addr_hit[0]: begin |
| reg_rdata_next[0] = intr_state_qs; |
| end |
| |
| addr_hit[1]: begin |
| reg_rdata_next[0] = intr_enable_qs; |
| end |
| |
| addr_hit[2]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[3]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[4]: begin |
| reg_rdata_next = DW'(adc_en_ctl_qs); |
| end |
| addr_hit[5]: begin |
| reg_rdata_next = DW'(adc_pd_ctl_qs); |
| end |
| addr_hit[6]: begin |
| reg_rdata_next = DW'(adc_lp_sample_ctl_qs); |
| end |
| addr_hit[7]: begin |
| reg_rdata_next = DW'(adc_sample_ctl_qs); |
| end |
| addr_hit[8]: begin |
| reg_rdata_next = DW'(adc_fsm_rst_qs); |
| end |
| addr_hit[9]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_0_qs); |
| end |
| addr_hit[10]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_1_qs); |
| end |
| addr_hit[11]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_2_qs); |
| end |
| addr_hit[12]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_3_qs); |
| end |
| addr_hit[13]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_4_qs); |
| end |
| addr_hit[14]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_5_qs); |
| end |
| addr_hit[15]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_6_qs); |
| end |
| addr_hit[16]: begin |
| reg_rdata_next = DW'(adc_chn0_filter_ctl_7_qs); |
| end |
| addr_hit[17]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_0_qs); |
| end |
| addr_hit[18]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_1_qs); |
| end |
| addr_hit[19]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_2_qs); |
| end |
| addr_hit[20]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_3_qs); |
| end |
| addr_hit[21]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_4_qs); |
| end |
| addr_hit[22]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_5_qs); |
| end |
| addr_hit[23]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_6_qs); |
| end |
| addr_hit[24]: begin |
| reg_rdata_next = DW'(adc_chn1_filter_ctl_7_qs); |
| end |
| addr_hit[25]: begin |
| reg_rdata_next = DW'(adc_chn_val_0_qs); |
| end |
| addr_hit[26]: begin |
| reg_rdata_next = DW'(adc_chn_val_1_qs); |
| end |
| addr_hit[27]: begin |
| reg_rdata_next = DW'(adc_wakeup_ctl_qs); |
| end |
| addr_hit[28]: begin |
| reg_rdata_next = DW'(filter_status_qs); |
| end |
| addr_hit[29]: begin |
| reg_rdata_next[8:0] = adc_intr_ctl_qs; |
| end |
| |
| addr_hit[30]: begin |
| reg_rdata_next[7:0] = adc_intr_status_filter_match_qs; |
| reg_rdata_next[8] = adc_intr_status_oneshot_qs; |
| end |
| |
| default: begin |
| reg_rdata_next = '1; |
| end |
| endcase |
| end |
| |
| // shadow busy |
| logic shadow_busy; |
| assign shadow_busy = 1'b0; |
| |
| // register busy |
| logic reg_busy_sel; |
| assign reg_busy = reg_busy_sel | shadow_busy; |
| always_comb begin |
| reg_busy_sel = '0; |
| unique case (1'b1) |
| addr_hit[4]: begin |
| reg_busy_sel = adc_en_ctl_busy; |
| end |
| addr_hit[5]: begin |
| reg_busy_sel = adc_pd_ctl_busy; |
| end |
| addr_hit[6]: begin |
| reg_busy_sel = adc_lp_sample_ctl_busy; |
| end |
| addr_hit[7]: begin |
| reg_busy_sel = adc_sample_ctl_busy; |
| end |
| addr_hit[8]: begin |
| reg_busy_sel = adc_fsm_rst_busy; |
| end |
| addr_hit[9]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_0_busy; |
| end |
| addr_hit[10]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_1_busy; |
| end |
| addr_hit[11]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_2_busy; |
| end |
| addr_hit[12]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_3_busy; |
| end |
| addr_hit[13]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_4_busy; |
| end |
| addr_hit[14]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_5_busy; |
| end |
| addr_hit[15]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_6_busy; |
| end |
| addr_hit[16]: begin |
| reg_busy_sel = adc_chn0_filter_ctl_7_busy; |
| end |
| addr_hit[17]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_0_busy; |
| end |
| addr_hit[18]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_1_busy; |
| end |
| addr_hit[19]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_2_busy; |
| end |
| addr_hit[20]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_3_busy; |
| end |
| addr_hit[21]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_4_busy; |
| end |
| addr_hit[22]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_5_busy; |
| end |
| addr_hit[23]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_6_busy; |
| end |
| addr_hit[24]: begin |
| reg_busy_sel = adc_chn1_filter_ctl_7_busy; |
| end |
| addr_hit[25]: begin |
| reg_busy_sel = adc_chn_val_0_busy; |
| end |
| addr_hit[26]: begin |
| reg_busy_sel = adc_chn_val_1_busy; |
| end |
| addr_hit[27]: begin |
| reg_busy_sel = adc_wakeup_ctl_busy; |
| end |
| addr_hit[28]: begin |
| reg_busy_sel = filter_status_busy; |
| end |
| default: begin |
| reg_busy_sel = '0; |
| end |
| endcase |
| end |
| |
| |
| // Unused signal tieoff |
| |
| // wdata / byte enable are not always fully used |
| // add a blanket unused statement to handle lint waivers |
| logic unused_wdata; |
| logic unused_be; |
| assign unused_wdata = ^reg_wdata; |
| assign unused_be = ^reg_be; |
| |
| // Assertions for Register Interface |
| `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) |
| `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) |
| |
| `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) |
| |
| `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) |
| |
| // this is formulated as an assumption such that the FPV testbenches do disprove this |
| // property by mistake |
| //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) |
| |
| endmodule |
