tree 8fe54c946fbccde295d8a3145b7362d913017f53
parent 054c40581027530bcdb7ace0c83f516ff130b204
author Silvestrs Timofejevs <silvestrst@lowrisc.org> 1591606455 +0100
committer Sam Elliott <sam@lenary.co.uk> 1591632074 +0100

[sw, dif_plic] Fulfil S1 Checklist DIF_TEST_SANITY requirement

DIF_TEST_SANITY (requirement):
Sanity tests exist for the DIF in sw/device/tests/dif named dif_<ip>_sanitytest.c.

This should perform a basic test of the main datapath of the hardware
module by the embedded core, via the DIF, and should be able to be run
on all OpenTitan platforms (including FPGA, simulation, and DV). This
test will be shared with DV.

Sanity tests are for diagnosing major issues in both software and
hardware, and with this in mind, they should execute
quickly. Initially we expect this kind of test to be written by
hardware designers for debugging issues during module
development. This happens long before a DIF is implemented, so there
are no requirements on how these should work, though we suggest they
are placed in sw/device/tests/<ip>/<ip>.c as this has been the
convention until now. Later, when a DIF is written, the DIF author is
responsible for updating this test to use the DIF, and for moving this
test into the aforementioned location.

CHANGE:
This change renames consecutive_irqs_test to dif_plic_sanitytest, and
places the source from sw/device/tests/ to sw/device/tests/dif/.

Signed-off-by: Silvestrs Timofejevs <silvestrst@lowrisc.org>