diff --git a/hw/ip/lc_ctrl/data/lc_ctrl.prj.hjson b/hw/ip/lc_ctrl/data/lc_ctrl.prj.hjson
index f482c00..8bad6a4 100644
--- a/hw/ip/lc_ctrl/data/lc_ctrl.prj.hjson
+++ b/hw/ip/lc_ctrl/data/lc_ctrl.prj.hjson
@@ -5,11 +5,11 @@
 {
     name:               "lc_ctrl",
     design_spec:        "hw/ip/lc_ctrl/doc",
-    dv_doc:            "",
-    hw_checklist:       "",
+    dv_doc:             "hw/ip/lc_ctrl/doc/dv",
+    hw_checklist:       "hw/ip/lc_ctrl/doc/checklist",
     version:            "0.1",
     life_stage:         "L1",
     design_stage:       "D1",
-    verification_stage: "V0",
+    verification_stage: "V1",
     notes:              "",
 }
diff --git a/hw/ip/lc_ctrl/doc/checklist.md b/hw/ip/lc_ctrl/doc/checklist.md
index 0d70d2d..759f357 100644
--- a/hw/ip/lc_ctrl/doc/checklist.md
+++ b/hw/ip/lc_ctrl/doc/checklist.md
@@ -115,28 +115,28 @@
 
  Type         | Item                                  | Resolution  | Note/Collaterals
 --------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][]            | Not Started | [LC_CTRL DV document]({{<relref "hw/ip/lc_ctrl/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][]                 | Not Started | [LC_CTRL DV plan]({{<relref "hw/ip/lc_ctrl/doc/dv/index.md#dv_plan" >}})
-Testbench     | [TB_TOP_CREATED][]                    | Not Started |
-Testbench     | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
-Testbench     | [SIM_TB_ENV_CREATED][]                | Not Started |
-Testbench     | [SIM_RAL_MODEL_GEN_AUTOMATED][]       | Not Started |
-Testbench     | [CSR_CHECK_GEN_AUTOMATED][]           | Not Started |
-Testbench     | [TB_GEN_AUTOMATED][]                  | Not Started |
-Tests         | [SIM_SMOKE_TEST_PASSING][]            | Not Started |
-Tests         | [SIM_CSR_MEM_TEST_SUITE_PASSING][]    | Not Started |
-Tests         | [FPV_MAIN_ASSERTIONS_PROVEN][]        | Not Started |
-Tool Setup    | [SIM_ALT_TOOL_SETUP][]                | Not Started |
-Regression    | [SIM_SMOKE_REGRESSION_SETUP][]        | Not Started |
-Regression    | [SIM_NIGHTLY_REGRESSION_SETUP][]      | Not Started |
-Regression    | [FPV_REGRESSION_SETUP][]              | Not Started |
-Coverage      | [SIM_COVERAGE_MODEL_ADDED][]          | Not Started |
-Code Quality  | [TB_LINT_SETUP][]                     | Not Started |
-Integration   | [PRE_VERIFIED_SUB_MODULES_V1][]       | Not Started |
-Review        | [DESIGN_SPEC_REVIEWED][]              | Not Started |
-Review        | [DV_PLAN_REVIEWED][]                  | Not Started |
-Review        | [STD_TEST_CATEGORIES_PLANNED][]       | Not Started | Exception (?)
-Review        | [V2_CHECKLIST_SCOPED][]               | Not Started |
+Documentation | [DV_DOC_DRAFT_COMPLETED][]            | Done        | [LC_CTRL DV document]({{<relref "hw/ip/lc_ctrl/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][]                 | Done        | [LC_CTRL DV plan]({{<relref "hw/ip/lc_ctrl/doc/dv/index.md#dv_plan" >}})
+Testbench     | [TB_TOP_CREATED][]                    | Done        |
+Testbench     | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done        |
+Testbench     | [SIM_TB_ENV_CREATED][]                | Done        |
+Testbench     | [SIM_RAL_MODEL_GEN_AUTOMATED][]       | Done        |
+Testbench     | [CSR_CHECK_GEN_AUTOMATED][]           | Done        |
+Testbench     | [TB_GEN_AUTOMATED][]                  | Done        |
+Tests         | [SIM_SMOKE_TEST_PASSING][]            | Done        |
+Tests         | [SIM_CSR_MEM_TEST_SUITE_PASSING][]    | Done        |
+Tests         | [FPV_MAIN_ASSERTIONS_PROVEN][]        | N/A         |
+Tool Setup    | [SIM_ALT_TOOL_SETUP][]                | Done        |
+Regression    | [SIM_SMOKE_REGRESSION_SETUP][]        | Done        |
+Regression    | [SIM_NIGHTLY_REGRESSION_SETUP][]      | Done        |
+Regression    | [FPV_REGRESSION_SETUP][]              | N/A         |
+Coverage      | [SIM_COVERAGE_MODEL_ADDED][]          | Done        |
+Code Quality  | [TB_LINT_SETUP][]                     | Done        |
+Integration   | [PRE_VERIFIED_SUB_MODULES_V1][]       | N/A         | Exception for IP modules
+Review        | [DESIGN_SPEC_REVIEWED][]              | Done        |
+Review        | [DV_PLAN_REVIEWED][]                  | Done        |
+Review        | [STD_TEST_CATEGORIES_PLANNED][]       | Done        | Exception (Security, Power)
+Review        | [V2_CHECKLIST_SCOPED][]               | Done        |
 
 [DV_DOC_DRAFT_COMPLETED]:             {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
 [DV_PLAN_COMPLETED]:                  {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
diff --git a/hw/ip/lc_ctrl/doc/dv/index.md b/hw/ip/lc_ctrl/doc/dv/index.md
index 412e540..9b5f727 100644
--- a/hw/ip/lc_ctrl/doc/dv/index.md
+++ b/hw/ip/lc_ctrl/doc/dv/index.md
@@ -114,5 +114,4 @@
 ```
 
 ## DV plan
-<!-- TODO: uncomment the line below after adding the DV plan -->
-{{</* testplan "hw/ip/lc_ctrl/data/lc_ctrl_testplan.hjson" */>}}
+{{< testplan "hw/ip/lc_ctrl/data/lc_ctrl_testplan.hjson" >}}
diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson
index 0dcb408..da40131 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson
@@ -5,7 +5,7 @@
 {
     name:               "otp_ctrl",
     design_spec:        "hw/ip/otp_ctrl/doc",
-    dv_doc:            "hw/ip/otp_ctrl/doc/dv",
+    dv_doc:             "hw/ip/otp_ctrl/doc/dv",
     hw_checklist:       "hw/ip/otp_ctrl/doc/checklist",
     sw_checklist:       "sw/device/lib/dif/dif_otp_ctrl",
     version:            "0.1",