hw/vendor/patches/pulp_riscv_dbg/0001-Fix-lint-errors.patch

From 62e0a09b7e90728c5c5380509c291cd0768f91e2 Mon Sep 17 00:00:00 2001
From: Michael Schaffner <msf@google.com>
Date: Tue, 25 Oct 2022 18:28:07 -0700
Subject: [PATCH 1/4] Fix lint errors

Signed-off-by: Michael Schaffner <msf@google.com>

diff --git a/src/dm_mem.sv b/src/dm_mem.sv
index 55ac8c6..09fc919 100755
--- a/src/dm_mem.sv
+++ b/src/dm_mem.sv
@@ -265,12 +265,13 @@ module dm_mem #(
           // core can write data registers
           [DataBaseAddr:DataEndAddr]: begin
             data_valid_o = 1'b1;
-            for (int dc = 0; dc < dm::DataCount; dc++) begin
+            for (int unsigned dc = 0; dc < dm::DataCount; dc++) begin
               if ((addr_i[DbgAddressBits-1:2] - DataBaseAddr[DbgAddressBits-1:2]) == dc) begin
-                for (int i = 0; i < $bits(be_i); i++) begin
+                for (int unsigned i = 0; i < $bits(be_i); i++) begin
                   if (be_i[i]) begin
                     if (i>3) begin // for upper 32bit data write (only used for BusWidth ==  64)
-                      if ((dc+1) < dm::DataCount) begin // ensure we write to an implemented data register
+                      // ensure we write to an implemented data register
+                      if (dc < (dm::DataCount - 1)) begin
                         data_bits[dc+1][(i-4)*8+:8] = wdata_i[i*8+:8];
                       end
                     end else begin // for lower 32bit data write
@@ -310,8 +311,11 @@ module dm_mem #(
 
           [DataBaseAddr:DataEndAddr]: begin
             rdata_d = {
-                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1) + 1'b1)],
-                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
+                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3]
+                                                      - DataBaseAddr[DbgAddressBits-1:3]) << 1)
+                                                    + 1'b1)],
+                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3]
+                                                      - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
                       };
           end
 
diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
index e897bf5..6be89a6 100644
--- a/src/dmi_jtag.sv
+++ b/src/dmi_jtag.sv
@@ -58,6 +58,7 @@ module dmi_jtag #(
   logic tdi;
 
   logic dtmcs_select;
+  dm::dtmcs_t dtmcs_d, dtmcs_q;
 
   assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset);
 
@@ -65,8 +66,6 @@ module dmi_jtag #(
   // Debug Module Control and Status
   // -------------------------------
 
-  dm::dtmcs_t dtmcs_d, dtmcs_q;
-
   always_comb begin
     dtmcs_d = dtmcs_q;
     if (capture) begin