| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module flash_ctrl_core_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input rst_shadowed_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| |
| // Output port for window |
| output tlul_pkg::tl_h2d_t tl_win_o [2], |
| input tlul_pkg::tl_d2h_t tl_win_i [2], |
| |
| // To HW |
| output flash_ctrl_reg_pkg::flash_ctrl_core_reg2hw_t reg2hw, // Write |
| input flash_ctrl_reg_pkg::flash_ctrl_core_hw2reg_t hw2reg, // Read |
| |
| output logic shadowed_storage_err_o, |
| output logic shadowed_update_err_o, |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import flash_ctrl_reg_pkg::* ; |
| |
| localparam int AW = 9; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [107:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(108) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(0) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| tlul_pkg::tl_h2d_t tl_socket_h2d [3]; |
| tlul_pkg::tl_d2h_t tl_socket_d2h [3]; |
| |
| logic [1:0] reg_steer; |
| |
| // socket_1n connection |
| assign tl_reg_h2d = tl_socket_h2d[2]; |
| assign tl_socket_d2h[2] = tl_reg_d2h; |
| |
| assign tl_win_o[0] = tl_socket_h2d[0]; |
| assign tl_socket_d2h[0] = tl_win_i[0]; |
| assign tl_win_o[1] = tl_socket_h2d[1]; |
| assign tl_socket_d2h[1] = tl_win_i[1]; |
| |
| // Create Socket_1n |
| tlul_socket_1n #( |
| .N (3), |
| .HReqPass (1'b1), |
| .HRspPass (1'b1), |
| .DReqPass ({3{1'b1}}), |
| .DRspPass ({3{1'b1}}), |
| .HReqDepth (4'h0), |
| .HRspDepth (4'h0), |
| .DReqDepth ({3{4'h0}}), |
| .DRspDepth ({3{4'h0}}), |
| .ExplicitErrs (1'b0) |
| ) u_socket ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| .tl_h_i (tl_i), |
| .tl_h_o (tl_o_pre), |
| .tl_d_o (tl_socket_h2d), |
| .tl_d_i (tl_socket_d2h), |
| .dev_select_i (reg_steer) |
| ); |
| |
| // Create steering logic |
| always_comb begin |
| reg_steer = |
| tl_i.a_address[AW-1:0] inside {[432:435]} ? 2'd0 : |
| tl_i.a_address[AW-1:0] inside {[436:439]} ? 2'd1 : |
| // Default set to register |
| 2'd2; |
| |
| // Override this in case of an integrity error |
| if (intg_err) begin |
| reg_steer = 2'd2; |
| end |
| end |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(1) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic intr_state_we; |
| logic intr_state_prog_empty_qs; |
| logic intr_state_prog_empty_wd; |
| logic intr_state_prog_lvl_qs; |
| logic intr_state_prog_lvl_wd; |
| logic intr_state_rd_full_qs; |
| logic intr_state_rd_full_wd; |
| logic intr_state_rd_lvl_qs; |
| logic intr_state_rd_lvl_wd; |
| logic intr_state_op_done_qs; |
| logic intr_state_op_done_wd; |
| logic intr_state_corr_err_qs; |
| logic intr_state_corr_err_wd; |
| logic intr_enable_we; |
| logic intr_enable_prog_empty_qs; |
| logic intr_enable_prog_empty_wd; |
| logic intr_enable_prog_lvl_qs; |
| logic intr_enable_prog_lvl_wd; |
| logic intr_enable_rd_full_qs; |
| logic intr_enable_rd_full_wd; |
| logic intr_enable_rd_lvl_qs; |
| logic intr_enable_rd_lvl_wd; |
| logic intr_enable_op_done_qs; |
| logic intr_enable_op_done_wd; |
| logic intr_enable_corr_err_qs; |
| logic intr_enable_corr_err_wd; |
| logic intr_test_we; |
| logic intr_test_prog_empty_wd; |
| logic intr_test_prog_lvl_wd; |
| logic intr_test_rd_full_wd; |
| logic intr_test_rd_lvl_wd; |
| logic intr_test_op_done_wd; |
| logic intr_test_corr_err_wd; |
| logic alert_test_we; |
| logic alert_test_recov_err_wd; |
| logic alert_test_fatal_std_err_wd; |
| logic alert_test_fatal_err_wd; |
| logic alert_test_fatal_prim_flash_alert_wd; |
| logic alert_test_recov_prim_flash_alert_wd; |
| logic dis_we; |
| logic [3:0] dis_qs; |
| logic [3:0] dis_wd; |
| logic exec_we; |
| logic [31:0] exec_qs; |
| logic [31:0] exec_wd; |
| logic init_we; |
| logic init_qs; |
| logic init_wd; |
| logic ctrl_regwen_re; |
| logic ctrl_regwen_qs; |
| logic control_we; |
| logic control_start_qs; |
| logic control_start_wd; |
| logic [1:0] control_op_qs; |
| logic [1:0] control_op_wd; |
| logic control_prog_sel_qs; |
| logic control_prog_sel_wd; |
| logic control_erase_sel_qs; |
| logic control_erase_sel_wd; |
| logic control_partition_sel_qs; |
| logic control_partition_sel_wd; |
| logic [1:0] control_info_sel_qs; |
| logic [1:0] control_info_sel_wd; |
| logic [11:0] control_num_qs; |
| logic [11:0] control_num_wd; |
| logic addr_we; |
| logic [19:0] addr_qs; |
| logic [19:0] addr_wd; |
| logic prog_type_en_we; |
| logic prog_type_en_normal_qs; |
| logic prog_type_en_normal_wd; |
| logic prog_type_en_repair_qs; |
| logic prog_type_en_repair_wd; |
| logic erase_suspend_we; |
| logic erase_suspend_qs; |
| logic erase_suspend_wd; |
| logic region_cfg_regwen_0_we; |
| logic region_cfg_regwen_0_qs; |
| logic region_cfg_regwen_0_wd; |
| logic region_cfg_regwen_1_we; |
| logic region_cfg_regwen_1_qs; |
| logic region_cfg_regwen_1_wd; |
| logic region_cfg_regwen_2_we; |
| logic region_cfg_regwen_2_qs; |
| logic region_cfg_regwen_2_wd; |
| logic region_cfg_regwen_3_we; |
| logic region_cfg_regwen_3_qs; |
| logic region_cfg_regwen_3_wd; |
| logic region_cfg_regwen_4_we; |
| logic region_cfg_regwen_4_qs; |
| logic region_cfg_regwen_4_wd; |
| logic region_cfg_regwen_5_we; |
| logic region_cfg_regwen_5_qs; |
| logic region_cfg_regwen_5_wd; |
| logic region_cfg_regwen_6_we; |
| logic region_cfg_regwen_6_qs; |
| logic region_cfg_regwen_6_wd; |
| logic region_cfg_regwen_7_we; |
| logic region_cfg_regwen_7_qs; |
| logic region_cfg_regwen_7_wd; |
| logic mp_region_cfg_0_we; |
| logic [3:0] mp_region_cfg_0_en_0_qs; |
| logic [3:0] mp_region_cfg_0_en_0_wd; |
| logic [3:0] mp_region_cfg_0_rd_en_0_qs; |
| logic [3:0] mp_region_cfg_0_rd_en_0_wd; |
| logic [3:0] mp_region_cfg_0_prog_en_0_qs; |
| logic [3:0] mp_region_cfg_0_prog_en_0_wd; |
| logic [3:0] mp_region_cfg_0_erase_en_0_qs; |
| logic [3:0] mp_region_cfg_0_erase_en_0_wd; |
| logic [3:0] mp_region_cfg_0_scramble_en_0_qs; |
| logic [3:0] mp_region_cfg_0_scramble_en_0_wd; |
| logic [3:0] mp_region_cfg_0_ecc_en_0_qs; |
| logic [3:0] mp_region_cfg_0_ecc_en_0_wd; |
| logic [3:0] mp_region_cfg_0_he_en_0_qs; |
| logic [3:0] mp_region_cfg_0_he_en_0_wd; |
| logic mp_region_cfg_1_we; |
| logic [3:0] mp_region_cfg_1_en_1_qs; |
| logic [3:0] mp_region_cfg_1_en_1_wd; |
| logic [3:0] mp_region_cfg_1_rd_en_1_qs; |
| logic [3:0] mp_region_cfg_1_rd_en_1_wd; |
| logic [3:0] mp_region_cfg_1_prog_en_1_qs; |
| logic [3:0] mp_region_cfg_1_prog_en_1_wd; |
| logic [3:0] mp_region_cfg_1_erase_en_1_qs; |
| logic [3:0] mp_region_cfg_1_erase_en_1_wd; |
| logic [3:0] mp_region_cfg_1_scramble_en_1_qs; |
| logic [3:0] mp_region_cfg_1_scramble_en_1_wd; |
| logic [3:0] mp_region_cfg_1_ecc_en_1_qs; |
| logic [3:0] mp_region_cfg_1_ecc_en_1_wd; |
| logic [3:0] mp_region_cfg_1_he_en_1_qs; |
| logic [3:0] mp_region_cfg_1_he_en_1_wd; |
| logic mp_region_cfg_2_we; |
| logic [3:0] mp_region_cfg_2_en_2_qs; |
| logic [3:0] mp_region_cfg_2_en_2_wd; |
| logic [3:0] mp_region_cfg_2_rd_en_2_qs; |
| logic [3:0] mp_region_cfg_2_rd_en_2_wd; |
| logic [3:0] mp_region_cfg_2_prog_en_2_qs; |
| logic [3:0] mp_region_cfg_2_prog_en_2_wd; |
| logic [3:0] mp_region_cfg_2_erase_en_2_qs; |
| logic [3:0] mp_region_cfg_2_erase_en_2_wd; |
| logic [3:0] mp_region_cfg_2_scramble_en_2_qs; |
| logic [3:0] mp_region_cfg_2_scramble_en_2_wd; |
| logic [3:0] mp_region_cfg_2_ecc_en_2_qs; |
| logic [3:0] mp_region_cfg_2_ecc_en_2_wd; |
| logic [3:0] mp_region_cfg_2_he_en_2_qs; |
| logic [3:0] mp_region_cfg_2_he_en_2_wd; |
| logic mp_region_cfg_3_we; |
| logic [3:0] mp_region_cfg_3_en_3_qs; |
| logic [3:0] mp_region_cfg_3_en_3_wd; |
| logic [3:0] mp_region_cfg_3_rd_en_3_qs; |
| logic [3:0] mp_region_cfg_3_rd_en_3_wd; |
| logic [3:0] mp_region_cfg_3_prog_en_3_qs; |
| logic [3:0] mp_region_cfg_3_prog_en_3_wd; |
| logic [3:0] mp_region_cfg_3_erase_en_3_qs; |
| logic [3:0] mp_region_cfg_3_erase_en_3_wd; |
| logic [3:0] mp_region_cfg_3_scramble_en_3_qs; |
| logic [3:0] mp_region_cfg_3_scramble_en_3_wd; |
| logic [3:0] mp_region_cfg_3_ecc_en_3_qs; |
| logic [3:0] mp_region_cfg_3_ecc_en_3_wd; |
| logic [3:0] mp_region_cfg_3_he_en_3_qs; |
| logic [3:0] mp_region_cfg_3_he_en_3_wd; |
| logic mp_region_cfg_4_we; |
| logic [3:0] mp_region_cfg_4_en_4_qs; |
| logic [3:0] mp_region_cfg_4_en_4_wd; |
| logic [3:0] mp_region_cfg_4_rd_en_4_qs; |
| logic [3:0] mp_region_cfg_4_rd_en_4_wd; |
| logic [3:0] mp_region_cfg_4_prog_en_4_qs; |
| logic [3:0] mp_region_cfg_4_prog_en_4_wd; |
| logic [3:0] mp_region_cfg_4_erase_en_4_qs; |
| logic [3:0] mp_region_cfg_4_erase_en_4_wd; |
| logic [3:0] mp_region_cfg_4_scramble_en_4_qs; |
| logic [3:0] mp_region_cfg_4_scramble_en_4_wd; |
| logic [3:0] mp_region_cfg_4_ecc_en_4_qs; |
| logic [3:0] mp_region_cfg_4_ecc_en_4_wd; |
| logic [3:0] mp_region_cfg_4_he_en_4_qs; |
| logic [3:0] mp_region_cfg_4_he_en_4_wd; |
| logic mp_region_cfg_5_we; |
| logic [3:0] mp_region_cfg_5_en_5_qs; |
| logic [3:0] mp_region_cfg_5_en_5_wd; |
| logic [3:0] mp_region_cfg_5_rd_en_5_qs; |
| logic [3:0] mp_region_cfg_5_rd_en_5_wd; |
| logic [3:0] mp_region_cfg_5_prog_en_5_qs; |
| logic [3:0] mp_region_cfg_5_prog_en_5_wd; |
| logic [3:0] mp_region_cfg_5_erase_en_5_qs; |
| logic [3:0] mp_region_cfg_5_erase_en_5_wd; |
| logic [3:0] mp_region_cfg_5_scramble_en_5_qs; |
| logic [3:0] mp_region_cfg_5_scramble_en_5_wd; |
| logic [3:0] mp_region_cfg_5_ecc_en_5_qs; |
| logic [3:0] mp_region_cfg_5_ecc_en_5_wd; |
| logic [3:0] mp_region_cfg_5_he_en_5_qs; |
| logic [3:0] mp_region_cfg_5_he_en_5_wd; |
| logic mp_region_cfg_6_we; |
| logic [3:0] mp_region_cfg_6_en_6_qs; |
| logic [3:0] mp_region_cfg_6_en_6_wd; |
| logic [3:0] mp_region_cfg_6_rd_en_6_qs; |
| logic [3:0] mp_region_cfg_6_rd_en_6_wd; |
| logic [3:0] mp_region_cfg_6_prog_en_6_qs; |
| logic [3:0] mp_region_cfg_6_prog_en_6_wd; |
| logic [3:0] mp_region_cfg_6_erase_en_6_qs; |
| logic [3:0] mp_region_cfg_6_erase_en_6_wd; |
| logic [3:0] mp_region_cfg_6_scramble_en_6_qs; |
| logic [3:0] mp_region_cfg_6_scramble_en_6_wd; |
| logic [3:0] mp_region_cfg_6_ecc_en_6_qs; |
| logic [3:0] mp_region_cfg_6_ecc_en_6_wd; |
| logic [3:0] mp_region_cfg_6_he_en_6_qs; |
| logic [3:0] mp_region_cfg_6_he_en_6_wd; |
| logic mp_region_cfg_7_we; |
| logic [3:0] mp_region_cfg_7_en_7_qs; |
| logic [3:0] mp_region_cfg_7_en_7_wd; |
| logic [3:0] mp_region_cfg_7_rd_en_7_qs; |
| logic [3:0] mp_region_cfg_7_rd_en_7_wd; |
| logic [3:0] mp_region_cfg_7_prog_en_7_qs; |
| logic [3:0] mp_region_cfg_7_prog_en_7_wd; |
| logic [3:0] mp_region_cfg_7_erase_en_7_qs; |
| logic [3:0] mp_region_cfg_7_erase_en_7_wd; |
| logic [3:0] mp_region_cfg_7_scramble_en_7_qs; |
| logic [3:0] mp_region_cfg_7_scramble_en_7_wd; |
| logic [3:0] mp_region_cfg_7_ecc_en_7_qs; |
| logic [3:0] mp_region_cfg_7_ecc_en_7_wd; |
| logic [3:0] mp_region_cfg_7_he_en_7_qs; |
| logic [3:0] mp_region_cfg_7_he_en_7_wd; |
| logic mp_region_0_we; |
| logic [8:0] mp_region_0_base_0_qs; |
| logic [8:0] mp_region_0_base_0_wd; |
| logic [9:0] mp_region_0_size_0_qs; |
| logic [9:0] mp_region_0_size_0_wd; |
| logic mp_region_1_we; |
| logic [8:0] mp_region_1_base_1_qs; |
| logic [8:0] mp_region_1_base_1_wd; |
| logic [9:0] mp_region_1_size_1_qs; |
| logic [9:0] mp_region_1_size_1_wd; |
| logic mp_region_2_we; |
| logic [8:0] mp_region_2_base_2_qs; |
| logic [8:0] mp_region_2_base_2_wd; |
| logic [9:0] mp_region_2_size_2_qs; |
| logic [9:0] mp_region_2_size_2_wd; |
| logic mp_region_3_we; |
| logic [8:0] mp_region_3_base_3_qs; |
| logic [8:0] mp_region_3_base_3_wd; |
| logic [9:0] mp_region_3_size_3_qs; |
| logic [9:0] mp_region_3_size_3_wd; |
| logic mp_region_4_we; |
| logic [8:0] mp_region_4_base_4_qs; |
| logic [8:0] mp_region_4_base_4_wd; |
| logic [9:0] mp_region_4_size_4_qs; |
| logic [9:0] mp_region_4_size_4_wd; |
| logic mp_region_5_we; |
| logic [8:0] mp_region_5_base_5_qs; |
| logic [8:0] mp_region_5_base_5_wd; |
| logic [9:0] mp_region_5_size_5_qs; |
| logic [9:0] mp_region_5_size_5_wd; |
| logic mp_region_6_we; |
| logic [8:0] mp_region_6_base_6_qs; |
| logic [8:0] mp_region_6_base_6_wd; |
| logic [9:0] mp_region_6_size_6_qs; |
| logic [9:0] mp_region_6_size_6_wd; |
| logic mp_region_7_we; |
| logic [8:0] mp_region_7_base_7_qs; |
| logic [8:0] mp_region_7_base_7_wd; |
| logic [9:0] mp_region_7_size_7_qs; |
| logic [9:0] mp_region_7_size_7_wd; |
| logic default_region_we; |
| logic [3:0] default_region_rd_en_qs; |
| logic [3:0] default_region_rd_en_wd; |
| logic [3:0] default_region_prog_en_qs; |
| logic [3:0] default_region_prog_en_wd; |
| logic [3:0] default_region_erase_en_qs; |
| logic [3:0] default_region_erase_en_wd; |
| logic [3:0] default_region_scramble_en_qs; |
| logic [3:0] default_region_scramble_en_wd; |
| logic [3:0] default_region_ecc_en_qs; |
| logic [3:0] default_region_ecc_en_wd; |
| logic [3:0] default_region_he_en_qs; |
| logic [3:0] default_region_he_en_wd; |
| logic bank0_info0_regwen_0_we; |
| logic bank0_info0_regwen_0_qs; |
| logic bank0_info0_regwen_0_wd; |
| logic bank0_info0_regwen_1_we; |
| logic bank0_info0_regwen_1_qs; |
| logic bank0_info0_regwen_1_wd; |
| logic bank0_info0_regwen_2_we; |
| logic bank0_info0_regwen_2_qs; |
| logic bank0_info0_regwen_2_wd; |
| logic bank0_info0_regwen_3_we; |
| logic bank0_info0_regwen_3_qs; |
| logic bank0_info0_regwen_3_wd; |
| logic bank0_info0_regwen_4_we; |
| logic bank0_info0_regwen_4_qs; |
| logic bank0_info0_regwen_4_wd; |
| logic bank0_info0_regwen_5_we; |
| logic bank0_info0_regwen_5_qs; |
| logic bank0_info0_regwen_5_wd; |
| logic bank0_info0_regwen_6_we; |
| logic bank0_info0_regwen_6_qs; |
| logic bank0_info0_regwen_6_wd; |
| logic bank0_info0_regwen_7_we; |
| logic bank0_info0_regwen_7_qs; |
| logic bank0_info0_regwen_7_wd; |
| logic bank0_info0_regwen_8_we; |
| logic bank0_info0_regwen_8_qs; |
| logic bank0_info0_regwen_8_wd; |
| logic bank0_info0_regwen_9_we; |
| logic bank0_info0_regwen_9_qs; |
| logic bank0_info0_regwen_9_wd; |
| logic bank0_info0_page_cfg_0_we; |
| logic [3:0] bank0_info0_page_cfg_0_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_en_0_wd; |
| logic [3:0] bank0_info0_page_cfg_0_rd_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_rd_en_0_wd; |
| logic [3:0] bank0_info0_page_cfg_0_prog_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_prog_en_0_wd; |
| logic [3:0] bank0_info0_page_cfg_0_erase_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_erase_en_0_wd; |
| logic [3:0] bank0_info0_page_cfg_0_scramble_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_scramble_en_0_wd; |
| logic [3:0] bank0_info0_page_cfg_0_ecc_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_ecc_en_0_wd; |
| logic [3:0] bank0_info0_page_cfg_0_he_en_0_qs; |
| logic [3:0] bank0_info0_page_cfg_0_he_en_0_wd; |
| logic bank0_info0_page_cfg_1_we; |
| logic [3:0] bank0_info0_page_cfg_1_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_en_1_wd; |
| logic [3:0] bank0_info0_page_cfg_1_rd_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_rd_en_1_wd; |
| logic [3:0] bank0_info0_page_cfg_1_prog_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_prog_en_1_wd; |
| logic [3:0] bank0_info0_page_cfg_1_erase_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_erase_en_1_wd; |
| logic [3:0] bank0_info0_page_cfg_1_scramble_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_scramble_en_1_wd; |
| logic [3:0] bank0_info0_page_cfg_1_ecc_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_ecc_en_1_wd; |
| logic [3:0] bank0_info0_page_cfg_1_he_en_1_qs; |
| logic [3:0] bank0_info0_page_cfg_1_he_en_1_wd; |
| logic bank0_info0_page_cfg_2_we; |
| logic [3:0] bank0_info0_page_cfg_2_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_en_2_wd; |
| logic [3:0] bank0_info0_page_cfg_2_rd_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_rd_en_2_wd; |
| logic [3:0] bank0_info0_page_cfg_2_prog_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_prog_en_2_wd; |
| logic [3:0] bank0_info0_page_cfg_2_erase_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_erase_en_2_wd; |
| logic [3:0] bank0_info0_page_cfg_2_scramble_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_scramble_en_2_wd; |
| logic [3:0] bank0_info0_page_cfg_2_ecc_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_ecc_en_2_wd; |
| logic [3:0] bank0_info0_page_cfg_2_he_en_2_qs; |
| logic [3:0] bank0_info0_page_cfg_2_he_en_2_wd; |
| logic bank0_info0_page_cfg_3_we; |
| logic [3:0] bank0_info0_page_cfg_3_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_en_3_wd; |
| logic [3:0] bank0_info0_page_cfg_3_rd_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_rd_en_3_wd; |
| logic [3:0] bank0_info0_page_cfg_3_prog_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_prog_en_3_wd; |
| logic [3:0] bank0_info0_page_cfg_3_erase_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_erase_en_3_wd; |
| logic [3:0] bank0_info0_page_cfg_3_scramble_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_scramble_en_3_wd; |
| logic [3:0] bank0_info0_page_cfg_3_ecc_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_ecc_en_3_wd; |
| logic [3:0] bank0_info0_page_cfg_3_he_en_3_qs; |
| logic [3:0] bank0_info0_page_cfg_3_he_en_3_wd; |
| logic bank0_info0_page_cfg_4_we; |
| logic [3:0] bank0_info0_page_cfg_4_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_en_4_wd; |
| logic [3:0] bank0_info0_page_cfg_4_rd_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_rd_en_4_wd; |
| logic [3:0] bank0_info0_page_cfg_4_prog_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_prog_en_4_wd; |
| logic [3:0] bank0_info0_page_cfg_4_erase_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_erase_en_4_wd; |
| logic [3:0] bank0_info0_page_cfg_4_scramble_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_scramble_en_4_wd; |
| logic [3:0] bank0_info0_page_cfg_4_ecc_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_ecc_en_4_wd; |
| logic [3:0] bank0_info0_page_cfg_4_he_en_4_qs; |
| logic [3:0] bank0_info0_page_cfg_4_he_en_4_wd; |
| logic bank0_info0_page_cfg_5_we; |
| logic [3:0] bank0_info0_page_cfg_5_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_en_5_wd; |
| logic [3:0] bank0_info0_page_cfg_5_rd_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_rd_en_5_wd; |
| logic [3:0] bank0_info0_page_cfg_5_prog_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_prog_en_5_wd; |
| logic [3:0] bank0_info0_page_cfg_5_erase_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_erase_en_5_wd; |
| logic [3:0] bank0_info0_page_cfg_5_scramble_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_scramble_en_5_wd; |
| logic [3:0] bank0_info0_page_cfg_5_ecc_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_ecc_en_5_wd; |
| logic [3:0] bank0_info0_page_cfg_5_he_en_5_qs; |
| logic [3:0] bank0_info0_page_cfg_5_he_en_5_wd; |
| logic bank0_info0_page_cfg_6_we; |
| logic [3:0] bank0_info0_page_cfg_6_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_en_6_wd; |
| logic [3:0] bank0_info0_page_cfg_6_rd_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_rd_en_6_wd; |
| logic [3:0] bank0_info0_page_cfg_6_prog_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_prog_en_6_wd; |
| logic [3:0] bank0_info0_page_cfg_6_erase_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_erase_en_6_wd; |
| logic [3:0] bank0_info0_page_cfg_6_scramble_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_scramble_en_6_wd; |
| logic [3:0] bank0_info0_page_cfg_6_ecc_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_ecc_en_6_wd; |
| logic [3:0] bank0_info0_page_cfg_6_he_en_6_qs; |
| logic [3:0] bank0_info0_page_cfg_6_he_en_6_wd; |
| logic bank0_info0_page_cfg_7_we; |
| logic [3:0] bank0_info0_page_cfg_7_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_en_7_wd; |
| logic [3:0] bank0_info0_page_cfg_7_rd_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_rd_en_7_wd; |
| logic [3:0] bank0_info0_page_cfg_7_prog_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_prog_en_7_wd; |
| logic [3:0] bank0_info0_page_cfg_7_erase_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_erase_en_7_wd; |
| logic [3:0] bank0_info0_page_cfg_7_scramble_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_scramble_en_7_wd; |
| logic [3:0] bank0_info0_page_cfg_7_ecc_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_ecc_en_7_wd; |
| logic [3:0] bank0_info0_page_cfg_7_he_en_7_qs; |
| logic [3:0] bank0_info0_page_cfg_7_he_en_7_wd; |
| logic bank0_info0_page_cfg_8_we; |
| logic [3:0] bank0_info0_page_cfg_8_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_en_8_wd; |
| logic [3:0] bank0_info0_page_cfg_8_rd_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_rd_en_8_wd; |
| logic [3:0] bank0_info0_page_cfg_8_prog_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_prog_en_8_wd; |
| logic [3:0] bank0_info0_page_cfg_8_erase_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_erase_en_8_wd; |
| logic [3:0] bank0_info0_page_cfg_8_scramble_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_scramble_en_8_wd; |
| logic [3:0] bank0_info0_page_cfg_8_ecc_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_ecc_en_8_wd; |
| logic [3:0] bank0_info0_page_cfg_8_he_en_8_qs; |
| logic [3:0] bank0_info0_page_cfg_8_he_en_8_wd; |
| logic bank0_info0_page_cfg_9_we; |
| logic [3:0] bank0_info0_page_cfg_9_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_en_9_wd; |
| logic [3:0] bank0_info0_page_cfg_9_rd_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_rd_en_9_wd; |
| logic [3:0] bank0_info0_page_cfg_9_prog_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_prog_en_9_wd; |
| logic [3:0] bank0_info0_page_cfg_9_erase_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_erase_en_9_wd; |
| logic [3:0] bank0_info0_page_cfg_9_scramble_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_scramble_en_9_wd; |
| logic [3:0] bank0_info0_page_cfg_9_ecc_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_ecc_en_9_wd; |
| logic [3:0] bank0_info0_page_cfg_9_he_en_9_qs; |
| logic [3:0] bank0_info0_page_cfg_9_he_en_9_wd; |
| logic bank0_info1_regwen_we; |
| logic bank0_info1_regwen_qs; |
| logic bank0_info1_regwen_wd; |
| logic bank0_info1_page_cfg_we; |
| logic [3:0] bank0_info1_page_cfg_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_en_0_wd; |
| logic [3:0] bank0_info1_page_cfg_rd_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_rd_en_0_wd; |
| logic [3:0] bank0_info1_page_cfg_prog_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_prog_en_0_wd; |
| logic [3:0] bank0_info1_page_cfg_erase_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_erase_en_0_wd; |
| logic [3:0] bank0_info1_page_cfg_scramble_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_scramble_en_0_wd; |
| logic [3:0] bank0_info1_page_cfg_ecc_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_ecc_en_0_wd; |
| logic [3:0] bank0_info1_page_cfg_he_en_0_qs; |
| logic [3:0] bank0_info1_page_cfg_he_en_0_wd; |
| logic bank0_info2_regwen_0_we; |
| logic bank0_info2_regwen_0_qs; |
| logic bank0_info2_regwen_0_wd; |
| logic bank0_info2_regwen_1_we; |
| logic bank0_info2_regwen_1_qs; |
| logic bank0_info2_regwen_1_wd; |
| logic bank0_info2_page_cfg_0_we; |
| logic [3:0] bank0_info2_page_cfg_0_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_en_0_wd; |
| logic [3:0] bank0_info2_page_cfg_0_rd_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_rd_en_0_wd; |
| logic [3:0] bank0_info2_page_cfg_0_prog_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_prog_en_0_wd; |
| logic [3:0] bank0_info2_page_cfg_0_erase_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_erase_en_0_wd; |
| logic [3:0] bank0_info2_page_cfg_0_scramble_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_scramble_en_0_wd; |
| logic [3:0] bank0_info2_page_cfg_0_ecc_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_ecc_en_0_wd; |
| logic [3:0] bank0_info2_page_cfg_0_he_en_0_qs; |
| logic [3:0] bank0_info2_page_cfg_0_he_en_0_wd; |
| logic bank0_info2_page_cfg_1_we; |
| logic [3:0] bank0_info2_page_cfg_1_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_en_1_wd; |
| logic [3:0] bank0_info2_page_cfg_1_rd_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_rd_en_1_wd; |
| logic [3:0] bank0_info2_page_cfg_1_prog_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_prog_en_1_wd; |
| logic [3:0] bank0_info2_page_cfg_1_erase_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_erase_en_1_wd; |
| logic [3:0] bank0_info2_page_cfg_1_scramble_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_scramble_en_1_wd; |
| logic [3:0] bank0_info2_page_cfg_1_ecc_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_ecc_en_1_wd; |
| logic [3:0] bank0_info2_page_cfg_1_he_en_1_qs; |
| logic [3:0] bank0_info2_page_cfg_1_he_en_1_wd; |
| logic bank1_info0_regwen_0_we; |
| logic bank1_info0_regwen_0_qs; |
| logic bank1_info0_regwen_0_wd; |
| logic bank1_info0_regwen_1_we; |
| logic bank1_info0_regwen_1_qs; |
| logic bank1_info0_regwen_1_wd; |
| logic bank1_info0_regwen_2_we; |
| logic bank1_info0_regwen_2_qs; |
| logic bank1_info0_regwen_2_wd; |
| logic bank1_info0_regwen_3_we; |
| logic bank1_info0_regwen_3_qs; |
| logic bank1_info0_regwen_3_wd; |
| logic bank1_info0_regwen_4_we; |
| logic bank1_info0_regwen_4_qs; |
| logic bank1_info0_regwen_4_wd; |
| logic bank1_info0_regwen_5_we; |
| logic bank1_info0_regwen_5_qs; |
| logic bank1_info0_regwen_5_wd; |
| logic bank1_info0_regwen_6_we; |
| logic bank1_info0_regwen_6_qs; |
| logic bank1_info0_regwen_6_wd; |
| logic bank1_info0_regwen_7_we; |
| logic bank1_info0_regwen_7_qs; |
| logic bank1_info0_regwen_7_wd; |
| logic bank1_info0_regwen_8_we; |
| logic bank1_info0_regwen_8_qs; |
| logic bank1_info0_regwen_8_wd; |
| logic bank1_info0_regwen_9_we; |
| logic bank1_info0_regwen_9_qs; |
| logic bank1_info0_regwen_9_wd; |
| logic bank1_info0_page_cfg_0_we; |
| logic [3:0] bank1_info0_page_cfg_0_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_en_0_wd; |
| logic [3:0] bank1_info0_page_cfg_0_rd_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_rd_en_0_wd; |
| logic [3:0] bank1_info0_page_cfg_0_prog_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_prog_en_0_wd; |
| logic [3:0] bank1_info0_page_cfg_0_erase_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_erase_en_0_wd; |
| logic [3:0] bank1_info0_page_cfg_0_scramble_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_scramble_en_0_wd; |
| logic [3:0] bank1_info0_page_cfg_0_ecc_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_ecc_en_0_wd; |
| logic [3:0] bank1_info0_page_cfg_0_he_en_0_qs; |
| logic [3:0] bank1_info0_page_cfg_0_he_en_0_wd; |
| logic bank1_info0_page_cfg_1_we; |
| logic [3:0] bank1_info0_page_cfg_1_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_en_1_wd; |
| logic [3:0] bank1_info0_page_cfg_1_rd_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_rd_en_1_wd; |
| logic [3:0] bank1_info0_page_cfg_1_prog_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_prog_en_1_wd; |
| logic [3:0] bank1_info0_page_cfg_1_erase_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_erase_en_1_wd; |
| logic [3:0] bank1_info0_page_cfg_1_scramble_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_scramble_en_1_wd; |
| logic [3:0] bank1_info0_page_cfg_1_ecc_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_ecc_en_1_wd; |
| logic [3:0] bank1_info0_page_cfg_1_he_en_1_qs; |
| logic [3:0] bank1_info0_page_cfg_1_he_en_1_wd; |
| logic bank1_info0_page_cfg_2_we; |
| logic [3:0] bank1_info0_page_cfg_2_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_en_2_wd; |
| logic [3:0] bank1_info0_page_cfg_2_rd_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_rd_en_2_wd; |
| logic [3:0] bank1_info0_page_cfg_2_prog_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_prog_en_2_wd; |
| logic [3:0] bank1_info0_page_cfg_2_erase_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_erase_en_2_wd; |
| logic [3:0] bank1_info0_page_cfg_2_scramble_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_scramble_en_2_wd; |
| logic [3:0] bank1_info0_page_cfg_2_ecc_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_ecc_en_2_wd; |
| logic [3:0] bank1_info0_page_cfg_2_he_en_2_qs; |
| logic [3:0] bank1_info0_page_cfg_2_he_en_2_wd; |
| logic bank1_info0_page_cfg_3_we; |
| logic [3:0] bank1_info0_page_cfg_3_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_en_3_wd; |
| logic [3:0] bank1_info0_page_cfg_3_rd_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_rd_en_3_wd; |
| logic [3:0] bank1_info0_page_cfg_3_prog_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_prog_en_3_wd; |
| logic [3:0] bank1_info0_page_cfg_3_erase_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_erase_en_3_wd; |
| logic [3:0] bank1_info0_page_cfg_3_scramble_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_scramble_en_3_wd; |
| logic [3:0] bank1_info0_page_cfg_3_ecc_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_ecc_en_3_wd; |
| logic [3:0] bank1_info0_page_cfg_3_he_en_3_qs; |
| logic [3:0] bank1_info0_page_cfg_3_he_en_3_wd; |
| logic bank1_info0_page_cfg_4_we; |
| logic [3:0] bank1_info0_page_cfg_4_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_en_4_wd; |
| logic [3:0] bank1_info0_page_cfg_4_rd_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_rd_en_4_wd; |
| logic [3:0] bank1_info0_page_cfg_4_prog_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_prog_en_4_wd; |
| logic [3:0] bank1_info0_page_cfg_4_erase_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_erase_en_4_wd; |
| logic [3:0] bank1_info0_page_cfg_4_scramble_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_scramble_en_4_wd; |
| logic [3:0] bank1_info0_page_cfg_4_ecc_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_ecc_en_4_wd; |
| logic [3:0] bank1_info0_page_cfg_4_he_en_4_qs; |
| logic [3:0] bank1_info0_page_cfg_4_he_en_4_wd; |
| logic bank1_info0_page_cfg_5_we; |
| logic [3:0] bank1_info0_page_cfg_5_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_en_5_wd; |
| logic [3:0] bank1_info0_page_cfg_5_rd_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_rd_en_5_wd; |
| logic [3:0] bank1_info0_page_cfg_5_prog_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_prog_en_5_wd; |
| logic [3:0] bank1_info0_page_cfg_5_erase_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_erase_en_5_wd; |
| logic [3:0] bank1_info0_page_cfg_5_scramble_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_scramble_en_5_wd; |
| logic [3:0] bank1_info0_page_cfg_5_ecc_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_ecc_en_5_wd; |
| logic [3:0] bank1_info0_page_cfg_5_he_en_5_qs; |
| logic [3:0] bank1_info0_page_cfg_5_he_en_5_wd; |
| logic bank1_info0_page_cfg_6_we; |
| logic [3:0] bank1_info0_page_cfg_6_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_en_6_wd; |
| logic [3:0] bank1_info0_page_cfg_6_rd_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_rd_en_6_wd; |
| logic [3:0] bank1_info0_page_cfg_6_prog_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_prog_en_6_wd; |
| logic [3:0] bank1_info0_page_cfg_6_erase_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_erase_en_6_wd; |
| logic [3:0] bank1_info0_page_cfg_6_scramble_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_scramble_en_6_wd; |
| logic [3:0] bank1_info0_page_cfg_6_ecc_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_ecc_en_6_wd; |
| logic [3:0] bank1_info0_page_cfg_6_he_en_6_qs; |
| logic [3:0] bank1_info0_page_cfg_6_he_en_6_wd; |
| logic bank1_info0_page_cfg_7_we; |
| logic [3:0] bank1_info0_page_cfg_7_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_en_7_wd; |
| logic [3:0] bank1_info0_page_cfg_7_rd_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_rd_en_7_wd; |
| logic [3:0] bank1_info0_page_cfg_7_prog_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_prog_en_7_wd; |
| logic [3:0] bank1_info0_page_cfg_7_erase_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_erase_en_7_wd; |
| logic [3:0] bank1_info0_page_cfg_7_scramble_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_scramble_en_7_wd; |
| logic [3:0] bank1_info0_page_cfg_7_ecc_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_ecc_en_7_wd; |
| logic [3:0] bank1_info0_page_cfg_7_he_en_7_qs; |
| logic [3:0] bank1_info0_page_cfg_7_he_en_7_wd; |
| logic bank1_info0_page_cfg_8_we; |
| logic [3:0] bank1_info0_page_cfg_8_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_en_8_wd; |
| logic [3:0] bank1_info0_page_cfg_8_rd_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_rd_en_8_wd; |
| logic [3:0] bank1_info0_page_cfg_8_prog_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_prog_en_8_wd; |
| logic [3:0] bank1_info0_page_cfg_8_erase_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_erase_en_8_wd; |
| logic [3:0] bank1_info0_page_cfg_8_scramble_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_scramble_en_8_wd; |
| logic [3:0] bank1_info0_page_cfg_8_ecc_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_ecc_en_8_wd; |
| logic [3:0] bank1_info0_page_cfg_8_he_en_8_qs; |
| logic [3:0] bank1_info0_page_cfg_8_he_en_8_wd; |
| logic bank1_info0_page_cfg_9_we; |
| logic [3:0] bank1_info0_page_cfg_9_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_en_9_wd; |
| logic [3:0] bank1_info0_page_cfg_9_rd_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_rd_en_9_wd; |
| logic [3:0] bank1_info0_page_cfg_9_prog_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_prog_en_9_wd; |
| logic [3:0] bank1_info0_page_cfg_9_erase_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_erase_en_9_wd; |
| logic [3:0] bank1_info0_page_cfg_9_scramble_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_scramble_en_9_wd; |
| logic [3:0] bank1_info0_page_cfg_9_ecc_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_ecc_en_9_wd; |
| logic [3:0] bank1_info0_page_cfg_9_he_en_9_qs; |
| logic [3:0] bank1_info0_page_cfg_9_he_en_9_wd; |
| logic bank1_info1_regwen_we; |
| logic bank1_info1_regwen_qs; |
| logic bank1_info1_regwen_wd; |
| logic bank1_info1_page_cfg_we; |
| logic [3:0] bank1_info1_page_cfg_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_en_0_wd; |
| logic [3:0] bank1_info1_page_cfg_rd_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_rd_en_0_wd; |
| logic [3:0] bank1_info1_page_cfg_prog_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_prog_en_0_wd; |
| logic [3:0] bank1_info1_page_cfg_erase_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_erase_en_0_wd; |
| logic [3:0] bank1_info1_page_cfg_scramble_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_scramble_en_0_wd; |
| logic [3:0] bank1_info1_page_cfg_ecc_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_ecc_en_0_wd; |
| logic [3:0] bank1_info1_page_cfg_he_en_0_qs; |
| logic [3:0] bank1_info1_page_cfg_he_en_0_wd; |
| logic bank1_info2_regwen_0_we; |
| logic bank1_info2_regwen_0_qs; |
| logic bank1_info2_regwen_0_wd; |
| logic bank1_info2_regwen_1_we; |
| logic bank1_info2_regwen_1_qs; |
| logic bank1_info2_regwen_1_wd; |
| logic bank1_info2_page_cfg_0_we; |
| logic [3:0] bank1_info2_page_cfg_0_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_en_0_wd; |
| logic [3:0] bank1_info2_page_cfg_0_rd_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_rd_en_0_wd; |
| logic [3:0] bank1_info2_page_cfg_0_prog_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_prog_en_0_wd; |
| logic [3:0] bank1_info2_page_cfg_0_erase_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_erase_en_0_wd; |
| logic [3:0] bank1_info2_page_cfg_0_scramble_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_scramble_en_0_wd; |
| logic [3:0] bank1_info2_page_cfg_0_ecc_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_ecc_en_0_wd; |
| logic [3:0] bank1_info2_page_cfg_0_he_en_0_qs; |
| logic [3:0] bank1_info2_page_cfg_0_he_en_0_wd; |
| logic bank1_info2_page_cfg_1_we; |
| logic [3:0] bank1_info2_page_cfg_1_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_en_1_wd; |
| logic [3:0] bank1_info2_page_cfg_1_rd_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_rd_en_1_wd; |
| logic [3:0] bank1_info2_page_cfg_1_prog_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_prog_en_1_wd; |
| logic [3:0] bank1_info2_page_cfg_1_erase_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_erase_en_1_wd; |
| logic [3:0] bank1_info2_page_cfg_1_scramble_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_scramble_en_1_wd; |
| logic [3:0] bank1_info2_page_cfg_1_ecc_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_ecc_en_1_wd; |
| logic [3:0] bank1_info2_page_cfg_1_he_en_1_qs; |
| logic [3:0] bank1_info2_page_cfg_1_he_en_1_wd; |
| logic hw_info_cfg_override_we; |
| logic [3:0] hw_info_cfg_override_scramble_dis_qs; |
| logic [3:0] hw_info_cfg_override_scramble_dis_wd; |
| logic [3:0] hw_info_cfg_override_ecc_dis_qs; |
| logic [3:0] hw_info_cfg_override_ecc_dis_wd; |
| logic bank_cfg_regwen_we; |
| logic bank_cfg_regwen_qs; |
| logic bank_cfg_regwen_wd; |
| logic mp_bank_cfg_shadowed_re; |
| logic mp_bank_cfg_shadowed_we; |
| logic mp_bank_cfg_shadowed_erase_en_0_qs; |
| logic mp_bank_cfg_shadowed_erase_en_0_wd; |
| logic mp_bank_cfg_shadowed_erase_en_0_storage_err; |
| logic mp_bank_cfg_shadowed_erase_en_0_update_err; |
| logic mp_bank_cfg_shadowed_erase_en_1_qs; |
| logic mp_bank_cfg_shadowed_erase_en_1_wd; |
| logic mp_bank_cfg_shadowed_erase_en_1_storage_err; |
| logic mp_bank_cfg_shadowed_erase_en_1_update_err; |
| logic op_status_we; |
| logic op_status_done_qs; |
| logic op_status_done_wd; |
| logic op_status_err_qs; |
| logic op_status_err_wd; |
| logic status_rd_full_qs; |
| logic status_rd_empty_qs; |
| logic status_prog_full_qs; |
| logic status_prog_empty_qs; |
| logic status_init_wip_qs; |
| logic status_initialized_qs; |
| logic debug_state_re; |
| logic [10:0] debug_state_qs; |
| logic err_code_we; |
| logic err_code_op_err_qs; |
| logic err_code_op_err_wd; |
| logic err_code_mp_err_qs; |
| logic err_code_mp_err_wd; |
| logic err_code_rd_err_qs; |
| logic err_code_rd_err_wd; |
| logic err_code_prog_err_qs; |
| logic err_code_prog_err_wd; |
| logic err_code_prog_win_err_qs; |
| logic err_code_prog_win_err_wd; |
| logic err_code_prog_type_err_qs; |
| logic err_code_prog_type_err_wd; |
| logic err_code_update_err_qs; |
| logic err_code_update_err_wd; |
| logic err_code_macro_err_qs; |
| logic err_code_macro_err_wd; |
| logic std_fault_status_reg_intg_err_qs; |
| logic std_fault_status_prog_intg_err_qs; |
| logic std_fault_status_lcmgr_err_qs; |
| logic std_fault_status_lcmgr_intg_err_qs; |
| logic std_fault_status_arb_fsm_err_qs; |
| logic std_fault_status_storage_err_qs; |
| logic std_fault_status_phy_fsm_err_qs; |
| logic std_fault_status_ctrl_cnt_err_qs; |
| logic std_fault_status_fifo_err_qs; |
| logic fault_status_op_err_qs; |
| logic fault_status_mp_err_qs; |
| logic fault_status_rd_err_qs; |
| logic fault_status_prog_err_qs; |
| logic fault_status_prog_win_err_qs; |
| logic fault_status_prog_type_err_qs; |
| logic fault_status_seed_err_qs; |
| logic fault_status_phy_relbl_err_qs; |
| logic fault_status_phy_storage_err_qs; |
| logic fault_status_spurious_ack_qs; |
| logic fault_status_arb_err_qs; |
| logic fault_status_host_gnt_err_qs; |
| logic [19:0] err_addr_qs; |
| logic ecc_single_err_cnt_we; |
| logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_qs; |
| logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_wd; |
| logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_qs; |
| logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_wd; |
| logic [19:0] ecc_single_err_addr_0_qs; |
| logic [19:0] ecc_single_err_addr_1_qs; |
| logic phy_alert_cfg_we; |
| logic phy_alert_cfg_alert_ack_qs; |
| logic phy_alert_cfg_alert_ack_wd; |
| logic phy_alert_cfg_alert_trig_qs; |
| logic phy_alert_cfg_alert_trig_wd; |
| logic phy_status_init_wip_qs; |
| logic phy_status_prog_normal_avail_qs; |
| logic phy_status_prog_repair_avail_qs; |
| logic scratch_we; |
| logic [31:0] scratch_qs; |
| logic [31:0] scratch_wd; |
| logic fifo_lvl_we; |
| logic [4:0] fifo_lvl_prog_qs; |
| logic [4:0] fifo_lvl_prog_wd; |
| logic [4:0] fifo_lvl_rd_qs; |
| logic [4:0] fifo_lvl_rd_wd; |
| logic fifo_rst_we; |
| logic fifo_rst_qs; |
| logic fifo_rst_wd; |
| logic curr_fifo_lvl_re; |
| logic [4:0] curr_fifo_lvl_prog_qs; |
| logic [4:0] curr_fifo_lvl_rd_qs; |
| |
| // Register instances |
| // R[intr_state]: V(False) |
| // F[prog_empty]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_prog_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_prog_empty_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.prog_empty.de), |
| .d (hw2reg.intr_state.prog_empty.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.prog_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_prog_empty_qs) |
| ); |
| |
| // F[prog_lvl]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_prog_lvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_prog_lvl_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.prog_lvl.de), |
| .d (hw2reg.intr_state.prog_lvl.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.prog_lvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_prog_lvl_qs) |
| ); |
| |
| // F[rd_full]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_rd_full ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_rd_full_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.rd_full.de), |
| .d (hw2reg.intr_state.rd_full.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.rd_full.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_rd_full_qs) |
| ); |
| |
| // F[rd_lvl]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_rd_lvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_rd_lvl_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.rd_lvl.de), |
| .d (hw2reg.intr_state.rd_lvl.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.rd_lvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_rd_lvl_qs) |
| ); |
| |
| // F[op_done]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_op_done ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_op_done_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.op_done.de), |
| .d (hw2reg.intr_state.op_done.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.op_done.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_op_done_qs) |
| ); |
| |
| // F[corr_err]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_corr_err ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_corr_err_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.corr_err.de), |
| .d (hw2reg.intr_state.corr_err.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.corr_err.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_corr_err_qs) |
| ); |
| |
| |
| // R[intr_enable]: V(False) |
| // F[prog_empty]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_prog_empty ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_prog_empty_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.prog_empty.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_prog_empty_qs) |
| ); |
| |
| // F[prog_lvl]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_prog_lvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_prog_lvl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.prog_lvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_prog_lvl_qs) |
| ); |
| |
| // F[rd_full]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_rd_full ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_rd_full_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.rd_full.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_rd_full_qs) |
| ); |
| |
| // F[rd_lvl]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_rd_lvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_rd_lvl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.rd_lvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_rd_lvl_qs) |
| ); |
| |
| // F[op_done]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_op_done ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_op_done_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.op_done.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_op_done_qs) |
| ); |
| |
| // F[corr_err]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_corr_err ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_corr_err_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.corr_err.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_corr_err_qs) |
| ); |
| |
| |
| // R[intr_test]: V(True) |
| logic intr_test_qe; |
| logic [5:0] intr_test_flds_we; |
| assign intr_test_qe = &intr_test_flds_we; |
| // F[prog_empty]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_prog_empty ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_prog_empty_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[0]), |
| .q (reg2hw.intr_test.prog_empty.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.prog_empty.qe = intr_test_qe; |
| |
| // F[prog_lvl]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_prog_lvl ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_prog_lvl_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[1]), |
| .q (reg2hw.intr_test.prog_lvl.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.prog_lvl.qe = intr_test_qe; |
| |
| // F[rd_full]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_rd_full ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_rd_full_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[2]), |
| .q (reg2hw.intr_test.rd_full.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.rd_full.qe = intr_test_qe; |
| |
| // F[rd_lvl]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_rd_lvl ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_rd_lvl_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[3]), |
| .q (reg2hw.intr_test.rd_lvl.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.rd_lvl.qe = intr_test_qe; |
| |
| // F[op_done]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_op_done ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_op_done_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[4]), |
| .q (reg2hw.intr_test.op_done.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.op_done.qe = intr_test_qe; |
| |
| // F[corr_err]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_corr_err ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_corr_err_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[5]), |
| .q (reg2hw.intr_test.corr_err.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.corr_err.qe = intr_test_qe; |
| |
| |
| // R[alert_test]: V(True) |
| logic alert_test_qe; |
| logic [4:0] alert_test_flds_we; |
| assign alert_test_qe = &alert_test_flds_we; |
| // F[recov_err]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_recov_err ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_recov_err_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[0]), |
| .q (reg2hw.alert_test.recov_err.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.recov_err.qe = alert_test_qe; |
| |
| // F[fatal_std_err]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_fatal_std_err ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_fatal_std_err_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[1]), |
| .q (reg2hw.alert_test.fatal_std_err.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.fatal_std_err.qe = alert_test_qe; |
| |
| // F[fatal_err]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_fatal_err ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_fatal_err_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[2]), |
| .q (reg2hw.alert_test.fatal_err.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.fatal_err.qe = alert_test_qe; |
| |
| // F[fatal_prim_flash_alert]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_fatal_prim_flash_alert ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_fatal_prim_flash_alert_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[3]), |
| .q (reg2hw.alert_test.fatal_prim_flash_alert.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.fatal_prim_flash_alert.qe = alert_test_qe; |
| |
| // F[recov_prim_flash_alert]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_recov_prim_flash_alert ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_recov_prim_flash_alert_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[4]), |
| .q (reg2hw.alert_test.recov_prim_flash_alert.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.recov_prim_flash_alert.qe = alert_test_qe; |
| |
| |
| // R[dis]: V(False) |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (4'h9) |
| ) u_dis ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dis_we), |
| .wd (dis_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dis.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dis_qs) |
| ); |
| |
| |
| // R[exec]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (32'h0) |
| ) u_exec ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (exec_we), |
| .wd (exec_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.exec.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (exec_qs) |
| ); |
| |
| |
| // R[init]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1S), |
| .RESVAL (1'h0) |
| ) u_init ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (init_we), |
| .wd (init_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.init.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (init_qs) |
| ); |
| |
| |
| // R[ctrl_regwen]: V(True) |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_ctrl_regwen ( |
| .re (ctrl_regwen_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.ctrl_regwen.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (ctrl_regwen_qs) |
| ); |
| |
| |
| // R[control]: V(False) |
| // Create REGWEN-gated WE signal |
| logic control_gated_we; |
| assign control_gated_we = control_we & ctrl_regwen_qs; |
| // F[start]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_start ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_start_wd), |
| |
| // from internal hardware |
| .de (hw2reg.control.start.de), |
| .d (hw2reg.control.start.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.start.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_start_qs) |
| ); |
| |
| // F[op]: 5:4 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h0) |
| ) u_control_op ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_op_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.op.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_op_qs) |
| ); |
| |
| // F[prog_sel]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_prog_sel ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_prog_sel_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.prog_sel.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_prog_sel_qs) |
| ); |
| |
| // F[erase_sel]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_erase_sel ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_erase_sel_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.erase_sel.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_erase_sel_qs) |
| ); |
| |
| // F[partition_sel]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_control_partition_sel ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_partition_sel_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.partition_sel.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_partition_sel_qs) |
| ); |
| |
| // F[info_sel]: 10:9 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h0) |
| ) u_control_info_sel ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_info_sel_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.info_sel.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_info_sel_qs) |
| ); |
| |
| // F[num]: 27:16 |
| prim_subreg #( |
| .DW (12), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (12'h0) |
| ) u_control_num ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (control_gated_we), |
| .wd (control_num_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.control.num.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (control_num_qs) |
| ); |
| |
| |
| // R[addr]: V(False) |
| // Create REGWEN-gated WE signal |
| logic addr_gated_we; |
| assign addr_gated_we = addr_we & ctrl_regwen_qs; |
| prim_subreg #( |
| .DW (20), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (20'h0) |
| ) u_addr ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (addr_gated_we), |
| .wd (addr_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.addr.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (addr_qs) |
| ); |
| |
| |
| // R[prog_type_en]: V(False) |
| // Create REGWEN-gated WE signal |
| logic prog_type_en_gated_we; |
| assign prog_type_en_gated_we = prog_type_en_we & ctrl_regwen_qs; |
| // F[normal]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_prog_type_en_normal ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (prog_type_en_gated_we), |
| .wd (prog_type_en_normal_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prog_type_en.normal.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (prog_type_en_normal_qs) |
| ); |
| |
| // F[repair]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_prog_type_en_repair ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (prog_type_en_gated_we), |
| .wd (prog_type_en_repair_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prog_type_en.repair.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (prog_type_en_repair_qs) |
| ); |
| |
| |
| // R[erase_suspend]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_erase_suspend ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (erase_suspend_we), |
| .wd (erase_suspend_wd), |
| |
| // from internal hardware |
| .de (hw2reg.erase_suspend.de), |
| .d (hw2reg.erase_suspend.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.erase_suspend.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (erase_suspend_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_0_we), |
| .wd (region_cfg_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_1_we), |
| .wd (region_cfg_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_2_we), |
| .wd (region_cfg_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_3_we), |
| .wd (region_cfg_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_4_we), |
| .wd (region_cfg_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_5_we), |
| .wd (region_cfg_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_6_we), |
| .wd (region_cfg_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg region_cfg_regwen |
| // R[region_cfg_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_region_cfg_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (region_cfg_regwen_7_we), |
| .wd (region_cfg_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (region_cfg_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mp_region_cfg |
| // R[mp_region_cfg_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_0_gated_we; |
| assign mp_region_cfg_0_gated_we = mp_region_cfg_0_we & region_cfg_regwen_0_qs; |
| // F[en_0]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_en_0_qs) |
| ); |
| |
| // F[rd_en_0]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_rd_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_rd_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_rd_en_0_qs) |
| ); |
| |
| // F[prog_en_0]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_prog_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_prog_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_prog_en_0_qs) |
| ); |
| |
| // F[erase_en_0]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_erase_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_erase_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_erase_en_0_qs) |
| ); |
| |
| // F[scramble_en_0]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_scramble_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_scramble_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_scramble_en_0_qs) |
| ); |
| |
| // F[ecc_en_0]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_ecc_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_ecc_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_ecc_en_0_qs) |
| ); |
| |
| // F[he_en_0]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_0_he_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_0_gated_we), |
| .wd (mp_region_cfg_0_he_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[0].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_0_he_en_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mp_region_cfg |
| // R[mp_region_cfg_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_1_gated_we; |
| assign mp_region_cfg_1_gated_we = mp_region_cfg_1_we & region_cfg_regwen_1_qs; |
| // F[en_1]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_en_1_qs) |
| ); |
| |
| // F[rd_en_1]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_rd_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_rd_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_rd_en_1_qs) |
| ); |
| |
| // F[prog_en_1]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_prog_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_prog_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_prog_en_1_qs) |
| ); |
| |
| // F[erase_en_1]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_erase_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_erase_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_erase_en_1_qs) |
| ); |
| |
| // F[scramble_en_1]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_scramble_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_scramble_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_scramble_en_1_qs) |
| ); |
| |
| // F[ecc_en_1]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_ecc_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_ecc_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_ecc_en_1_qs) |
| ); |
| |
| // F[he_en_1]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_1_he_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_1_gated_we), |
| .wd (mp_region_cfg_1_he_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[1].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_1_he_en_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mp_region_cfg |
| // R[mp_region_cfg_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_2_gated_we; |
| assign mp_region_cfg_2_gated_we = mp_region_cfg_2_we & region_cfg_regwen_2_qs; |
| // F[en_2]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_en_2_qs) |
| ); |
| |
| // F[rd_en_2]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_rd_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_rd_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_rd_en_2_qs) |
| ); |
| |
| // F[prog_en_2]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_prog_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_prog_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_prog_en_2_qs) |
| ); |
| |
| // F[erase_en_2]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_erase_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_erase_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_erase_en_2_qs) |
| ); |
| |
| // F[scramble_en_2]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_scramble_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_scramble_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_scramble_en_2_qs) |
| ); |
| |
| // F[ecc_en_2]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_ecc_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_ecc_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_ecc_en_2_qs) |
| ); |
| |
| // F[he_en_2]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_2_he_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_2_gated_we), |
| .wd (mp_region_cfg_2_he_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[2].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_2_he_en_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mp_region_cfg |
| // R[mp_region_cfg_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_3_gated_we; |
| assign mp_region_cfg_3_gated_we = mp_region_cfg_3_we & region_cfg_regwen_3_qs; |
| // F[en_3]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_en_3_qs) |
| ); |
| |
| // F[rd_en_3]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_rd_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_rd_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_rd_en_3_qs) |
| ); |
| |
| // F[prog_en_3]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_prog_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_prog_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_prog_en_3_qs) |
| ); |
| |
| // F[erase_en_3]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_erase_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_erase_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_erase_en_3_qs) |
| ); |
| |
| // F[scramble_en_3]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_scramble_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_scramble_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_scramble_en_3_qs) |
| ); |
| |
| // F[ecc_en_3]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_ecc_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_ecc_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_ecc_en_3_qs) |
| ); |
| |
| // F[he_en_3]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_3_he_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_3_gated_we), |
| .wd (mp_region_cfg_3_he_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[3].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_3_he_en_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mp_region_cfg |
| // R[mp_region_cfg_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_4_gated_we; |
| assign mp_region_cfg_4_gated_we = mp_region_cfg_4_we & region_cfg_regwen_4_qs; |
| // F[en_4]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_en_4_qs) |
| ); |
| |
| // F[rd_en_4]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_rd_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_rd_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_rd_en_4_qs) |
| ); |
| |
| // F[prog_en_4]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_prog_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_prog_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_prog_en_4_qs) |
| ); |
| |
| // F[erase_en_4]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_erase_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_erase_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_erase_en_4_qs) |
| ); |
| |
| // F[scramble_en_4]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_scramble_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_scramble_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_scramble_en_4_qs) |
| ); |
| |
| // F[ecc_en_4]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_ecc_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_ecc_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_ecc_en_4_qs) |
| ); |
| |
| // F[he_en_4]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_4_he_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_4_gated_we), |
| .wd (mp_region_cfg_4_he_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[4].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_4_he_en_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mp_region_cfg |
| // R[mp_region_cfg_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_5_gated_we; |
| assign mp_region_cfg_5_gated_we = mp_region_cfg_5_we & region_cfg_regwen_5_qs; |
| // F[en_5]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_en_5_qs) |
| ); |
| |
| // F[rd_en_5]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_rd_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_rd_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_rd_en_5_qs) |
| ); |
| |
| // F[prog_en_5]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_prog_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_prog_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_prog_en_5_qs) |
| ); |
| |
| // F[erase_en_5]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_erase_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_erase_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_erase_en_5_qs) |
| ); |
| |
| // F[scramble_en_5]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_scramble_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_scramble_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_scramble_en_5_qs) |
| ); |
| |
| // F[ecc_en_5]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_ecc_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_ecc_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_ecc_en_5_qs) |
| ); |
| |
| // F[he_en_5]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_5_he_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_5_gated_we), |
| .wd (mp_region_cfg_5_he_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[5].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_5_he_en_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mp_region_cfg |
| // R[mp_region_cfg_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_6_gated_we; |
| assign mp_region_cfg_6_gated_we = mp_region_cfg_6_we & region_cfg_regwen_6_qs; |
| // F[en_6]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_en_6_qs) |
| ); |
| |
| // F[rd_en_6]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_rd_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_rd_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_rd_en_6_qs) |
| ); |
| |
| // F[prog_en_6]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_prog_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_prog_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_prog_en_6_qs) |
| ); |
| |
| // F[erase_en_6]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_erase_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_erase_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_erase_en_6_qs) |
| ); |
| |
| // F[scramble_en_6]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_scramble_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_scramble_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_scramble_en_6_qs) |
| ); |
| |
| // F[ecc_en_6]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_ecc_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_ecc_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_ecc_en_6_qs) |
| ); |
| |
| // F[he_en_6]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_6_he_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_6_gated_we), |
| .wd (mp_region_cfg_6_he_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[6].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_6_he_en_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mp_region_cfg |
| // R[mp_region_cfg_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_cfg_7_gated_we; |
| assign mp_region_cfg_7_gated_we = mp_region_cfg_7_we & region_cfg_regwen_7_qs; |
| // F[en_7]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_en_7_qs) |
| ); |
| |
| // F[rd_en_7]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_rd_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_rd_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_rd_en_7_qs) |
| ); |
| |
| // F[prog_en_7]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_prog_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_prog_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_prog_en_7_qs) |
| ); |
| |
| // F[erase_en_7]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_erase_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_erase_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_erase_en_7_qs) |
| ); |
| |
| // F[scramble_en_7]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_scramble_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_scramble_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_scramble_en_7_qs) |
| ); |
| |
| // F[ecc_en_7]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_ecc_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_ecc_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_ecc_en_7_qs) |
| ); |
| |
| // F[he_en_7]: 27:24 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_mp_region_cfg_7_he_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_cfg_7_gated_we), |
| .wd (mp_region_cfg_7_he_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region_cfg[7].he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_cfg_7_he_en_7_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mp_region |
| // R[mp_region_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_0_gated_we; |
| assign mp_region_0_gated_we = mp_region_0_we & region_cfg_regwen_0_qs; |
| // F[base_0]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_0_base_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_0_gated_we), |
| .wd (mp_region_0_base_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[0].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_0_base_0_qs) |
| ); |
| |
| // F[size_0]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_0_size_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_0_gated_we), |
| .wd (mp_region_0_size_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[0].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_0_size_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mp_region |
| // R[mp_region_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_1_gated_we; |
| assign mp_region_1_gated_we = mp_region_1_we & region_cfg_regwen_1_qs; |
| // F[base_1]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_1_base_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_1_gated_we), |
| .wd (mp_region_1_base_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[1].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_1_base_1_qs) |
| ); |
| |
| // F[size_1]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_1_size_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_1_gated_we), |
| .wd (mp_region_1_size_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[1].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_1_size_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mp_region |
| // R[mp_region_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_2_gated_we; |
| assign mp_region_2_gated_we = mp_region_2_we & region_cfg_regwen_2_qs; |
| // F[base_2]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_2_base_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_2_gated_we), |
| .wd (mp_region_2_base_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[2].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_2_base_2_qs) |
| ); |
| |
| // F[size_2]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_2_size_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_2_gated_we), |
| .wd (mp_region_2_size_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[2].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_2_size_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mp_region |
| // R[mp_region_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_3_gated_we; |
| assign mp_region_3_gated_we = mp_region_3_we & region_cfg_regwen_3_qs; |
| // F[base_3]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_3_base_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_3_gated_we), |
| .wd (mp_region_3_base_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[3].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_3_base_3_qs) |
| ); |
| |
| // F[size_3]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_3_size_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_3_gated_we), |
| .wd (mp_region_3_size_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[3].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_3_size_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mp_region |
| // R[mp_region_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_4_gated_we; |
| assign mp_region_4_gated_we = mp_region_4_we & region_cfg_regwen_4_qs; |
| // F[base_4]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_4_base_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_4_gated_we), |
| .wd (mp_region_4_base_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[4].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_4_base_4_qs) |
| ); |
| |
| // F[size_4]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_4_size_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_4_gated_we), |
| .wd (mp_region_4_size_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[4].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_4_size_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mp_region |
| // R[mp_region_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_5_gated_we; |
| assign mp_region_5_gated_we = mp_region_5_we & region_cfg_regwen_5_qs; |
| // F[base_5]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_5_base_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_5_gated_we), |
| .wd (mp_region_5_base_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[5].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_5_base_5_qs) |
| ); |
| |
| // F[size_5]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_5_size_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_5_gated_we), |
| .wd (mp_region_5_size_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[5].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_5_size_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mp_region |
| // R[mp_region_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_6_gated_we; |
| assign mp_region_6_gated_we = mp_region_6_we & region_cfg_regwen_6_qs; |
| // F[base_6]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_6_base_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_6_gated_we), |
| .wd (mp_region_6_base_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[6].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_6_base_6_qs) |
| ); |
| |
| // F[size_6]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_6_size_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_6_gated_we), |
| .wd (mp_region_6_size_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[6].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_6_size_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mp_region |
| // R[mp_region_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mp_region_7_gated_we; |
| assign mp_region_7_gated_we = mp_region_7_we & region_cfg_regwen_7_qs; |
| // F[base_7]: 8:0 |
| prim_subreg #( |
| .DW (9), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (9'h0) |
| ) u_mp_region_7_base_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_7_gated_we), |
| .wd (mp_region_7_base_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[7].base.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_7_base_7_qs) |
| ); |
| |
| // F[size_7]: 18:9 |
| prim_subreg #( |
| .DW (10), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (10'h0) |
| ) u_mp_region_7_size_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mp_region_7_gated_we), |
| .wd (mp_region_7_size_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mp_region[7].size.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mp_region_7_size_7_qs) |
| ); |
| |
| |
| // R[default_region]: V(False) |
| // F[rd_en]: 3:0 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_default_region_rd_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (default_region_we), |
| .wd (default_region_rd_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.default_region.rd_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (default_region_rd_en_qs) |
| ); |
| |
| // F[prog_en]: 7:4 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_default_region_prog_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (default_region_we), |
| .wd (default_region_prog_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.default_region.prog_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (default_region_prog_en_qs) |
| ); |
| |
| // F[erase_en]: 11:8 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_default_region_erase_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (default_region_we), |
| .wd (default_region_erase_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.default_region.erase_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (default_region_erase_en_qs) |
| ); |
| |
| // F[scramble_en]: 15:12 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_default_region_scramble_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (default_region_we), |
| .wd (default_region_scramble_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.default_region.scramble_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (default_region_scramble_en_qs) |
| ); |
| |
| // F[ecc_en]: 19:16 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_default_region_ecc_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (default_region_we), |
| .wd (default_region_ecc_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.default_region.ecc_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (default_region_ecc_en_qs) |
| ); |
| |
| // F[he_en]: 23:20 |
| prim_subreg #( |
| .DW (4), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (4'h9) |
| ) u_default_region_he_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (default_region_we), |
| .wd (default_region_he_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.default_region.he_en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (default_region_he_en_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_bank0_info0_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (bank0_info0_regwen_0_we), |
| .wd (bank0_info0_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (bank0_info0_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_bank0_info0_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (bank0_info0_regwen_1_we), |
| .wd (bank0_info0_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (bank0_info0_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_bank0_info0_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (bank0_info0_regwen_2_we), |
| .wd (bank0_info0_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (bank0_info0_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_bank0_info0_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (bank0_info0_regwen_3_we), |
| .wd (bank0_info0_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (bank0_info0_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_bank0_info0_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (bank0_info0_regwen_4_we), |
| .wd (bank0_info0_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (bank0_info0_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_bank0_info0_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (bank0_info0_regwen_5_we), |
| .wd (bank0_info0_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (bank0_info0_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg bank0_info0_regwen |
| // R[bank0_info0_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .
|