)]}'
{
  "commit": "cb1c9d002eff37909bb870d704246f804d2364c6",
  "tree": "7190fb2ed26ae5018ee03901c60a895a5be4cfd8",
  "parents": [
    "6f2af49b630915350d808df4a7a3332185b64689"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Mon Nov 15 17:18:25 2021 -0800"
  },
  "committer": {
    "name": "Srikrishna Iyer",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Tue Nov 16 10:37:34 2021 -0800"
  },
  "message": "[chip dv] Add support for tiled RAM instances\n\n- Adds support for attaching multiple mem backdoor util instances for\nmultiply-tiled RAMs in the design.\n- Number of tiles for main / ret SRAM is a runtime setting that is set\nto 1 in the open source testbench with a generic model.\n- Extended class can set it to whatever the correct value is for that\nenvironment.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
  "tree_diff": [
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