diff --git a/hw/ip/pinmux/doc/pinmux.md b/hw/ip/pinmux/doc/pinmux.md
index 7b03af3..242a6cb 100644
--- a/hw/ip/pinmux/doc/pinmux.md
+++ b/hw/ip/pinmux/doc/pinmux.md
@@ -86,16 +86,16 @@
 {{% section2 Signals }}
 The table below lists the `pinmux` signals. The number of IOs is parametric, and hence the signals are stacked in packed arrays.
 
-Signal                         | Direction        | Type           | Description
--------------------------------|------------------|----------------|---------------
-`tl_i`                         | `input`          | `tl_h2d_t`     | TileLink-UL input for control register access.
-`tl_o`                         | `output`         | `tl_d2h_t`     | TileLink-UL output for control register access.
-`periph_out_i[NPeriphOut-1:0]` | `input`          | packed `logic` | Signals from `NPeriphOut` peripheral outputs coming into the pinmux.
-`periph_oe_i[NPeriphOut-1:0]`  | `input`          | packed `logic` | Signals from `NPeriphOut` peripheral output enables coming into the pinmux.
-`periph_in_i[NPeriphIn-1:0]`   | `output`         | packed `logic` | Signals to `NPeriphIn` peripherals coming from the pinmux.
-`mio_out_o[NMioPads-1:0]`      | `output`         | packed `logic` | Signals to `NMioPads` bidirectional pads as output data.
-`mio_oe_o[NMioPads-1:0]`       | `output`         | packed `logic` | Signals to `NMioPads` bidirectional pads as output enables.
-`mio_in_i[NMioPads-1:0]`       | `input`          | packed `logic` | Signals from `NMioPads` bidirectional pads as input data.
+Signal                               | Direction        | Type           | Description
+-------------------------------------|------------------|----------------|---------------
+`tl_i`                               | `input`          | `tl_h2d_t`     | TileLink-UL input for control register access.
+`tl_o`                               | `output`         | `tl_d2h_t`     | TileLink-UL output for control register access.
+`periph_to_mio_i[NPeriphOut-1:0]`    | `input`          | packed `logic` | Signals from `NPeriphOut` peripheral outputs coming into the pinmux.
+`periph_to_mio_oe_i[NPeriphOut-1:0]` | `input`          | packed `logic` | Signals from `NPeriphOut` peripheral output enables coming into the pinmux.
+`mio_to_periph_o[NPeriphIn-1:0]`     | `output`         | packed `logic` | Signals to `NPeriphIn` peripherals coming from the pinmux.
+`mio_out_o[NMioPads-1:0]`            | `output`         | packed `logic` | Signals to `NMioPads` bidirectional pads as output data.
+`mio_oe_o[NMioPads-1:0]`             | `output`         | packed `logic` | Signals to `NMioPads` bidirectional pads as output enables.
+`mio_in_i[NMioPads-1:0]`             | `input`          | packed `logic` | Signals from `NMioPads` bidirectional pads as input data.
 
 {{% section2 Programmers Guide }}
 
diff --git a/hw/ip/pinmux/rtl/pinmux.sv b/hw/ip/pinmux/rtl/pinmux.sv
index 278fe2a..01e1b0a 100644
--- a/hw/ip/pinmux/rtl/pinmux.sv
+++ b/hw/ip/pinmux/rtl/pinmux.sv
@@ -12,9 +12,9 @@
   input  tlul_pkg::tl_h2d_t                     tl_i,
   output tlul_pkg::tl_d2h_t                     tl_o,
   // Peripheral side
-  input        [pinmux_reg_pkg::NPeriphOut-1:0] periph_out_i,
-  input        [pinmux_reg_pkg::NPeriphOut-1:0] periph_oe_i,
-  output logic [pinmux_reg_pkg::NPeriphIn-1:0]  periph_in_o,
+  input        [pinmux_reg_pkg::NPeriphOut-1:0] periph_to_mio_i,
+  input        [pinmux_reg_pkg::NPeriphOut-1:0] periph_to_mio_oe_i,
+  output logic [pinmux_reg_pkg::NPeriphIn-1:0]  mio_to_periph_o,
   // Pad side
   output logic [pinmux_reg_pkg::NMioPads-1:0]   mio_out_o,
   output logic [pinmux_reg_pkg::NMioPads-1:0]   mio_oe_o,
@@ -46,7 +46,7 @@
     // possible defaults: constant 0 or 1
     assign data_mux = $size(data_mux)'({mio_in_i, 1'b1, 1'b0});
     // index using configured insel
-    assign periph_in_o[k] = data_mux[reg2hw.periph_insel[k].q];
+    assign mio_to_periph_o[k] = data_mux[reg2hw.periph_insel[k].q];
     // disallow undefined entries
     `ASSUME(InSelRange_A, reg2hw.periph_insel[k].q < pinmux_reg_pkg::NMioPads + 2, clk_i, rst_ni)
   end
@@ -59,8 +59,8 @@
     logic [pinmux_reg_pkg::NPeriphOut+3-1:0] data_mux, oe_mux;
     // stack output data/enable and default signals for convenient indexing below
     // possible defaults: 0, 1 or 2 (high-Z)
-    assign data_mux = $size(data_mux)'({periph_out_i, 1'b0, 1'b1, 1'b0});
-    assign oe_mux   = $size(oe_mux)'({periph_oe_i,  1'b0, 1'b1, 1'b1});
+    assign data_mux = $size(data_mux)'({periph_to_mio_i, 1'b0, 1'b1, 1'b0});
+    assign oe_mux   = $size(oe_mux)'({periph_to_mio_oe_i,  1'b0, 1'b1, 1'b1});
     // index using configured outsel
     assign mio_out_o[k] = data_mux[reg2hw.mio_outsel[k].q];
     assign mio_oe_o[k]  = oe_mux[reg2hw.mio_outsel[k].q];