tree 9bd36d3bef9b1ef8a8cf6261c550e1d5f5882126
parent 86e6a563e0877223e868ed0b3da20262e5d4f7b7
author Philipp Wagner <phw@lowrisc.org> 1614785693 +0000
committer Philipp Wagner <mail@philipp-wagner.com> 1633589834 +0100

[rv_plic] Produce top_earlgrey instance of rv_plic with ipgen

This rather large commit makes rv_plic an IP template, and then uses
ipgen to instantiate the block with the right parametrization for
top_earlgrey.

In contrast to the previous approach, `hw/top_earlgrey/ip_autogen`
now contains a full copy of rv_plic under a unique FuseSoC core
name, `lowrisc:opentitan:top_earlgrey_rv_plic`.

Unfortunately, doing so requires a fair amount of reshuffling, which
cannot be easily split into individual commits while keeping the whole
tree building. Here's what was done:

* Move `ip/rv_plic` to `ip_templates/rv_plic`.
* Remove the `reg_rv_plic.py` tooling, which is now replaced by ipgen.
* Change `topgen.py` to generate the toplevel-specific instance of
  `rv_plic` through ipgen.
* Adjust references in the documentation as necessary.
* Adjust the software build as necessary.
* The FPV testbench is now only run for the Earl Grey-instantiated IP
  block, there is no more "generic" testbench. Update all references
  pointing to the testbench.

Signed-off-by: Philipp Wagner <phw@lowrisc.org>