diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 34d7193..8524a57 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -6,7 +6,8 @@
 { name: "earlgrey",
   type: "top",
 
-  datawidth: "32",  # 32-bit datawidth
+  # 32-bit datawidth
+  datawidth: "32",
 
   // This is the clock data strcture of the design.
   // The hier path refers to the clock reference path (struct / port)
@@ -74,57 +75,69 @@
       { name: "peri",    src:"top", sw_cg: "yes",  unique: "no"   }
       { name: "timers",  src:"top", sw_cg: "no"                   }
       { name: "proc",
-        src: "no"
-        sw_cg: "no"
-        unique: "no"
+        src: "no",
+        sw_cg: "no",
+        unique: "no",
         clocks: {
           clk_proc_main: main
         }
       }
     ],
-  }
+  },
 
-  // Reset attributes
-  // name: name of reset.
-  //
-  // gen: whether the reset is generated
-  // 1: it is a generated reset inside rstmgr
-  // 0: it is a hardwired design reset inside rstmgr (roots and por)
-  //
-  // type: the reset type [ext, top]
-  // ext: the reset is coming in from the ports, external to earlgrey
-  // int: the reset is only used inside rstmgr
-  // top: the reset is output from rstmgr to top level struct
-  //
-  // root: The parent reset
-  // If type is "ext", there is no root, since it is external
-  //
-  // domain: The power domain
-  // If no domain, it means there is no choice, just inherits from root.
-  // Otherwise, selects the domain to which it is related
-  // 0 is defaulted for always on.
-  // TBD: This should eventually be changed to a name->index project wide lookup
-  //
-  // clk:  related clock domain for synchronous release
-  // If type is "por", there is not related clock, since it is
-  // likely external or generated from a voltage comparator
-  //
-  resets: [
-    { name: "rst_ni",      gen: 0, type: "ext"                                                  }
-    { name: "por_aon",     gen: 0, type: "top",              root: "rst_ni",  clk: "aon"        }
-    { name: "lc_src",      gen: 0, type: "int",              root: "por",     clk: "io_div2"    }
-    { name: "sys_src",     gen: 0, type: "int",              root: "por",     clk: "io_div2"    }
-    { name: "por",         gen: 1, type: "top",              root: "por_aon", clk: "main"       }
-    { name: "por_io",      gen: 1, type: "top",              root: "por_aon", clk: "io"         }
-    { name: "por_io_div2", gen: 1, type: "top",              root: "por_aon", clk: "io_div2"    }
-    { name: "por_usb",     gen: 1, type: "top",              root: "por_aon", clk: "usb"        }
-    { name: "lc",          gen: 1, type: "top", domain: "0", root: "lc_src",  clk: "io_div2"    }
-    { name: "sys",         gen: 1, type: "top", domain: "0", root: "sys_src", clk: "main"       }
-    { name: "sys_io",      gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2"    }
-    { name: "sys_aon",     gen: 1, type: "top", domain: "0", root: "sys_src", clk: "aon"        }
-    { name: "spi_device",  gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2", sw: 1 }
-    { name: "usb",         gen: 1, type: "top", domain: "0", root: "sys_src", clk: "usb",     sw: 1 }
-  ]
+  // This is the reset data strcture of the design.
+  // The hier path refers to the reset reference path (struct / port)
+  //   - The top/ext desgination follows the same scheme as inter-module
+  // The node key represents all the known resets in the design
+  resets: {
+
+    hier_paths: {
+      top: "rstmgr_resets.", // top level is a struct
+      ext: "",               // ext is a port of the clock name
+    },
+
+    // Reset node attributes
+    // name: name of reset.
+    //
+    // gen: whether the reset is generated
+    // true: it is a generated reset inside rstmgr
+    // false: it is a hardwired design reset inside rstmgr (roots and por)
+    //
+    // type: the reset type [ext, top]
+    // ext: the reset is coming in from the ports, external to earlgrey
+    // int: the reset is only used inside rstmgr
+    // top: the reset is output from rstmgr to top level struct
+    //
+    // parent: The parent reset
+    // If type is "ext", there is no root, since it is external
+    //
+    // domain: The power domain
+    // If no domain, it means there is no choice, just inherits from root.
+    // Otherwise, selects the domain to which it is related
+    // 0 is defaulted for always on.
+    // TBD: This should eventually be changed to a name->index project wide lookup
+    //
+    // clk:  related clock domain for synchronous release
+    // If type is "por", there is not related clock, since it is
+    // likely external or generated from a voltage comparator
+    //
+    nodes: [
+      { name: "rst_ni",      gen: false, type: "ext"                                                  }
+      { name: "por_aon",     gen: false, type: "top",              parent: "rst_ni",  clk: "aon"        }
+      { name: "lc_src",      gen: false, type: "int",              parent: "por",     clk: "io_div2"    }
+      { name: "sys_src",     gen: false, type: "int",              parent: "por",     clk: "io_div2"    }
+      { name: "por",         gen: true,  type: "top",              parent: "por_aon", clk: "main"       }
+      { name: "por_io",      gen: true,  type: "top",              parent: "por_aon", clk: "io"         }
+      { name: "por_io_div2", gen: true,  type: "top",              parent: "por_aon", clk: "io_div2"    }
+      { name: "por_usb",     gen: true,  type: "top",              parent: "por_aon", clk: "usb"        }
+      { name: "lc",          gen: true,  type: "top", domain: "0", parent: "lc_src",  clk: "io_div2"    }
+      { name: "sys",         gen: true,  type: "top", domain: "0", parent: "sys_src", clk: "main"       }
+      { name: "sys_io",      gen: true,  type: "top", domain: "0", parent: "sys_src", clk: "io_div2"    }
+      { name: "sys_aon",     gen: true,  type: "top", domain: "0", parent: "sys_src", clk: "aon"        }
+      { name: "spi_device",  gen: true,  type: "top", domain: "0", parent: "sys_src", clk: "io_div2",  sw: 1 }
+      { name: "usb",         gen: true,  type: "top", domain: "0", parent: "sys_src", clk: "usb", sw: 1 }
+    ]
+  }
 
   // Number of cores: used in rv_plic and timer
   num_cores: "1",