diff --git a/hw/ip/aes/pre_sca/alma/README.md b/hw/ip/aes/pre_sca/alma/README.md
index 8c074e4..61b362a 100644
--- a/hw/ip/aes/pre_sca/alma/README.md
+++ b/hw/ip/aes/pre_sca/alma/README.md
@@ -154,7 +154,7 @@
 1. The first step involves the parsing the synthesized netlist.
    ```sh
    ./parse.py --top-module aes_sbox \
-      --source ${REPO_TOP}/hw/ip/aes/pre_syn/syn_out/latest/generated/aes_sbox.pre_map.v \
+      --source ${REPO_TOP}/hw/ip/aes/pre_syn/syn_out/latest/generated/aes_sbox.alma.v \
       --netlist tmp/circuit.v --log-yosys
    ```
 
diff --git a/hw/ip/aes/pre_sca/alma/verify_aes.sh b/hw/ip/aes/pre_sca/alma/verify_aes.sh
index f74c804..b442564 100755
--- a/hw/ip/aes/pre_sca/alma/verify_aes.sh
+++ b/hw/ip/aes/pre_sca/alma/verify_aes.sh
@@ -28,7 +28,7 @@
 
 # Parse
 ./parse.py --top-module ${TOP_MODULE} \
---source ${REPO_TOP}/hw/ip/aes/pre_syn/syn_out/latest/generated/${TOP_MODULE}.pre_map.v \
+--source ${REPO_TOP}/hw/ip/aes/pre_syn/syn_out/latest/generated/${TOP_MODULE}.alma.v \
 --netlist tmp/circuit.v --log-yosys
 
 # Trace
diff --git a/hw/ip/aes/pre_syn/tcl/lr_synth_flow_var_setup.tcl b/hw/ip/aes/pre_syn/tcl/lr_synth_flow_var_setup.tcl
index 64354c5..48da78a 100644
--- a/hw/ip/aes/pre_syn/tcl/lr_synth_flow_var_setup.tcl
+++ b/hw/ip/aes/pre_syn/tcl/lr_synth_flow_var_setup.tcl
@@ -12,6 +12,7 @@
 set_flow_var top_module "aes" "top module"
 set_flow_var out_dir "syn_out" "Output directory for synthesis"
 set_flow_var pre_map_out "./${lr_synth_out_dir}/generated/${lr_synth_top_module}.pre_map.v" "Pre-mapping netlist out"
+set_flow_var alma_out "./${lr_synth_out_dir}/generated/${lr_synth_top_module}.alma.v" "Alma netlist out for pre-silicon SCA verification"
 set_flow_var netlist_out "./${lr_synth_out_dir}/generated/${lr_synth_top_module}_netlist.v" "netlist out"
 set_flow_var config_file "${lr_synth_ip_name}_lr_synth_conf.tcl" "Synth config file"
 set_flow_var rpt_out "./${lr_synth_out_dir}/reports" "Report output directory"
diff --git a/hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl b/hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl
index da54dc9..dc6d1db 100644
--- a/hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl
+++ b/hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl
@@ -44,6 +44,21 @@
 
 yosys "write_verilog $lr_synth_pre_map_out"
 
+# Remove keep_hierarchy constraints before writing out the netlist for Alma as it doesn't like
+# these constraints.
+yosys "setattr -mod -set keep_hierarchy 0 *prim_xilinx_buf*"
+yosys "setattr -mod -set keep_hierarchy 0 *aes_*_fsm_p*"
+yosys "setattr -mod -set keep_hierarchy 0 *aes_*_fsm_n*"
+yosys "setattr -mod -set keep_hierarchy 0 *aes_sel_buf_chk*"
+
+yosys "write_verilog $lr_synth_alma_out"
+
+# Re-add keep_hierarchy constraints for further synthesis steps.
+yosys "setattr -mod -set keep_hierarchy 1 *prim_xilinx_buf*"
+yosys "setattr -mod -set keep_hierarchy 1 *aes_*_fsm_p*"
+yosys "setattr -mod -set keep_hierarchy 1 *aes_*_fsm_n*"
+yosys "setattr -mod -set keep_hierarchy 1 *aes_sel_buf_chk*"
+
 yosys "dfflibmap -liberty $lr_synth_cell_library_path"
 yosys "opt"