diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core
index e73b4a1..9e25354 100644
--- a/hw/top_earlgrey/ip/ast/ast.core
+++ b/hw/top_earlgrey/ip/ast/ast.core
@@ -9,7 +9,10 @@
     depend:
       - lowrisc:ip:tlul
     files:
+      - rtl/lc_ctrl_pkg.sv
       - rtl/ast_reg_pkg.sv
+      - rtl/ast_pkg.sv
+      - rtl/ana_pkg.sv
       - rtl/ast.sv
       - rtl/adc.sv
       - rtl/aon_clk.sv
@@ -20,15 +23,14 @@
       - rtl/gen_pok.sv
       - rtl/io_clk.sv
       - rtl/io_osc.sv
-      - rtl/main_rglt.sv
-      - rtl/pdm.sv
+      - rtl/rglts_pdm_3p3v.sv
       - rtl/rng.sv
       - rtl/rng_osc.sv
       - rtl/sys_clk.sv
       - rtl/sys_osc.sv
       - rtl/usb_clk.sv
       - rtl/usb_osc.sv
-
+      
     file_type: systemVerilogSource
 
 
@@ -55,3 +57,4 @@
       vcs:
         vcs_options: [-timescale=1ns/1ps]
     toplevel: ast
+  
diff --git a/hw/top_earlgrey/ip/ast/data/ast.hjson b/hw/top_earlgrey/ip/ast/data/ast.hjson
index 414bb88..10f51f7 100644
--- a/hw/top_earlgrey/ip/ast/data/ast.hjson
+++ b/hw/top_earlgrey/ip/ast/data/ast.hjson
@@ -1,6 +1,10 @@
 // Copyright lowRISC contributors.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
+//#############################################################################
+// *Name: ast
+// *Module Description: Analog Sensors Top Registers
+//#############################################################################
 { name: "ast",
   clock_primary: "clk_i",
   bus_device: "tlul",
@@ -10,7 +14,7 @@
     { name: "RWTYPE0",
       desc: "RW type with one field",
       swaccess: "rw",
-      hwaccess: "hro",
+      hwaccess: "hrw",
       fields: [
         {
           bits: "31:0",
diff --git a/hw/top_earlgrey/ip/ast/doc/ast_regs.html b/hw/top_earlgrey/ip/ast/doc/ast_regs.html
new file mode 100644
index 0000000..9a170c9
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/doc/ast_regs.html
@@ -0,0 +1,35 @@
+<table class="regdef" id="Reg_rwtype0">
+<tr><th class="regdef" colspan=5><div>ast.RWTYPE0 @ + 0x0</div><div>RW type with one field</div><div>Reset default = 0xbc614e, mask 0xffffffff</div></th></tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>RWTYPE0...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...RWTYPE0</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xbc614e</td><td class="regfn">RWTYPE0</td><td class="regde">field description
+</td></tr>
+</table>
+<br><br>
+<table class="regdef" id="Reg_rwtype1">
+<tr><th class="regdef" colspan=5><div>ast.RWTYPE1 @ + 0x4</div><div>RW type
+with long
+description
+and multiple fields</div><div>Reset default = 0x6411, mask 0xff13</div></th></tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="unused" colspan=16>&nbsp;</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=8>FIELD15_8</td>
+<td class="unused" colspan=3>&nbsp;</td>
+<td class="fname" colspan=1 style="font-size:50.0%">FIELD4</td>
+<td class="unused" colspan=2>&nbsp;</td>
+<td class="fname" colspan=1 style="font-size:50.0%">FIELD1</td>
+<td class="fname" colspan=1 style="font-size:50.0%">FIELD0</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">0</td><td class="regperm">rw</td><td class="regrv">0x1</td><td class="regfn">FIELD0</td><td class="regde">field 0
+</td></tr>
+<tr><td class="regbits">1</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">FIELD1</td><td class="regde">field 1
+</td></tr>
+<tr><td class="regbits">3:2</td><td></td><td></td><td></td><td>Reserved</td></tr><tr><td class="regbits">4</td><td class="regperm">rw</td><td class="regrv">0x1</td><td class="regfn">FIELD4</td><td class="regde">field 4
+</td></tr>
+<tr><td class="regbits">7:5</td><td></td><td></td><td></td><td>Reserved</td></tr><tr><td class="regbits">15:8</td><td class="regperm">rw</td><td class="regrv">0x64</td><td class="regfn">FIELD15_8</td><td class="regde">field [15:8]
+</td></tr>
+</table>
+<br><br>
+
diff --git a/hw/top_earlgrey/ip/ast/rtl/adc.sv b/hw/top_earlgrey/ip/ast/rtl/adc.sv
index 9ffbc80..0b089c4 100644
--- a/hw/top_earlgrey/ip/ast/rtl/adc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/adc.sv
@@ -2,68 +2,103 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: adc
 // *Module Description:  Analog/Digital Converter
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
-module adc #(
-   parameter int AdcDataWidth = 10,
-   parameter int AdcChannels  = 2,
-   parameter int AdcCnvtClks  = 44
+module adc
+  import ana_pkg::*;  // For nettype real awire;
+#(
+  parameter int AdcCnvtClks  = 22,          //JL TODO: Update to actual convertion clock
+  parameter int AdcDataWidth = 10,
+  parameter int AdcChannels  = 2
 ) (
-   input [AdcChannels-1:0] adc_ai,         // One signal per channel
-   input [AdcChannels-1:0] adc_chnsel_i,   // Onehot value only for selrction
-   input adc_pd_i,
-   input clk_adc_i,
-   input rst_adc_ni,
-   output logic [AdcDataWidth-1:0] adc_d_o,
-   output logic adc_d_val_o
+`ifndef VERILATOR
+`ifndef SYNTHESIS
+  input awire adc_a0_ai,                    // ADC A0 Analog Input
+  input awire adc_a1_ai,                    // ADC A1 Analog Input
+`else
+  input wire adc_a0_ai,                     // ADC A0 Analog Input
+  input wire adc_a1_ai,                     // ADC A1 Analog Input
+`endif
+`else
+  input wire adc_a0_ai,                     // ADC A0 Analog Input
+  input wire adc_a1_ai,                     // ADC A1 Analog Input
+`endif
+  input [AdcChannels-1:0] adc_chnsel_i,     // Onehot value only for selrction
+  input adc_pd_i,                           // ADC Power Down
+  input clk_adc_i,                          // ADC Clock (aon_clk - 200KHz)
+  input rst_adc_ni,                         // ADC Reset active low
+  output logic [AdcDataWidth-1:0] adc_d_o,  // ADC 10-bit Data Output
+  output logic adc_d_val_o                  // ADC Data Valid Output
 );
-
+ 
 // Behavioral Model
+integer adc_d_ch0, adc_d_ch1;
+
+`ifndef VERILATOR
+`ifndef SYNTHESIS
+awire vref = 2.3;
+awire adc_vi0, adc_vi1;
+assign adc_vi0 = adc_a0_ai;
+assign adc_vi1 = adc_a1_ai;
+assign adc_d_ch0 = $rtoi( (adc_vi0/vref) * $itor(10'h3ff) );
+assign adc_d_ch1 = $rtoi( (adc_vi1/vref) * $itor(10'h3ff) );
+`else
+assign adc_d_ch0 = 'h31;    // 0.111V
+assign adc_d_ch1 = 'h21f;   // 1.222V
+`endif
+`else
+// Hook for testing for VERILATOR
+assign adc_d_ch0 = 'h31;    // 0.111V
+assign adc_d_ch1 = 'h21f;   // 1.222V
+`endif
+
+logic adc_en;
+
+always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin
+  if ( !rst_adc_ni ) adc_en <= 1'b0;
+  else               adc_en <= ~adc_pd_i;
+end
 
 logic [8-1:0] ConvertCount;
-logic [8-1:0] cnv_cnt;
-logic [AdcChannels-1:0] cnv_chnsel;
-logic chn_selected;
-logic rst_pd_adc_n;
-// 2 ahalog channels as digital for testing
-logic [AdcDataWidth-1:0] adc_a_chn0;
-logic [AdcDataWidth-1:0] adc_a_chn1;
+assign ConvertCount = AdcCnvtClks[8-1:0];
 
-assign ConvertCount = AdcCnvtClks[8-1:0];  // 44
-assign adc_a_chn0 = {AdcDataWidth{1'b0}};  // All '0'
-assign adc_a_chn1 = {AdcDataWidth{1'b1}};  // All '1'
-
+logic init_convert, chn_selected, chn_selected_d;
 assign chn_selected = |(adc_chnsel_i[AdcChannels-1:0]);
-assign rst_pd_adc_n = rst_adc_ni && ~adc_pd_i;
 
-always_ff @( posedge clk_adc_i, negedge rst_pd_adc_n ) begin
-   if (!rst_pd_adc_n ) begin
-      cnv_cnt     <= 8'h00;
-      cnv_chnsel  <= {AdcChannels{1'b0}};
-      adc_d_o     <= {AdcDataWidth{1'b0}};
-      adc_d_val_o <= 1'b0;
-   end
-   else if ( !chn_selected ) begin
-      cnv_cnt     <= 8'h00;
-      cnv_chnsel  <= {AdcChannels{1'b0}};
-      adc_d_val_o <= 1'b0;
-   end
-   else if ( cnv_cnt != ConvertCount ) begin
-      cnv_chnsel  <= adc_chnsel_i[AdcChannels-1:0];
-      cnv_cnt     <= cnv_cnt + 1'b1;
-      adc_d_val_o <= 1'b0;
-   end
-   else begin
-      adc_d_o     <= (cnv_chnsel == 2'b00) ? adc_d_o :
-                     (cnv_chnsel == 2'b01) ? adc_a_chn0 :
-                     (cnv_chnsel == 2'b10) ? adc_a_chn1 : {AdcDataWidth{1'bx}};
-      adc_d_val_o <= 1'b1;
-   end
+always_ff @( posedge clk_adc_i ) begin
+  chn_selected_d <= chn_selected;
+end
+
+assign init_convert = chn_selected && ~chn_selected_d;
+
+logic [8-1:0] cnv_cyc;
+logic adc_convert;
+
+always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin
+  if (!rst_adc_ni ) begin
+    cnv_cyc     <= 8'h00;
+    adc_d_val_o <= 1'b0;
+    adc_convert <= 1'b0;
+    adc_d_o     <= {AdcDataWidth{1'b0}};
+  end else if ( !(adc_en && chn_selected) ) begin
+    cnv_cyc     <= 8'h00;
+    adc_d_val_o <= 1'b0;
+    adc_convert <= 1'b0;
+  end else if ( init_convert ) begin
+    cnv_cyc     <= ConvertCount;
+    adc_convert <= 1'b1;
+  end else if ( adc_convert && (cnv_cyc > 8'h00) ) begin
+    cnv_cyc     <= cnv_cyc - 1'b1;
+  end else if ( adc_convert ) begin
+    adc_d_val_o <= 1'b1;
+    adc_d_o     <= (adc_chnsel_i == 2'b00) ? adc_d_o :
+                   (adc_chnsel_i == 2'b01) ? adc_d_ch0[10-1:0] :
+                   (adc_chnsel_i == 2'b10) ? adc_d_ch1[10-1:0] :
+                                             {AdcDataWidth{1'bx}};
+  end
 end
 
 
diff --git a/hw/top_earlgrey/ip/ast/rtl/ana_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ana_pkg.sv
new file mode 100644
index 0000000..4ac5633
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/rtl/ana_pkg.sv
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: ana_pkg
+// *Module Description: Analog (nettype) Package
+//############################################################################
+
+`ifdef __ANA_PKG
+`else
+`define __ANA_PKG
+package ana_pkg;
+
+// NETTYPE Definition
+`ifndef VERILATOR
+`ifndef SYNTHESIS
+  nettype real awire;
+`endif
+`endif
+endpackage  // of ana_pkg
+`endif  // of __ANA_PKG
diff --git a/hw/top_earlgrey/ip/ast/rtl/aon_clk.sv b/hw/top_earlgrey/ip/ast/rtl/aon_clk.sv
index acbd045..bd30e4a 100644
--- a/hw/top_earlgrey/ip/ast/rtl/aon_clk.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/aon_clk.sv
@@ -2,46 +2,57 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: aon_clk
 // *Module Description: Always ON Clock
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module aon_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time AON_EN_RDLY = 10us,
-   parameter time AON_EN_FDLY = 100ns
+  parameter time AON_EN_RDLY = 5us
 // synopsys translate_on
+`endif
 ) (
-   input rst_ni,                   // Reset
-   output logic clk_src_aon_o,     // AON Source Clock
-   output logic clk_src_aon_val_o  // AON Source Clock Valid
+  input vcaon_pok_i,              // 1.1v VCAON POK
+  output logic clk_src_aon_o,     // AON Source Clock
+  output logic clk_src_aon_val_o  // AON Source Clock Valid
 );
 
-logic clk, clk_en, aon_en;
+logic clk, aon_clk_en, aon_clk_val, aon_en, rst_n;
+assign aon_en = 1'b1;  // AON Clock is always enabled!
 
 // Behavioral Model
+assign rst_n = vcaon_pok_i;
+
 aon_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .AON_EN_RDLY ( AON_EN_RDLY ),
-/*P*/ .AON_EN_FDLY ( AON_EN_FDLY )
+/*P*/ .AON_EN_RDLY ( AON_EN_RDLY )
 // synopsys translate_on
+`endif
 ) i_aon_osc (
-/*I*/ .aon_en_i ( 1'b1 ),  // AON Clock is always enabled!
-/*O*/ .aon_clk_o ( clk ),
-/*O*/ .aon_clk_en_o ( aon_en )
+/*I*/ .vcaon_pok_i ( vcaon_pok_i ),
+/*I*/ .aon_en_i ( aon_en ),
+/*O*/ .aon_clk_o ( clk )
 );
 
-always_ff @( posedge clk, negedge rst_ni ) begin
-   if ( !rst_ni )  clk_en <= 1'b0;
-   else            clk_en <= aon_en;
-end
 
 // Clock & Valid
-assign clk_src_aon_o = clk_en ? ~clk : 1'b0;
-assign clk_src_aon_val_o = clk_en;
+assign clk_src_aon_o = clk;
+
+wire rst_val_n = rst_n;
+
+// 2-stage deassertion
+always_ff @( posedge clk, negedge rst_val_n ) begin
+  if ( !rst_val_n )  begin
+    aon_clk_val       <= 1'b0;
+    clk_src_aon_val_o <= 1'b0;
+  end else begin
+    aon_clk_val       <= 1'b1;
+    clk_src_aon_val_o <= aon_clk_val;
+  end
+end
 
 
 endmodule  // of aon_clk
diff --git a/hw/top_earlgrey/ip/ast/rtl/aon_osc.sv b/hw/top_earlgrey/ip/ast/rtl/aon_osc.sv
index cef8bbc..ac785f6 100644
--- a/hw/top_earlgrey/ip/ast/rtl/aon_osc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/aon_osc.sv
@@ -2,56 +2,54 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: aon_osc
 // *Module Description: AON Clock Oscilator
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module aon_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time AON_EN_RDLY = 10us,
-   parameter time AON_EN_FDLY = 100ns
+  parameter time AON_EN_RDLY = 5us
 // synopsys translate_on
+`endif
 ) (
-   input aon_en_i,              // AON Source Clock Enable
-   output logic aon_clk_o,      // AON Clock Output
-   output logic aon_clk_en_o    // AON Clock Enable Output
+  input vcaon_pok_i,       // VCAON POK @1.1V
+  input aon_en_i,          // AON Source Clock Enable
+  output logic aon_clk_o   // AON Clock Output
 );
 
+`ifndef VERILATOR
 // synopsys translate_off
-
-// localparam real AON_CLK_PERIOD = 5000; // 5000ns (200Khz)
-// TBD
-// sped up to 200ns by default.
-// There should be a DV hook here so that the test can choose the actual frequency
-   localparam real AON_CLK_PERIOD = 200;
-
-logic init_start, clk;
+localparam time AON_CLK_PERIOD = 5000ns; // 5000ns (200Khz)
+logic clk, en_osc, en_osc_re, en_osc_fe;
 
 initial begin
-   clk = 1'b0;
-   $display("\nAON Clock Period: %0dns", AON_CLK_PERIOD);
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
+  clk = 1'b0;
+  $display("\nAON Clock Period: %0dns", AON_CLK_PERIOD);
 end
 
+always @( * ) begin
+  if ( !vcaon_pok_i )                 en_osc_re = 1'b0;
+  else if ( aon_en_i && vcaon_pok_i ) en_osc_re = #(AON_EN_RDLY) 1'b1;
+  else                                en_osc_re = 1'b0;
+end
+
+// Syncronize en_osc_fe to clk FE for glitch free disable
+always_ff @( negedge clk or negedge vcaon_pok_i ) begin
+  if ( !vcaon_pok_i ) en_osc_fe <= 1'b0;
+  else                en_osc_fe <= en_osc_re;
+end
+
+assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
+
 always begin
-   #(AON_CLK_PERIOD/2) clk = ~clk;
+  #(AON_CLK_PERIOD/2) clk = ~clk && en_osc;
 end
 
 assign aon_clk_o = clk;
-
-always_ff @( init_start, posedge aon_en_i, negedge aon_en_i ) begin
-    if ( init_start )
-       aon_clk_en_o <= 1'b0;
-    else if ( !init_start && aon_en_i )
-       aon_clk_en_o <= #(AON_EN_RDLY) aon_en_i;
-    else if ( !init_start && !aon_en_i )
-       aon_clk_en_o <= #(AON_EN_FDLY) aon_en_i;
-end
-
 // synopsys translate_on
+`endif
+
 
 endmodule  // of aon_osc
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index 3ef2150..bbddd0d 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -2,203 +2,201 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: ast
 // *Module Description: Analog Sensors Top
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
-module ast #(
-   parameter int EntropyStreams  = 4,
-   parameter int EntropyInWidth  = 1,
-   parameter int AdcChannels     = 2,
-   parameter int AdcDataWidth    = 10,
-   parameter int Ast2PadOutWidth = 16,         // TBD
-   parameter int Pad2AstInWidth  = 16,         // TBD
-   parameter int JitCalibWidth   = 16,         // TBD
-   parameter int JitSRateWidth   = 16,         // TBD
-   parameter int UsbCalibWidth   = 16          // TBD
+module ast
+  import ana_pkg::*;
+  import lc_ctrl_pkg::*;
+#(
+  parameter int EntropyStreams  = 4,
+  parameter int AdcChannels     = 2,
+  parameter int AdcDataWidth    = 10,
+  parameter int Ast2PadOutWidth = 16,         // TBD
+  parameter int Pad2AstInWidth  = 16,         // TBD
+  parameter int UsbCalibWidth   = 16          // TBD
 ) (
-   // Power and IO pin connections
-   input main_iso_en_i,                        // Isolation enable for main core power (VCMAIN).
+ 
+  // tlul if
+  input  tlul_pkg::tl_h2d_t tl_i,             // TLUL H2D 
+  output tlul_pkg::tl_d2h_t tl_o,             // TLUL D2H
 
-   // tlul if
-   input  tlul_pkg::tl_h2d_t tl_i,             // TLUL H2D
-   output tlul_pkg::tl_d2h_t tl_o,             // TLUL D2H
+  // LC TX if
+  input lc_ctrl_pkg::lc_tx_t lc_root_clk_byp_i,  // External clock mux override for OTP bootstrap
+  input lc_ctrl_pkg::lc_tx_t lc_dft_en_i,     // DFT enable 
 
-   // clocks / rests
-   input clk_ast_adc_i,                        // Buffered AST ADC Clock
-   input rst_ast_adc_ni,                       // Buffered AST ADC Reset
-   input clk_ast_alert_i,                      // Buffered AST Alert Clock
-   input rst_ast_alert_ni,                     // Buffered AST Alert Reset
-   input clk_ast_es_i,                         // Buffered AST Entropy Source Clock
-   input rst_ast_es_ni,                        // Buffered AST Entropy Source Reset
-   input clk_ast_rng_i,                        // Buffered AST RNG Clock
-   input rst_ast_rng_ni,                       // Buffered AST RNG Reset
-   input clk_ast_tlul_i,                       // Buffered AST TLUL Clock
-   input rst_ast_tlul_ni,                      // Buffered AST TLUL Reset
-   input clk_ast_usb_i,                        // Buffered AST USB Clock
-   input rst_ast_usb_ni,                       // Buffered AST USB Reset
-   input clk_ast_ext_i,                        // Buffered AST External Clock
-   input por_ni,                               // Power ON Reset
+  // clocks / rests
+  input clk_ast_adc_i,                        // Buffered AST ADC Clock
+  input rst_ast_adc_ni,                       // Buffered AST ADC Reset
+  input clk_ast_alert_i,                      // Buffered AST Alert Clock
+  input rst_ast_alert_ni,                     // Buffered AST Alert Reset
+  input clk_ast_es_i,                         // Buffered AST Entropy Source Clock
+  input rst_ast_es_ni,                        // Buffered AST Entropy Source Reset
+  input clk_ast_rng_i,                        // Buffered AST RNG Clock
+  input rst_ast_rng_ni,                       // Buffered AST RNG Reset
+  input clk_ast_tlul_i,                       // Buffered AST TLUL Clock
+  input rst_ast_tlul_ni,                      // Buffered AST TLUL Reset
+  input clk_ast_usb_i,                        // Buffered AST USB Clock
+  input rst_ast_usb_ni,                       // Buffered AST USB Reset
+  input clk_ast_ext_i,                        // Buffered AST External Clock
+  input por_ni,                               // Power ON Reset
 
-   // power OK control
-   // In non-power aware DV environment, the <>_supp_i is for debug only!
-   // POK signal follow this input.
-   // In a power aware environment this signal should be connected to constant '1'
-   input vcc_supp_i,                           // VCC Supply Test
-   input vcaon_supp_i,                         // VCAON Supply Test
-   input vcmain_supp_i,                        // VCMAIN Supply Test
-   input vioa_supp_i,                          // VIOA Rail Supply Test
-   input viob_supp_i,                          // VIOB Rail Supply Test
-   output logic vcaon_pok_o,                   // VCAON Power OK
-   output logic vcmain_pok_o,                  // VCMAIN Power OK
-   output logic vioa_pok_o,                    // VIOA Rail Power OK
-   output logic viob_pok_o,                    // VIOB Rail Power OK
+  // power OK control 
+  // In non-power aware DV environment, the <>_supp_i is for debug only! 
+  // POK signal follow this input.
+  // In a power aware environment this signal should be connected to constant '1'
+  input vcc_supp_i,                           // VCC Supply Test for OS FPGA 
+  input vcaon_supp_i,                         // VCAON Supply Test for OS FPGA
+  input vcmain_supp_i,                        // VCMAIN Supply Test for OS FPGA
+  input vioa_supp_i,                          // VIOA Rail Supply Test for OS FPGA
+  input viob_supp_i,                          // VIOB Rail Supply Test for OS FPGA
+  output logic vcaon_pok_o,                   // VCAON Power OK
+  output logic vcmain_pok_o,                  // VCMAIN Power OK
+  output logic vioa_pok_o,                    // VIOA Rail Power OK
+  output logic viob_pok_o,                    // VIOB Rail Power OK
+ 
+  // Power and IO pin connections
+  input main_pd_ni,                           // MAIN Regulator Power Down
+  input main_iso_en_i,                        // Isolation enable for main core power (VCMAIN).
 
-   // main regulator
-   input main_pd_ni,                           // MAIN Regulator Power Down
+  // power down monitor logic - flash/otp related
+  output logic flash_power_down_h_o,          // Flash Power Down
+  output logic flash_power_ready_h_o,         // Flash Power Ready
+  input [1:0] otp_power_seq_i,                // MMR0,24 in (VDD)
+  output logic [1:0] otp_power_seq_h_o,       // MMR0,24 masked by PDM, out (VCC)
 
-   // power down monitor logic - flash related
-   output logic flash_power_down_h_o,          // Flash Power Down
-   output logic flash_power_ready_h_o,         // Flash Power Ready
+  // system source clock
+  input clk_src_sys_en_i,                     // SYS Source Clock Enable
+  input clk_src_sys_jen_i,                    // SYS Source Clock Jitter Enable
+  output logic clk_src_sys_o,                 // SYS Source Clock
+  output logic clk_src_sys_val_o,             // SYS Source Clock Valid
 
-   // system source clock
-   input clk_src_sys_en_i,                     // SYS Source Clock Enable
-   input clk_src_sys_jen_i,                    // SYS Source Clock Jitter Enable
-   output logic clk_src_sys_o,                 // SYS Source Clock
-   output logic clk_src_sys_val_o,             // SYS Source Clock Valid
+  // aon source clock
+  output logic clk_src_aon_o,                 // AON Source Clock
+  output logic clk_src_aon_val_o,             // AON Source Clock Valid
 
-   // aon source clock
-   output logic clk_src_aon_o,                 // AON Source Clock
-   output logic clk_src_aon_val_o,             // AON Source Clock Valid
+  // io source clock
+  input clk_src_io_en_i,                      // IO Source Clock Enable
+  output logic clk_src_io_o,                  // IO Source Clock
+  output logic clk_src_io_val_o,              // IO Source Clock Valid
 
-   // io source clock
-   input clk_src_io_en_i,                      // IO Source Clock Enable
-   output logic clk_src_io_o,                  // IO Source Clock
-   output logic clk_src_io_val_o,              // IO Source Clock Valid
+  // usb source clock
+  input usb_ref_pulse_i,                      // USB Reference Pulse
+  input usb_ref_val_i,                        // USB Reference Valid 
+  input clk_src_usb_en_i,                     // USB Source Clock Enable
+  output logic clk_src_usb_o,                 // USB Source Clock
+  output logic clk_src_usb_val_o,             // USB Source Clock Valid
+  output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o,  // USB IO Pull-up Calibration Setting 
 
-   // usb source clock
-   input usb_ref_pulse_i,                      // USB Reference Pulse
-   input usb_ref_val_i,                        // USB Reference Valid
-   input clk_src_usb_en_i,                     // USB Source Clock Enable
-   output logic clk_src_usb_o,                 // USB Source Clock
-   output logic clk_src_usb_val_o,             // USB Source Clock Valid
-   output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o,  // USB IO Pull-up Calibration Setting
+  // adc interface
+  input adc_pd_i,                             // ADC Power Down
+`ifndef VERILATOR
+`ifndef SYNTHESIS
+  input awire adc_a0_ai,                      // ADC A0 Analog Input
+  input awire adc_a1_ai,                      // ADC A1 Analog Input
+`else
+  input wire adc_a0_ai,                       // ADC A0 Analog Input
+  input wire adc_a1_ai,                       // ADC A1 Analog Input
+`endif
+`else
+  input wire adc_a0_ai,                       // ADC A0 Analog Input
+  input wire adc_a1_ai,                       // ADC A1 Analog Input
+`endif
+  input [AdcChannels-1:0] adc_chnsel_i,       // ADC Channel Select 
+  output [AdcDataWidth-1:0] adc_d_o,          // ADC Digital (per channel)
+  output adc_d_val_o,                         // ADC Digital Valid
 
-   // adc interface
-   input adc_pd_i,                             // ADC Power Down
-   input [AdcChannels-1:0] adc_ai,             // ADC Analog (per channel)
-   input [AdcChannels-1:0] adc_chnsel_i,       // ADC Channel Select
-   output [AdcDataWidth-1:0] adc_d_o,          // ADC Digital (per channel)
-   output adc_d_val_o,                         // ADC Digital Valid
+  // entropy source interface
+  input rng_en_i,                             // RNG Enable
+  output logic rng_val_o,                     // RNG Valid
+  output logic [EntropyStreams-1:0] rng_b_o,  // RNG Bit(s)
 
-   // entropy source interface
-   input rng_en_i,                             // RNG Enable
-   output logic rng_ok_o,                      // RNG OK
-   output logic [EntropyStreams-1:0] rng_b_o,  // RNG Bit(s)
+  // entropy distribution interface
+  input entropy_ack_i,                        // Entropy Acknowlage
+  input entropy_i,                            // Entropy
+  output logic entropy_req_o,                 // Entropy Request
 
-   // entropy distribution interface
-   input entropy_ack_i,                        // Entropy Acknowlage
-   input [EntropyInWidth-1:0] entropy_i,       // Entropy
-   output logic entropy_req_o,                 // Entropy Request
+  // alerts
+  input as_alert_trig_i,                      // Active Shield Alert Trigger
+  input as_alert_ack_i,                       // Active Shield Alert Acknowlage
+  output logic as_alert_po,                   // Active Shield Alert Positive
+  output logic as_alert_no,                   // Active Shield Alert Negative
 
-   // alerts
-   input as_alert_trig_i,                      // Active Shield Alert Trigger
-   input as_alert_ack_i,                       // Active Shield Alert Acknowlage
-   output logic as_alert_po,                   // Active Shield Alert Positive
-   output logic as_alert_no,                   // Active Shield Alert Negative
+  input cg_alert_trig_i,                      // CG Alert Trigger
+  input cg_alert_ack_i,                       // CG Alert Acknowlage
+  output logic cg_alert_po,                   // CG Alert Positive
+  output logic cg_alert_no,                   // CG Alert Negative
 
-   input cg_alert_trig_i,                      // CG Alert Trigger
-   input cg_alert_ack_i,                       // CG Alert Acknowlage
-   output logic cg_alert_po,                   // CG Alert Positive
-   output logic cg_alert_no,                   // CG Alert Negative
+  input gd_alert_trig_i,                      // GD Alert Trigger
+  input gd_alert_ack_i,                       // GD Alert Acknowlage
+  output logic gd_alert_po,                   // GD Alert Positive
+  output logic gd_alert_no,                   // GD Alert Negative
 
-   input gd_alert_trig_i,                      // GD Alert Trigger
-   input gd_alert_ack_i,                       // GD Alert Acknowlage
-   output logic gd_alert_po,                   // GD Alert Positive
-   output logic gd_alert_no,                   // GD Alert Negative
+  input ts_alert_hi_trig_i,                   // TS High Alert Trigger
+  input ts_alert_hi_ack_i,                    // TS High Alert Acknowlage
+  output logic ts_alert_hi_po,                // TS High Alert Positive
+  output logic ts_alert_hi_no,                // TS High Alert Negative
 
-   input ts_alert_hi_trig_i,                   // TS High Alert Trigger
-   input ts_alert_hi_ack_i,                    // TS High Alert Acknowlage
-   output logic ts_alert_hi_po,                // TS High Alert Positive
-   output logic ts_alert_hi_no,                // TS High Alert Negative
+  input ts_alert_lo_trig_i,                   // TS Low Alert Trigger
+  input ts_alert_lo_ack_i,                    // TS Low Alert Acknowlage
+  output logic ts_alert_lo_po,                // TS Low Alert Positive
+  output logic ts_alert_lo_no,                // TS Low Alert Negative
 
-   input ts_alert_lo_trig_i,                   // TS Low Alert Trigger
-   input ts_alert_lo_ack_i,                    // TS Low Alert Acknowlage
-   output logic ts_alert_lo_po,                // TS Low Alert Positive
-   output logic ts_alert_lo_no,                // TS Low Alert Negative
+  input ls_alert_trig_i,                      // LS Alert Trigger
+  input ls_alert_ack_i,                       // LS Alert Acknowlage
+  output logic ls_alert_po,                   // LS Alert Positive
+  output logic ls_alert_no,                   // LS Alert Negative
 
-   input ls_alert_trig_i,                      // LS Alert Trigger
-   input ls_alert_ack_i,                       // LS Alert Acknowlage
-   output logic ls_alert_po,                   // LS Alert Positive
-   output logic ls_alert_no,                   // LS Alert Negative
+  input ot_alert_trig_i,                      // OT Alert Trigger
+  input ot_alert_ack_i,                       // OT Alert Acknowlage
+  output logic ot_alert_po,                   // OT Alert Positive
+  output logic ot_alert_no,                   // OT Alert Negative
+  
+  // pad mux related - DFT
+  input [Pad2AstInWidth-1:0] padmux2ast_i,    // IO_2_DFT Input Signals
+  output logic [Ast2PadOutWidth-1:0] ast2padmux_o,   // DFT_2_IO Output Signals
+  inout wire ast2pad_a_io,                    // TODO: If needed, add width param
 
-   input ot_alert_trig_i,                      // OT Alert Trigger
-   input ot_alert_ack_i,                       // OT Alert Acknowlage
-   output logic ot_alert_po,                   // OT Alert Positive
-   output logic ot_alert_no,                   // OT Alert Negative
-
-   // pad mux related - DFT
-   input [Pad2AstInWidth-1:0] padmux2ast_i,    // IO_2_DFT Input Signals
-   output logic [Ast2PadOutWidth-1:0] ast2padmux_o,   // DFT_2_IO Output Signals
-   inout wire ast2pad_a_io,                    // TODO: If needed, add width param
-
-   // Scan
-   input scan_mode_i,                          // Scan Mode
-   input scan_reset_ni                         // Scan Reset
+  // Scan
+  input scan_mode_i,                          // Scan Mode
+  input scan_reset_ni                         // Scan Reset
 );
 
+import ast_pkg::*;
 import ast_reg_pkg::*;
 
-// To HW
-/*O*/ ast_reg_pkg::ast_reg2hw_t reg2hw; // Write
-
-logic vcaon_pok, vcaon_pok_h;
+logic vcaon_pok, vcaon_pok_h; 
 
 
 
 /////////////////////////////////
 // Power OK
 /////////////////////////////////
-// Local signals for testing hook
-logic vcc_a;     assign vcc_a = 1'b1;
-logic vioa_a;    assign vioa_a = 1'b1;
-logic viob_a;    assign viob_a = 1'b1;
-logic vcaon_a;   assign vcaon_a = 1'b1;
-logic vcmain_a;  assign vcmain_a = 1'b1;
-
-logic vcc_pok_h, vcc_pok;
 
 // VCC POK
+logic vcc_pok_h, vcc_pok;
 gen_pok #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .POK_RDLY ( 3us ),
-/*P*/ .POK_FDLY ( 500ns )
+/*P*/ .POK_RDLY ( VCC_POK_RDLY ), 
+/*P*/ .POK_FDLY ( VCC_POK_FDLY ) 
 // synopsys translate_on
+`endif
 ) i_vcc_pok (
-/*I*/ .gen_supp_a ( vcc_a ),
-/*I*/ .gen_supp_i ( vcc_supp_i ),
-/*O*/ .gen_pok_o ( vcc_pok_h )
+/*O*/ .gen_pok_o ( vcc_pok_int )
 );
 
-assign vcc_pok = vcc_pok_h;  // "Level Shifter"
-
-logic vcmain_pok, vcmain_pok_h;
+assign vcc_pok = vcc_pok_int && vcc_supp_i;
+assign vcc_pok_h = vcc_pok;     // "Level Shifter"
 
 
 // VCAON POK
-gen_pok #(
-// synopsys translate_off
-/*P*/ .POK_RDLY ( 3us ),
-/*P*/ .POK_FDLY ( 500ns )
-// synopsys translate_on
-) i_vcaon_pok (
-/*I*/ .gen_supp_a ( vcaon_a ),
-/*I*/ .gen_supp_i ( vcaon_supp_i ),
-/*O*/ .gen_pok_o ( vcaon_pok )
-);
+logic vcmain_pok, vcmain_pok_h; 
+logic vcaon_pok_int, vcaon_pok_int_h;
+assign vcaon_pok   = vcaon_pok_int && vcaon_supp_i;
+assign vcaon_pok_h = vcaon_pok_int_h && vcaon_supp_i;
 
 // 'por_sync_n' reset deasetion synchronizer output
 logic por_syn_rst_n, por_sync0_n, por_sync_n;
@@ -206,100 +204,104 @@
 assign por_syn_rst_n = por_ni && vcc_pok && vcaon_pok;
 
 always_ff @( posedge clk_src_aon_o, negedge por_syn_rst_n ) begin
-   if ( !por_syn_rst_n ) begin
-      por_sync0_n <= 1'b0;
-      por_sync_n  <= 1'b0;
-   end
-   else begin
-      por_sync0_n <= 1'b1;
-      por_sync_n  <= por_sync0_n;
-   end
+  if ( !por_syn_rst_n ) begin
+    por_sync0_n <= 1'b0;
+    por_sync_n  <= 1'b0;
+  end
+  else begin
+    por_sync0_n <= 1'b1;
+    por_sync_n  <= por_sync0_n;
+  end
 end
 
 assign vcaon_pok_o = por_sync_n && vcc_pok && vcaon_pok;
 
 
 // VCMAIN POK
-
 // Power up/down with rise/fall delays.
-logic main_pwr_dly;
+logic vcmain_pok_int, main_pwr_dly_o;
 
-gen_pok #(
+gen_pok #( 
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .POK_RDLY ( 3us ),
-/*P*/ .POK_FDLY ( 500ns )
+/*P*/ .POK_RDLY ( VCMAIN_POK_RDLY ), 
+/*P*/ .POK_FDLY ( VCMAIN_POK_FDLY ) 
 // synopsys translate_on
+`endif
 ) i_vcmain_pok (
-/*I*/ .gen_supp_a ( vcmain_a && main_pwr_dly ),
-/*I*/ .gen_supp_i ( vcmain_supp_i ),
-/*O*/ .gen_pok_o ( vcmain_pok )
+/*O*/ .gen_pok_o ( vcmain_pok_int )
 );
 
-assign vcmain_pok_o = vcaon_pok_o && vcmain_pok;
+assign vcmain_pok = vcmain_pok_int && vcmain_supp_i && main_pwr_dly_o ;
+assign vcmain_pok_h = vcmain_pok;   // Level Shifter
+assign vcmain_pok_o = vcaon_pok_o && vcmain_pok; 
 
 
 // VIOA POK
 logic vioa_pok;
+logic vioa_pok_int;
 
-gen_pok #(
+gen_pok #( 
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .POK_RDLY ( 3us ),
-/*P*/ .POK_FDLY ( 500ns )
+/*P*/ .POK_RDLY ( VIOA_POK_RDLY ), 
+/*P*/ .POK_FDLY ( VIOA_POK_FDLY ) 
 // synopsys translate_on
+`endif
 ) i_vioa_pok (
-/*I*/ .gen_supp_a ( vioa_a ),
-/*I*/ .gen_supp_i ( vioa_supp_i ),
-/*O*/ .gen_pok_o ( vioa_pok )
+/*O*/ .gen_pok_o ( vioa_pok_int )
 );
 
+assign vioa_pok = vioa_pok_int && vioa_supp_i;
+
 assign vioa_pok_o = vcaon_pok && vioa_pok;
 
 
 // VIOB POK
 logic viob_pok;
+logic viob_pok_int;
 
-gen_pok #(
+gen_pok #( 
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .POK_RDLY ( 3us ),
-/*P*/ .POK_FDLY ( 500ns )
+/*P*/ .POK_RDLY ( VIOB_POK_RDLY ), 
+/*P*/ .POK_FDLY ( VIOB_POK_FDLY ) 
 // synopsys translate_on
+`endif
 ) i_viob_pok (
-/*I*/ .gen_supp_a ( viob_a ),
-/*I*/ .gen_supp_i ( viob_supp_i ),
-/*O*/ .gen_pok_o ( viob_pok )
+/*O*/ .gen_pok_o ( viob_pok_int )
 );
 
+assign viob_pok = viob_pok_int && viob_supp_i;
+
 assign viob_pok_o = vcaon_pok && viob_pok;
 
 
 /////////////////////////////////
-// Main Regulator
+// Regulators & PDM Logic
 /////////////////////////////////
 
-// Main Regulator (VCC)
-main_rglt #(
+// Regulators (VCC)
+// Analog & Digital are 3.3v
+rglts_pdm_3p3v #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .MRVCC_RDLY ( 5us ),
-/*P*/ .MRVCC_FDLY ( 100ns ),
-/*P*/ .MRPD_RDLY ( 50us ),
-/*P*/ .MRPD_FDLY ( 1us )
+/*P*/ .MRVCC_RDLY ( MPVCC_RDLY ),
+/*P*/ .MRVCC_FDLY ( MPVCC_FDLY ),
+/*P*/ .MRPD_RDLY ( MPPD_RDLY ),
+/*P*/ .MRPD_FDLY ( MPPD_FDLY )
 // synopsys translate_on
-) i_main_rglt (
-/*I*/ .vcc_pok_i ( vcc_pok ),
+`endif
+) i_rglts_pdm_3p3v (
+/*I*/ .vcc_pok_h_i ( vcc_pok_h ),
+/*I*/ .vcmain_pok_h_i ( vcmain_pok_h ),
+/*I*/ .clk_src_aon_i ( clk_src_aon_o ),
 /*I*/ .main_pd_ni ( main_pd_ni ),
-/*O*/ .main_pwr_dly ( main_pwr_dly )
-);
-
-
-/////////////////////////////////
-// PDM (Power Down Mode) Logic
-/////////////////////////////////
-
-// Power Down Mode (VCC)
-pdm i_pdm (
-/*I*/ .vcc_pok_i ( vcc_pok_h ),
-/*I*/ .vcmain_pok_i ( vcmain_pok ),
-/*I*/ .main_pd_ni ( main_pd_ni ),
+/*I*/ .otp_power_seq_i ( otp_power_seq_i[1:0] ),
+/*O*/ .main_pwr_dly_o ( main_pwr_dly_o ),
+/*O*/ .vcaon_pok_o ( vcaon_pok_int ),
+/*O*/ .vcaon_pok_h_o ( vcaon_pok_int_h ),
+/*O*/ .otp_power_seq_h_o ( otp_power_seq_h_o[1:0] ),
 /*O*/ .flash_power_down_h_o ( flash_power_down_h_o ),
 /*O*/ .flash_power_ready_h_o ( flash_power_ready_h_o )
 );
@@ -311,31 +313,30 @@
 
 // System Clock (Always ON)
 sys_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .SYS_EN_RDLY ( 10us ),
-/*P*/ .SYS_EN_FDLY ( 100ns ),
-/*P*/ .SYS_JEN_RDLY ( 80ns ),
-/*P*/ .SYS_JEN_FDLY ( 80ns )
+/*P*/ .SYS_EN_RDLY ( SYS_EN_RDLY )
 // synopsys translate_on
+`endif
 ) i_sys_clk (
+/*I*/ .vcmain_pok_i ( vcmain_pok ),
 /*I*/ .clk_src_sys_en_i ( clk_src_sys_en_i ),
 /*I*/ .clk_src_sys_jen_i ( clk_src_sys_jen_i ),
-/*I*/ .rst_ni ( vcmain_pok_o ),
 /*O*/ .clk_src_sys_o ( clk_src_sys_o ),
 /*O*/ .clk_src_sys_val_o ( clk_src_sys_val_o )
 );
 
 // USB Clock (Always ON)
 usb_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .USB_EN_RDLY ( 10us ),
-/*P*/ .USB_EN_FDLY ( 100ns ),
-/*P*/ .USB_VAL_RDLY ( 80ns ),  // Reduced for simulation from 50ms
-/*P*/ .USB_VAL_FDLY ( 80ns ),
+/*P*/ .USB_EN_RDLY ( USB_EN_RDLY ),
+/*P*/ .USB_VAL_RDLY ( USB_VAL_RDLY ),
+/*P*/ .USB_VAL_FDLY ( USB_VAL_FDLY )
 // synopsys translate_on
-/*P*/ .UsbCalibWidth ( UsbCalibWidth )
+`endif
 ) i_usb_clk (
-/*I*/ .rst_ni ( vcmain_pok_o ),
+/*I*/ .vcmain_pok_i ( vcmain_pok ),
 /*I*/ .clk_src_usb_en_i ( clk_src_usb_en_i ),
 /*I*/ .usb_ref_pulse_i ( usb_ref_pulse_i ),
 /*I*/ .usb_ref_val_i ( usb_ref_val_i ),
@@ -345,27 +346,29 @@
 
 // AON Clock (Always ON)
 aon_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .AON_EN_RDLY ( 10us ),
-/*P*/ .AON_EN_FDLY ( 100ns )
+/*P*/ .AON_EN_RDLY ( AON_EN_RDLY )
 // synopsys translate_on
+`endif
 ) i_aon_clk (
-/*I*/ .rst_ni ( vcaon_pok ),
+/*I*/ .vcaon_pok_i ( vcaon_pok ),
 /*O*/ .clk_src_aon_o ( clk_src_aon_o ),
 /*O*/ .clk_src_aon_val_o ( clk_src_aon_val_o )
 );
 
 // IO Clock (Always ON)
 io_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .IO_EN_RDLY ( 10us ),
-/*P*/ .IO_EN_FDLY ( 100ns )
+/*P*/ .IO_EN_RDLY ( 5us )
 // synopsys translate_on
+`endif
 ) i_io_clk (
-/*O*/ .clk_src_io_o ( clk_src_io_o ),
-/*O*/ .clk_src_io_val_o ( clk_src_io_val_o ),
+/*I*/ .vcmain_pok_i ( vcmain_pok ),
 /*I*/ .clk_src_io_en_i ( clk_src_io_en_i ),
-/*I*/ .rst_ni ( vcmain_pok_o )
+/*O*/ .clk_src_io_o ( clk_src_io_o ),
+/*O*/ .clk_src_io_val_o ( clk_src_io_val_o )
 );
 
 
@@ -374,12 +377,13 @@
 /////////////////////////////////
 
 // ADC (Always ON)
-adc #(
+adc #( 
+/*P*/ .AdcCnvtClks ( AdcCnvtClks ),
 /*P*/ .AdcDataWidth ( AdcDataWidth ),
-/*P*/ .AdcChannels ( AdcChannels ),
-/*P*/ .AdcCnvtClks ( 44 )
+/*P*/ .AdcChannels ( AdcChannels )
 ) i_adc (
-/*I*/ .adc_ai ( adc_ai[AdcChannels-1:0] ),
+/*I*/ .adc_a0_ai ( adc_a0_ai ),
+/*I*/ .adc_a1_ai ( adc_a1_ai ),
 /*I*/ .adc_chnsel_i ( adc_chnsel_i[AdcChannels-1:0] ),
 /*I*/ .adc_pd_i ( adc_pd_i ),
 /*I*/ .clk_adc_i ( clk_ast_adc_i ),
@@ -395,19 +399,18 @@
 
 // Entropy (Always ON)
 localparam int EntropyRateWidth = 4;
-logic [EntropyRateWidth-1:0] entropy_rate_i;
+logic [EntropyRateWidth-1:0] entropy_rate_o; 
 
 entropy #(
-/*P*/ .EntropyInWidth ( EntropyInWidth ),
 /*P*/ .EntropyRateWidth ( EntropyRateWidth )
 ) i_entropy (
 /*I*/ .entropy_ack_i ( entropy_ack_i ),
-/*I*/ .entropy_i ( entropy_i[EntropyInWidth-1:0] ),
-/*I*/ .entropy_rate_i ( entropy_rate_i[EntropyRateWidth-1:0] ),
-/*I*/ .clk_src_sys_jen_i ( clk_src_sys_jen_i ),
-/*I*/ .clk_ast_es_i ( clk_ast_es_i ),
+/*I*/ .entropy_i ( entropy_i ),
+/*I*/ .entropy_rate_i ( entropy_rate_o[EntropyRateWidth-1:0] ),
+/*I*/ .clk_src_sys_jen_i ( clk_src_sys_jen_i ), 
+/*I*/ .clk_ast_es_i ( clk_ast_es_i ), 
 /*I*/ .rst_ast_es_ni ( rst_ast_es_ni ),
-/*I*/ .clk_src_sys_i ( clk_src_sys_o ),
+/*I*/ .clk_src_sys_i ( clk_src_sys_o ), 
 /*I*/ .rst_src_sys_ni ( vcmain_pok_o ),
 /*I*/ .scan_mode_i ( scan_mode_i ),
 /*O*/ .entropy_req_o ( entropy_req_o )
@@ -415,101 +418,92 @@
 
 // RNG (Always ON)
 rng #(
+`ifndef VERILATOR
+// synopsys translate_off
+/*P*/ .RNG_EN_RDLY ( RNG_EN_RDLY ),
+// synopsys translate_on
+`endif
 /*P*/ .EntropyStreams ( EntropyStreams )
 ) i_rng (
-/*O*/ .rng_ok_o ( rng_ok_o ),
-/*O*/ .rng_b_o ( rng_b_o[EntropyStreams-1:0] ),
-/*I*/ .rng_en_i ( rng_en_i ),
 /*I*/ .clk_i ( clk_ast_rng_i ),
-/*I*/ .rst_ni ( rst_ast_rng_ni )
+/*I*/ .rst_ni ( rst_ast_rng_ni ),
+/*I*/ .vcaon_pok_i ( vcaon_pok ),
+/*I*/ .rng_en_i ( rng_en_i ),
+/*O*/ .rng_b_o ( rng_b_o[EntropyStreams-1:0] ),
+/*O*/ .rng_val_o ( rng_val_o )
 );
 
 
 //////////////////////////////////
 // Alerts (Always ON)
 /////////////////////////////////
-// Local signals for testing hook
-logic as_alert_i;     assign as_alert_i = 1'b0;
-logic cg_alert_i;     assign cg_alert_i = 1'b0;
-logic gd_alert_i;     assign gd_alert_i = 1'b0;
-logic ts_alert_hi_i;  assign ts_alert_hi_i = 1'b0;
-logic ts_alert_lo_i;  assign ts_alert_lo_i = 1'b0;
-logic ls_alert_i;     assign ls_alert_i = 1'b0;
-logic ot_alert_i;     assign ot_alert_i = 1'b0;
 
 // Active Shield (AS)
-gen_alert i_as_alert (
-/*I*/ .gen_alert_i ( as_alert_i ),
-/*I*/ .gen_alert_trig_i ( as_alert_trig_i ),
-/*I*/ .gen_alert_ack_i ( as_alert_ack_i ),
+gen_alert i_alert_as (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( as_alert_trig_i ),
+/*I*/ .gen_alert_ack_i ( as_alert_ack_i ),
 /*O*/ .gen_alert_po ( as_alert_po ),
 /*O*/ .gen_alert_no ( as_alert_no )
 );
 
 // Clock Glitch (CG)
-gen_alert i_cg_alert (
-/*I*/ .gen_alert_i ( cg_alert_i ),
-/*I*/ .gen_alert_trig_i ( cg_alert_trig_i ),
-/*I*/ .gen_alert_ack_i ( cg_alert_ack_i ),
+gen_alert i_alert_cg (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( cg_alert_trig_i ),
+/*I*/ .gen_alert_ack_i ( cg_alert_ack_i ),
 /*O*/ .gen_alert_po ( cg_alert_po ),
 /*O*/ .gen_alert_no ( cg_alert_no )
 );
 
 // Glitch Detector (GD)
-gen_alert i_gd_alert (
-/*I*/ .gen_alert_i ( gd_alert_i ),
-/*I*/ .gen_alert_trig_i ( gd_alert_trig_i ),
-/*I*/ .gen_alert_ack_i ( gd_alert_ack_i ),
+gen_alert i_alert_gd (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( gd_alert_trig_i ),
+/*I*/ .gen_alert_ack_i ( gd_alert_ack_i ),
 /*O*/ .gen_alert_po ( gd_alert_po ),
 /*O*/ .gen_alert_no ( gd_alert_no )
 );
 
 // Temprature Sensor High (TS Hi)
-gen_alert i_ts_alert_hi (
-/*I*/ .gen_alert_i ( ts_alert_hi_i ),
-/*I*/ .gen_alert_trig_i ( ts_alert_hi_trig_i ),
-/*I*/ .gen_alert_ack_i ( ts_alert_hi_ack_i ),
+gen_alert i_alert_ts_hi (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( ts_alert_hi_trig_i ),
+/*I*/ .gen_alert_ack_i ( ts_alert_hi_ack_i ),
 /*O*/ .gen_alert_po ( ts_alert_hi_po ),
 /*O*/ .gen_alert_no ( ts_alert_hi_no )
 );
 
 // Temprature Sensor Low (TS Lo)
-gen_alert i_ts_alert_lo (
-/*I*/ .gen_alert_i ( ts_alert_lo_i ),
-/*I*/ .gen_alert_trig_i ( ts_alert_lo_trig_i ),
-/*I*/ .gen_alert_ack_i ( ts_alert_lo_ack_i ),
+gen_alert i_alert_ts_lo (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( ts_alert_lo_trig_i ),
+/*I*/ .gen_alert_ack_i ( ts_alert_lo_ack_i ),
 /*O*/ .gen_alert_po ( ts_alert_lo_po ),
 /*O*/ .gen_alert_no ( ts_alert_lo_no )
 );
 
 // Light Sensor (LS)
-gen_alert i_ls_alert (
-/*I*/ .gen_alert_i ( ls_alert_i ),
-/*I*/ .gen_alert_trig_i ( ls_alert_trig_i ),
-/*I*/ .gen_alert_ack_i ( ls_alert_ack_i ),
+gen_alert i_alert_ls (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( ls_alert_trig_i ),
+/*I*/ .gen_alert_ack_i ( ls_alert_ack_i ),
 /*O*/ .gen_alert_po ( ls_alert_po ),
 /*O*/ .gen_alert_no ( ls_alert_no )
 );
 
 // Other Alert (OT)
-gen_alert i_ot_alert (
-/*I*/ .gen_alert_i ( ot_alert_i ),
-/*I*/ .gen_alert_trig_i ( ot_alert_trig_i ),
-/*I*/ .gen_alert_ack_i ( ot_alert_ack_i ),
+gen_alert i_alert_ot (
 /*I*/ .clk_i ( clk_ast_alert_i ),
 /*I*/ .rst_ni ( rst_ast_alert_ni ),
+/*I*/ .gen_alert_trig_i ( ot_alert_trig_i ),
+/*I*/ .gen_alert_ack_i ( ot_alert_ack_i ),
 /*O*/ .gen_alert_po ( ot_alert_po ),
 /*O*/ .gen_alert_no ( ot_alert_no )
 );
@@ -520,29 +514,44 @@
 /////////////////////////////////
 
 // AST REGs (Always ON)
+ast_reg_pkg::ast_reg2hw_t reg2hw; // Write (To HW)
+ast_reg_pkg::ast_hw2reg_t hw2reg; // Read  (From HW)
+
 ast_reg_top i_ast_reg_top (
 /*I*/ .clk_i ( clk_ast_tlul_i ),
 /*I*/ .rst_ni ( rst_ast_tlul_ni ),
 /*I*/ .tl_i ( tl_i ),
 /*O*/ .tl_o ( tl_o ),
 /*O*/ .reg2hw ( reg2hw ),
+/*I*/ .hw2reg ( hw2reg ),
 /*I*/ .devmode_i ( 1'b0 )
 );
 
-// Register output to AST
+// Registers Output to AST
 logic [32-1:0] ast_rwtype0_q;
 logic [11-1:0] ast_rwtype1_q;
 
-assign ast_rwtype0_q = reg2hw.rwtype0.q;
+assign ast_rwtype0_q = reg2hw.rwtype0.q; 
 assign ast_rwtype1_q = { reg2hw.rwtype1.field15_8.q,
                          reg2hw.rwtype1.field4.q,
                          reg2hw.rwtype1.field1.q,
-                         reg2hw.rwtype1.field0.q };
+                         reg2hw.rwtype1.field0.q }; 
 
-// TODO: Temporrary outputs assignment
-assign entropy_rate_i = 4'd5;
-assign ast2padmux_o = {Ast2PadOutWidth{1'b0}};   // DFT from AST Analog/Digital
+// AST to Registers Input
+assign hw2reg.rwtype0.d = 32'h0000_0000;
+assign hw2reg.rwtype0.de = 1'b0;
+
+
+///////////////////////////////////////
+// DFT to PADs / PADs to DFT
+///////////////////////////////////////
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+// TODO: Temporrary assignment
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+assign entropy_rate_o = 4'd5;
 assign usb_io_pu_cal_o = {UsbCalibWidth{1'b0}};  // From AST Regfile
 
+assign ast2padmux_o = {Ast2PadOutWidth{1'b0}};   // DFT from AST Analog/Digital
+
 
 endmodule // of ast
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
new file mode 100644
index 0000000..0add361
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
@@ -0,0 +1,45 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: ast_pkg
+// *Module Description: AST Package
+//############################################################################
+
+package ast_pkg;
+
+`ifndef VERILATOR
+// synopsys translate_off
+/////////////////////////////////
+// Delay Parameters from Spec
+/////////////////////////////////
+// POKs
+parameter time VCC_POK_RDLY    = 3us;
+parameter time VCC_POK_FDLY    = 500ns;
+parameter time VCAON_POK_RDLY  = 3us;
+parameter time VCAON_POK_FDLY  = 500ns;
+parameter time VCMAIN_POK_RDLY = 3us;
+parameter time VCMAIN_POK_FDLY = 500ns;
+parameter time VIOA_POK_RDLY   = 3us;
+parameter time VIOA_POK_FDLY   = 500ns;
+parameter time VIOB_POK_RDLY   = 3us;
+parameter time VIOB_POK_FDLY   = 500ns;
+// Main Regulator
+parameter time MPVCC_RDLY      = 5us;
+parameter time MPVCC_FDLY      = 100ns;
+parameter time MPPD_RDLY       = 50us;
+parameter time MPPD_FDLY       = 1us;
+// Clocks
+parameter time SYS_EN_RDLY     = 5us;
+parameter time USB_EN_RDLY     = 5us;
+parameter time USB_VAL_RDLY    = 80ns;   // Reduced for simulation from 50ms 
+parameter time USB_VAL_FDLY    = 80ns; 
+parameter time IO_EN_RDLY      = 5us;
+parameter time AON_EN_RDLY     = 5us;
+parameter time RNG_EN_RDLY     = 5us;
+// synopsys translate_on
+`endif
+// ADC
+parameter int AdcCnvtClks      = 22;
+
+endpackage  // of ana_pkg
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv
index 58b8eaa..3a42b2d 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv
@@ -29,6 +29,11 @@
   } ast_reg2hw_rwtype1_reg_t;
 
 
+  typedef struct packed {
+    logic [31:0] d;
+    logic        de;
+  } ast_hw2reg_rwtype0_reg_t;
+
 
   ///////////////////////////////////////
   // Register to internal design logic //
@@ -41,6 +46,9 @@
   ///////////////////////////////////////
   // Internal design logic to register //
   ///////////////////////////////////////
+  typedef struct packed {
+    ast_hw2reg_rwtype0_reg_t rwtype0; // [32:1]
+  } ast_hw2reg_t;
 
   // Register Address
   parameter logic [2:0] AST_RWTYPE0_OFFSET = 3'h 0;
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
index 54933e8..e6bd8f3 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
@@ -15,6 +15,7 @@
   output tlul_pkg::tl_d2h_t tl_o,
   // To HW
   output ast_reg_pkg::ast_reg2hw_t reg2hw, // Write
+  input  ast_reg_pkg::ast_hw2reg_t hw2reg, // Read
 
   // Config
   input devmode_i // If 1, explicit error return for unmapped register access
@@ -102,8 +103,8 @@
     .wd     (rwtype0_wd),
 
     // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
+    .de     (hw2reg.rwtype0.de),
+    .d      (hw2reg.rwtype0.d ),
 
     // to internal hardware
     .qe     (),
diff --git a/hw/top_earlgrey/ip/ast/rtl/entropy.sv b/hw/top_earlgrey/ip/ast/rtl/entropy.sv
index 13ff835..235ef8a 100644
--- a/hw/top_earlgrey/ip/ast/rtl/entropy.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/entropy.sv
@@ -2,148 +2,129 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: entropy
 // *Module Description:  Entropy
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module entropy #(
-   parameter int EntropyInWidth = 1,
-   parameter int EntropyRateWidth = 4
+  parameter int EntropyRateWidth = 4
 ) (
-   input entropy_ack_i,
-   input [EntropyInWidth-1:0] entropy_i,
-   input [EntropyRateWidth-1:0] entropy_rate_i,
-   input clk_src_sys_jen_i,                           // System Source Clock Jitter Enable
-   input clk_ast_es_i,
-   input rst_ast_es_ni,
-   input clk_src_sys_i,
-   input rst_src_sys_ni,
-   input scan_mode_i,
-   output logic entropy_req_o
+  input entropy_ack_i,
+  input entropy_i,
+  input [EntropyRateWidth-1:0] entropy_rate_i,
+  input clk_src_sys_jen_i,                         // System Source Clock Jitter Enable
+  input clk_ast_es_i,
+  input rst_ast_es_ni,
+  input clk_src_sys_i,
+  input rst_src_sys_ni,
+  input scan_mode_i,
+  output logic entropy_req_o
 );
 
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+// Entropy Logic @clk_ast_es_i clock domain 
 
-///////////////////////////////////
-// Entropy & Jitter
-///////////////////////////////////
 
+///////////////////////////////////////
 // Entropy Enable
+///////////////////////////////////////
 logic entropy_enable;
-
 assign entropy_enable = rst_ast_es_ni && clk_src_sys_jen_i;
 
 // Reset De-Assert syncronizer
+//JL TODO: Concider using Prim cell
+// prim_generic_flop_2sync #(
+//    .Width ( 1 )
+// ) rst_es_da_sync (
+//    .clk_i ( clk_ast_es_i ),
+//    .rst_ni ( entropy_enable ),
+//    .d_i ( 1'b1 ),
+//    .q_o ( rst_es_n )
+// );
 logic sync1_rst_es_n, sync2_rst_es_n, rst_es_n;
 
 always_ff @( posedge clk_ast_es_i, negedge entropy_enable ) begin
-   if ( !entropy_enable ) begin
-      sync1_rst_es_n <= 1'b0;
-      sync2_rst_es_n <= 1'b0;
-   end
-   else begin
-      sync1_rst_es_n <= 1'b1;
-      sync2_rst_es_n <= sync1_rst_es_n;
-   end
+  if ( !entropy_enable ) begin
+    sync1_rst_es_n <= 1'b0;
+    sync2_rst_es_n <= 1'b0;
+  end
+  else begin
+    sync1_rst_es_n <= 1'b1;
+    sync2_rst_es_n <= sync1_rst_es_n;
+  end
 end
 
 assign rst_es_n = scan_mode_i ? rst_ast_es_ni : sync2_rst_es_n;
 
+
+///////////////////////////////////////
 // Entropy Rate
-logic [(1<<EntropyRateWidth)-1:0] rate_cnt;
-logic [32-1:0] entropy_rate;
+///////////////////////////////////////
 logic read_entropy;
+logic [(1<<EntropyRateWidth)-1:0] erate_cnt;
+logic [32-1:0] entropy_rate;
 
 always_ff @( posedge clk_ast_es_i, negedge rst_es_n ) begin
-   if ( !rst_es_n )          rate_cnt <= {(1<<EntropyRateWidth){1'b0}};
-   else if ( read_entropy )  rate_cnt <= {(1<<EntropyRateWidth){1'b0}};
-   else                      rate_cnt <= rate_cnt + 1'b1;
+  if ( !rst_es_n )         erate_cnt <= {(1<<EntropyRateWidth){1'b0}};
+  else if ( read_entropy ) erate_cnt <= {(1<<EntropyRateWidth){1'b0}};
+  else                     erate_cnt <= erate_cnt + 1'b1;
 end
 
 assign entropy_rate = (1 << entropy_rate_i);
-assign read_entropy = (rate_cnt == entropy_rate[(1 << EntropyRateWidth)-1:0]);
+assign read_entropy = (erate_cnt == entropy_rate[(1<<EntropyRateWidth)-1:0]); 
 
+
+///////////////////////////////////////
+// Entropy FIFO 
+///////////////////////////////////////
 // FIFO RDP/WRP/Level
 logic [6-1:0] fifo_cnt;            // For 32 1-bit FIFO
 logic [5-1:0] fifo_rdp, fifo_wrp;  // FIFO read pointer & write pointer
-logic [32-1:0] fifo_data;          // 32 1-bi FIFOt
+logic [32-1:0] fifo_data;          // 32 1-bi FIFOt 
 logic inc_fifo_cnt, dec_fifo_cnt;
 
 assign inc_fifo_cnt = (fifo_cnt < 6'h20) && entropy_ack_i;
 assign dec_fifo_cnt = (fifo_cnt != 6'h00) && read_entropy;
 
 always_ff @( posedge clk_ast_es_i, negedge rst_es_n ) begin
-   if ( !rst_es_n ) begin
-      fifo_cnt <= 6'h00;
-      fifo_rdp <= 5'h00;
-      fifo_wrp <= 5'h00;
-   end
-   else if ( inc_fifo_cnt && dec_fifo_cnt ) begin
-      fifo_rdp <= fifo_rdp + 1'b1;
-      fifo_wrp <= fifo_wrp + 1'b1;
-   end
-   else if ( inc_fifo_cnt ) begin
-      fifo_cnt <= fifo_cnt + 1'b1;
-      fifo_wrp <= fifo_wrp + 1'b1;
-   end
-   else if ( dec_fifo_cnt ) begin
-      fifo_cnt <= fifo_cnt - 1'b1;
-      fifo_rdp <= fifo_rdp + 1'b1;
-   end
+  if ( !rst_es_n ) begin
+    fifo_cnt <= 6'h00;
+    fifo_rdp <= 5'h00;
+    fifo_wrp <= 5'h00;
+  end
+  else if ( inc_fifo_cnt && dec_fifo_cnt ) begin
+    fifo_rdp <= fifo_rdp + 1'b1;
+    fifo_wrp <= fifo_wrp + 1'b1;
+  end
+  else if ( inc_fifo_cnt ) begin
+    fifo_cnt <= fifo_cnt + 1'b1;
+    fifo_wrp <= fifo_wrp + 1'b1;
+  end
+  else if ( dec_fifo_cnt ) begin
+    fifo_cnt <= fifo_cnt - 1'b1;
+    fifo_rdp <= fifo_rdp + 1'b1;
+  end
 end
 
 // Request
 always_ff @( posedge clk_ast_es_i, negedge rst_es_n ) begin
-   if ( !rst_es_n )
-      entropy_req_o <= 1'b0;
-   else if ( fifo_cnt < 6'h10 )
-      entropy_req_o <= 1'b1;  // Half
-   else if ( (fifo_cnt == 6'h1f) && inc_fifo_cnt && ~dec_fifo_cnt )
-      entropy_req_o <= 1'b0;  // Full
+  if ( !rst_es_n )
+    entropy_req_o <= 1'b0;
+  else if ( fifo_cnt < 6'h10 )
+    entropy_req_o <= 1'b1;  // Half
+  else if ( (fifo_cnt == 6'h1f) && inc_fifo_cnt && ~dec_fifo_cnt )
+    entropy_req_o <= 1'b0;  // Full
 end
 
 // FIFO Write
 always_ff @( posedge clk_ast_es_i, negedge rst_es_n ) begin
-   if ( !rst_es_n )          fifo_data[32-1:0]   <= {32{1'b0}};
-   else if ( inc_fifo_cnt )  fifo_data[fifo_wrp] <= entropy_i[0];
+  if ( !rst_es_n )         fifo_data[32-1:0]   <= {32{1'b0}};
+  else if ( inc_fifo_cnt ) fifo_data[fifo_wrp] <= entropy_i;
 end
 
-// FIFO Read
+// FIFO Read Out
 wire fifo_entropy_out = fifo_data[fifo_rdp];
 
 
-// Sync to SYS clock
-logic lfsr_data_in;
-logic sync1_lfsr_data_in, sync2_lfsr_data_in;
-
-always_ff @( posedge clk_src_sys_i, negedge rst_src_sys_ni ) begin
-   if ( !rst_src_sys_ni ) begin
-      sync1_lfsr_data_in <= 1'b0;
-      sync2_lfsr_data_in <= 1'b0;
-   end
-   else begin
-      sync1_lfsr_data_in <= fifo_entropy_out;
-      sync2_lfsr_data_in <= sync1_lfsr_data_in;
-   end
-end
-
-assign lfsr_data_in = sync2_lfsr_data_in;
-
-// prim_generic_flop_2sync #(
-//    .Width ( 1 )
-// ) entropy_sync (
-//    .clk_i ( clk_src_sys_i ),
-//    .rst_ni ( rst_src_sys_ni ),
-//    .d_i ( fifo_entropy_out ),
-//    .q_o ( lfsr_data_in )
-// );
-
-
-// Jitter
-// random 0-2000ps (upto +20% of SYS clock)
-// jitter = sys_jen ? $urandom_range(2000, 0) : 0;
-
-
 endmodule  // of entropy
diff --git a/hw/top_earlgrey/ip/ast/rtl/gen_alert.sv b/hw/top_earlgrey/ip/ast/rtl/gen_alert.sv
index 0460204..044fd87 100644
--- a/hw/top_earlgrey/ip/ast/rtl/gen_alert.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/gen_alert.sv
@@ -2,37 +2,37 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: gen_alert
 // *Module Description:  Generic Alert
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module gen_alert (
-   input gen_alert_i,
-   input gen_alert_trig_i,
-   input gen_alert_ack_i,
-   input clk_i,
-   input rst_ni,
-   output logic gen_alert_po,
-   output logic gen_alert_no
+  input clk_i,
+  input rst_ni,
+  input gen_alert_trig_i,
+  input gen_alert_ack_i,
+  output logic gen_alert_po,
+  output logic gen_alert_no
 );
-
 // Behavioral Model
-logic gen_alert_ff, gen_alert_set, gen_alert_clr;
 
-assign gen_alert_set = gen_alert_i | gen_alert_trig_i;
+// Hook for testing
+logic gen_alert;
+assign gen_alert = 1'b0;
+
+logic gen_alert_set, gen_alert_clr;
+
+assign gen_alert_set = gen_alert | gen_alert_trig_i;
 assign gen_alert_clr = ~gen_alert_set & gen_alert_ack_i;
 
 always_ff @( posedge clk_i, negedge rst_ni ) begin
-   if ( !rst_ni )             gen_alert_ff <= 1'b0;
-   else if ( gen_alert_set )  gen_alert_ff <= 1'b1;
-   else if ( gen_alert_clr )  gen_alert_ff <= 1'b0;
+  if ( !rst_ni )            gen_alert_po <= 1'b0;
+  else if ( gen_alert_set ) gen_alert_po <= 1'b1;
+  else if ( gen_alert_clr ) gen_alert_po <= 1'b0;
 end
 
-assign gen_alert_po =  gen_alert_ff;
-assign gen_alert_no = ~gen_alert_ff;
+assign gen_alert_no = ~gen_alert_po;
 
 
 endmodule  // of gen_alert
diff --git a/hw/top_earlgrey/ip/ast/rtl/gen_pok.sv b/hw/top_earlgrey/ip/ast/rtl/gen_pok.sv
index 9cd74ab..aef18b9 100644
--- a/hw/top_earlgrey/ip/ast/rtl/gen_pok.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/gen_pok.sv
@@ -2,48 +2,47 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: gen_pok
 // *Module Description:  Generic Power OK
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module gen_pok #(
+`ifndef VERILATOR
 // synopsys translate_off
-  parameter time POK_RDLY = 3us,
-  parameter time POK_FDLY = 500ns
+ parameter time POK_RDLY = 3us,
+ parameter time POK_FDLY = 500ns
 // synopsys translate_on
+`endif
 ) (
-   input gen_supp_a,
-   input gen_supp_i,
-   output logic gen_pok_o
+  output logic gen_pok_o
 );
-// synopsys translate_off
-// Behavioral Model
-logic supp_a;
 
+// Behavioral Model
+
+`ifndef VERILATOR
+// synopsys translate_off
+// Local signal for testing hook
+logic gen_supp_a;
+assign gen_supp_a = 1'b1;
 
 // The initial is needed to clear the X of the delays at the start
 // Also to force a power-up effect at the bgining.
-logic init_start;
+logic init_start; 
 
 initial begin
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
+  init_start = 1'b1; #1;
+  init_start = 1'b0;
 end
 
-always_ff @( init_start, posedge gen_supp_a, negedge gen_supp_a ) begin
-    if ( init_start )
-       supp_a <= 1'b0;
-    else if ( !init_start && gen_supp_a )
-       supp_a <= #(POK_RDLY) gen_supp_a;
-    else if ( !init_start && !gen_supp_a )
-       supp_a <= #(POK_FDLY) gen_supp_a;
+always @( * ) begin
+  if ( init_start )                      gen_pok_o <= 1'b0;
+  else if ( !init_start && gen_supp_a )  gen_pok_o <= #(POK_RDLY) gen_supp_a;
+  else if ( !init_start && !gen_supp_a ) gen_pok_o <= #(POK_FDLY) gen_supp_a;
 end
-
-assign gen_pok_o = supp_a && gen_supp_i;
 // synopsys translate_on
+`endif
 
 
 endmodule  // of gen_pok
+
diff --git a/hw/top_earlgrey/ip/ast/rtl/io_clk.sv b/hw/top_earlgrey/ip/ast/rtl/io_clk.sv
index cbd1172..fafaedc 100644
--- a/hw/top_earlgrey/ip/ast/rtl/io_clk.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/io_clk.sv
@@ -2,49 +2,58 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: io_clk
 // *Module Description: IO Clock
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module io_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time IO_EN_RDLY = 10us,
-   parameter time IO_EN_FDLY = 100ns
+  parameter time IO_EN_RDLY = 5us
 // synopsys translate_on
+`endif
 ) (
-   input rst_ni,                  // Reset
-   input clk_src_io_en_i,         // IO Source Clock Enable
-   output logic clk_src_io_o,     // IO Source Clock
-   output logic clk_src_io_val_o  // IO Source Clock Valid
+  input vcmain_pok_i,              // VCMAIN POK @1.1V
+  input clk_src_io_en_i,           // IO Source Clock Enable
+  output logic clk_src_io_o,       // IO Source Clock
+  output logic clk_src_io_val_o    // IO Source Clock Valid
 );
 
-logic clk, io_en, clk_en;
+logic clk, io_clk_val, rst_n;
 
 // Behavioral Model
+assign rst_n = vcmain_pok_i;
 
 // Clock Oscilator
 io_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .IO_EN_RDLY ( IO_EN_RDLY ),
-/*P*/ .IO_EN_FDLY ( IO_EN_FDLY )
+/*P*/ .IO_EN_RDLY ( IO_EN_RDLY )
 // synopsys translate_on
+`endif
 ) i_io_osc (
+/*I*/ .vcmain_pok_i ( vcmain_pok_i ),
 /*I*/ .io_en_i ( clk_src_io_en_i ),
-/*O*/ .io_clk_o ( clk ),
-/*O*/ .io_clk_en_o ( io_en )
+/*O*/ .io_clk_o ( clk )
 );
 
-always_ff @( posedge clk, negedge rst_ni ) begin
-   if ( !rst_ni )  clk_en <= 1'b0;
-   else            clk_en <= io_en;
-end
 
 // Clock & Valid
-assign clk_src_io_o = clk_en ? ~clk : 1'b0;
-assign clk_src_io_val_o = clk_en;
+assign clk_src_io_o = clk;
+
+wire rst_val_n = rst_n && clk_src_io_en_i;
+
+// 2-stage deassertion
+always_ff @( posedge clk, negedge rst_val_n ) begin
+  if ( !rst_val_n )  begin
+    io_clk_val       <= 1'b0;
+    clk_src_io_val_o <= 1'b0;
+  end else begin
+    io_clk_val       <= 1'b1;
+    clk_src_io_val_o <= io_clk_val;
+  end
+end
 
 
 endmodule  // of io_clk
diff --git a/hw/top_earlgrey/ip/ast/rtl/io_osc.sv b/hw/top_earlgrey/ip/ast/rtl/io_osc.sv
index 848e969..7305148 100644
--- a/hw/top_earlgrey/ip/ast/rtl/io_osc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/io_osc.sv
@@ -2,52 +2,56 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: io_osc
 // *Module Description: IO Clock Oscilator
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module io_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time IO_EN_RDLY = 10us,
-   parameter time IO_EN_FDLY = 100ns
+  parameter time IO_EN_RDLY = 10us
 // synopsys translate_on
+`endif
 ) (
-   input io_en_i,              // IO Source Clock Enable
-   output logic io_clk_o,      // IO Clock Output
-   output logic io_clk_en_o    // IO Clock Enable Output
+  input vcmain_pok_i,    // VCMAIN POK @1.1V
+  input io_en_i,         // IO Source Clock Enable
+  output logic io_clk_o  // IO Clock Output
 );
 
+// Behavioral Model
+
+`ifndef VERILATOR
 // synopsys translate_off
 localparam real IO_CLK_PERIOD = 1000000/96;  // ~10416.666667ps (96Mhz)
-
-logic init_start, clk;
+logic clk, en_osc, en_osc_re, en_osc_fe;
 
 initial begin
-   clk = 1'b0;
-   $display("\nIO Clock Period: %0dps", IO_CLK_PERIOD);
-   // init_start = 1'b0; #1;
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
+  clk = 1'b0;
+  $display("\nIO Clock Period: %0dps", IO_CLK_PERIOD);
 end
 
+always @( * ) begin
+  if ( !vcmain_pok_i )                en_osc_re = 1'b0;  // For Startup
+  else if ( io_en_i && vcmain_pok_i ) en_osc_re = #(IO_EN_RDLY) 1'b1;
+  else                                en_osc_re = 1'b0;
+end
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk or negedge vcmain_pok_i ) begin
+  if ( !vcmain_pok_i ) en_osc_fe <= 1'b0;
+  else                 en_osc_fe <= en_osc_re;
+end
+
+assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
+
 always begin
-   #(IO_CLK_PERIOD/2000) clk = ~clk;
+   #(IO_CLK_PERIOD/2000) clk = ~clk && en_osc;
 end
 
 assign io_clk_o = clk;
-
-always_ff @( init_start, posedge io_en_i, negedge io_en_i ) begin
-    if ( init_start )
-       io_clk_en_o <= 1'b0;
-    else if ( !init_start && io_en_i )
-       io_clk_en_o <= #(IO_EN_RDLY) io_en_i;
-    else if ( !init_start && !io_en_i )
-       io_clk_en_o <= #(IO_EN_FDLY) io_en_i;
-end
 // synopsys translate_on
+`endif
 
 
 endmodule  // of io_osc
diff --git a/hw/top_earlgrey/ip/ast/rtl/lc_ctrl_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/lc_ctrl_pkg.sv
new file mode 100644
index 0000000..82b6ca7
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/rtl/lc_ctrl_pkg.sv
@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package lc_ctrl_pkg;
+
+  /////////////////////////////////
+  // General Typedefs and Params //
+  /////////////////////////////////
+
+  parameter int LcValueWidth = 16;
+  parameter int LcTokenWidth = 128;
+  parameter int NumLcStateValues = 12;
+  parameter int LcStateWidth = NumLcStateValues * LcValueWidth;
+  parameter int NumLcCountValues = 32;
+
+  typedef enum logic [LcValueWidth-1:0] {
+    Blk = 16'h0000, // blank
+    Set = 16'hF5FA  // programmed
+  } lc_value_e;
+
+  typedef enum logic [LcStateWidth-1:0] {
+    // Halfword idx   :  11 | 10 |  9 |  8 |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0
+    LcStRaw           = {Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk},
+    LcStTestUnlocked0 = {Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Set},
+    LcStTestLocked0   = {Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Set, Set},
+    LcStTestUnlocked1 = {Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Set, Set, Set},
+    LcStTestLocked1   = {Blk, Blk, Blk, Blk, Blk, Blk, Blk, Blk, Set, Set, Set, Set},
+    LcStTestUnlocked2 = {Blk, Blk, Blk, Blk, Blk, Blk, Blk, Set, Set, Set, Set, Set},
+    LcStTestLocked2   = {Blk, Blk, Blk, Blk, Blk, Blk, Set, Set, Set, Set, Set, Set},
+    LcStTestUnlocked3 = {Blk, Blk, Blk, Blk, Blk, Set, Set, Set, Set, Set, Set, Set},
+    LcStDev           = {Blk, Blk, Blk, Blk, Set, Set, Set, Set, Set, Set, Set, Set},
+    LcStProd          = {Blk, Blk, Blk, Set, Blk, Set, Set, Set, Set, Set, Set, Set},
+    LcStProdEnd       = {Blk, Blk, Set, Blk, Blk, Set, Set, Set, Set, Set, Set, Set},
+    LcStRma           = {Set, Set, Blk, Set, Set, Set, Set, Set, Set, Set, Set, Set},
+    LcStScrap         = {Set, Set, Set, Set, Set, Set, Set, Set, Set, Set, Set, Set}
+  } lc_state_e;
+
+  typedef lc_value_e [NumLcCountValues-1:0] lc_cnt_t;
+
+  ////////////////////////////////
+  // Typedefs for LC Interfaces //
+  ////////////////////////////////
+
+  parameter int TxWidth = 4;
+  typedef enum logic [TxWidth-1:0] {
+    On  = 4'b1010,
+    Off = 4'b0101
+  } lc_tx_e;
+
+  typedef struct packed {
+    lc_tx_e state;
+  } lc_tx_t;
+
+  parameter lc_tx_t LC_TX_DEFAULT = Off;
+
+endpackage : lc_ctrl_pkg
diff --git a/hw/top_earlgrey/ip/ast/rtl/main_rglt.sv b/hw/top_earlgrey/ip/ast/rtl/main_rglt.sv
deleted file mode 100644
index 2a79810..0000000
--- a/hw/top_earlgrey/ip/ast/rtl/main_rglt.sv
+++ /dev/null
@@ -1,60 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//############################################################################
-//
-// *Name: main_rglt
-// *Module Description: Main Regulator
-//
-//############################################################################
-`timescale 1ns/1ps
-
-module main_rglt #(
-// synopsys translate_off
-   parameter time MRVCC_RDLY = 5us,
-   parameter time MRVCC_FDLY = 100ns,
-   parameter time MRPD_RDLY = 50us,
-   parameter time MRPD_FDLY = 1us
-// synopsys translate_on
-) (
-   input vcc_pok_i,
-   input main_pd_ni,
-   output logic main_pwr_dly
-);
-
-// Behavioral Model
-// synopsys translate_off
-
-logic mr_vcc_dly, mr_pd_dly;
-
-// The initial is needed to clear the X of the delays at the start
-logic init_start;
-
-initial begin
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
-end
-
-always_ff @( init_start, posedge vcc_pok_i, negedge vcc_pok_i ) begin
-    if ( init_start )
-       mr_vcc_dly <= 1'b0;
-    else if ( !init_start && vcc_pok_i )
-       mr_vcc_dly <= #(MRVCC_RDLY) vcc_pok_i;
-    else if ( !init_start && !vcc_pok_i )
-       mr_vcc_dly <= #(MRVCC_FDLY) vcc_pok_i;
-end
-
-always_ff @( init_start, posedge main_pd_ni, negedge main_pd_ni ) begin
-    if ( init_start )
-       mr_pd_dly <= 1'b1;
-    else if ( !init_start && main_pd_ni && vcc_pok_i )
-       mr_pd_dly <= #(MRPD_RDLY) main_pd_ni && vcc_pok_i;
-    else if ( !init_start && !main_pd_ni && vcc_pok_i )
-       mr_pd_dly <= #(MRPD_FDLY) main_pd_ni && vcc_pok_i;
-end
-
-assign main_pwr_dly = mr_vcc_dly && mr_pd_dly;
-
-// synopsys translate_on
-
-endmodule  // of main_rglt
diff --git a/hw/top_earlgrey/ip/ast/rtl/pdm.sv b/hw/top_earlgrey/ip/ast/rtl/pdm.sv
deleted file mode 100644
index fb98631..0000000
--- a/hw/top_earlgrey/ip/ast/rtl/pdm.sv
+++ /dev/null
@@ -1,26 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//############################################################################
-//
-// *Name: pdm
-// *Module Description: Power Down Mode
-//
-//############################################################################
-`timescale 1ns/1ps
-
-module pdm (
-   input vcc_pok_i,
-   input vcmain_pok_i,
-   input main_pd_ni,
-   output logic flash_power_down_h_o,
-   output logic flash_power_ready_h_o
-);
-
-// Behavioral Model
-
-assign flash_power_down_h_o  = ~(main_pd_ni && vcmain_pok_i);
-assign flash_power_ready_h_o = vcc_pok_i;
-
-
-endmodule  // of pdm
diff --git a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
new file mode 100644
index 0000000..4a24231
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
@@ -0,0 +1,106 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: rglts_pdm_3p3v
+// *Module Description: Regulators (MAIN & AON) & PDM Logic @3.3V
+//############################################################################
+`timescale 1ns / 10ps
+
+module rglts_pdm_3p3v 
+#(
+`ifndef VERILATOR
+// synopsys translate_off
+  parameter time MRVCC_RDLY = 5us,
+  parameter time MRVCC_FDLY = 100ns,
+  parameter time MRPD_RDLY = 50us,
+  parameter time MRPD_FDLY = 1us
+// synopsys translate_on
+`endif
+) (
+  input vcc_pok_h_i,                     // VCC (3.3V) Exist @3.3v
+  input vcmain_pok_h_i,                  // VCMAIN (1.1v) Exist @3.3v
+  input clk_src_aon_i,                   // AON Clock @1.1v 
+  input main_pd_ni,                      // VCMAIN/Regulator Power Down @1.1v
+  input [1:0] otp_power_seq_i,           // MMR0,24 in (VDD)
+  output logic main_pwr_dly_o,           // For modeling only.
+  output logic vcaon_pok_o,              // VCAON (1.1v) Exist @1.1v
+  output logic vcaon_pok_h_o,            // VCAON (1.1v) Exist @3.3v
+  output logic flash_power_down_h_o,     // 
+  output logic flash_power_ready_h_o,    // 
+  output logic [1:0] otp_power_seq_h_o   // MMR0,24 masked by PDM, out (VCC)
+);
+
+logic main_pd_h_n, clk_src_aon_h;
+logic [1:0] otp_power_seq_h;
+
+import ast_pkg::*;
+
+// Behavioral Model
+
+
+// Up Level Shefters
+assign main_pd_h_n = main_pd_ni;
+assign clk_src_aon = clk_src_aon_i;
+assign otp_power_seq_h = otp_power_seq_i;
+
+`ifndef VERILATOR
+// synopsys translate_off
+logic mr_vcc_dly, mr_pd_dly;
+
+// The initial is needed to clear the X of the delays at the start
+logic init_start;
+
+initial begin
+  init_start = 1'b1; #1; 
+  init_start = 1'b0;
+end
+
+always_ff @( init_start, posedge vcc_pok_h_i, negedge vcc_pok_h_i ) begin
+  if ( init_start )
+    mr_vcc_dly <= 1'b0;
+  else if ( !init_start && vcc_pok_h_i )
+    mr_vcc_dly <= #(MRVCC_RDLY) vcc_pok_h_i;
+  else if ( !init_start && !vcc_pok_h_i )
+    mr_vcc_dly <= #(MRVCC_FDLY) vcc_pok_h_i;
+end
+
+always_ff @( init_start, posedge main_pd_h_n, negedge main_pd_h_n ) begin
+  if ( init_start )        
+    mr_pd_dly <= 1'b1;
+  else if ( !init_start && main_pd_h_n && vcc_pok_h_i )
+    mr_pd_dly <= #(MRPD_RDLY) main_pd_h_n && vcc_pok_h_i;
+  else if ( !init_start && !main_pd_h_n && vcc_pok_h_i )
+    mr_pd_dly <= #(MRPD_FDLY) main_pd_h_n && vcc_pok_h_i;
+end
+
+assign main_pwr_dly_o = mr_vcc_dly && mr_pd_dly;
+
+gen_pok #( 
+// synopsys translate_off
+/*P*/ .POK_RDLY ( VCMAIN_POK_RDLY ), 
+/*P*/ .POK_FDLY ( VCMAIN_POK_FDLY ) 
+// synopsys translate_on
+) i_vcaon_pok (
+/*O*/ .gen_pok_o ( vcaon_pok_o )
+);
+assign vcaon_pok_h_o = vcaon_pok_o;  // Level Shifter
+// synopsys translate_on
+`endif
+
+
+///////////////////////////////////////
+// Flash
+///////////////////////////////////////
+assign flash_power_down_h_o  = ~(main_pd_h_n && vcmain_pok_h_i); 
+assign flash_power_ready_h_o = vcc_pok_h_i;
+
+
+///////////////////////////////////////
+// OTP
+///////////////////////////////////////
+assign otp_power_seq_h_o[0] = flash_power_down_h_o && otp_power_seq_h[0]; 
+assign otp_power_seq_h_o[1] = flash_power_down_h_o || otp_power_seq_h[1]; 
+
+
+endmodule  // of rglts_pdm_3p3v
diff --git a/hw/top_earlgrey/ip/ast/rtl/rng.sv b/hw/top_earlgrey/ip/ast/rtl/rng.sv
index dd964d6..72b9725 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rng.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rng.sv
@@ -2,45 +2,48 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: rng
 // *Module Description:  Random (bit/s) Generator
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module rng #(
-   parameter int EntropyStreams = 4
+`ifndef VERILATOR
+// synopsys translate_off
+  parameter time RNG_EN_RDLY = 5us,
+// synopsys translate_on
+`endif
+  parameter int EntropyStreams = 4
 ) (
-   output logic rng_ok_o,
-   output logic [EntropyStreams-1:0] rng_b_o,
-   input rng_en_i,
-   input clk_i,
-   input rst_ni
+  input clk_i,
+  input rst_ni,
+  input vcaon_pok_i,
+  input rng_en_i,
+  output logic [EntropyStreams-1:0] rng_b_o,
+  output logic rng_val_o
 );
 
 ///////////////////////////////////////
 // Clock Oscilator
 ///////////////////////////////////////
-logic clk, rng_clk_en;
+logic clk, rng_clk_en, rng_clk, rst_n;
+assign rst_n = vcaon_pok_i;
 
 // Behavioral Model
+
 // For FPGA, it can be replace with clk_src_aon_o/4 (200K/4=50K)
-rng_osc i_rng_osc (
-/*I*/ .en_i ( rng_en_i ),
-/*O*/ .clk_o ( clk ),
-/*O*/ .clk_en_o (rng_clk_en )
+rng_osc #(
+`ifndef VERILATOR
+// synopsys translate_off
+/*P*/ .RNG_EN_RDLY ( RNG_EN_RDLY )
+// synopsys translate_on
+`endif
+) i_rng_osc (
+/*I*/ .vcaon_pok_i ( vcaon_pok_i ),
+/*I*/ .rng_en_i ( rng_en_i ),
+/*O*/ .rng_clk_o ( rng_clk_o )
 );
 
-logic rng_clk, clk_en;
-
-always_ff @( posedge clk, negedge rst_ni ) begin
-   if ( !rst_ni )  clk_en <= 1'b0;
-   else            clk_en <= rng_clk_en;
-end
-
-assign rng_clk = clk_en ? ~clk : 1'b0;
-
 
 ///////////////////////////////////////
 // LFSR for Pseudo Random Numbers
@@ -50,13 +53,13 @@
 
 assign rng_rst_n = rst_ni && rng_en_i;
 
-always_ff @(posedge rng_clk, negedge rng_rst_n ) begin
-   if ( !rng_rst_n ) begin
-      lfsr_val       <= 32'h1234_5678;
-   end else begin
-      lfsr_val[31:1] <= lfsr_val[30:0];
-      lfsr_val[0]    <= ~(lfsr_val[31] ^ lfsr_val[21] ^ lfsr_val[1] ^ lfsr_val[0]);
-   end
+always_ff @(posedge rng_clk_o, negedge rng_rst_n ) begin
+  if ( !rng_rst_n ) begin
+    lfsr_val       <= 32'h1234_5678;
+  end else begin
+    lfsr_val[31:1] <= lfsr_val[30:0];
+    lfsr_val[0]    <= ~(lfsr_val[31] ^ lfsr_val[21] ^ lfsr_val[1] ^ lfsr_val[0]);
+  end
 end
 
 
@@ -66,46 +69,47 @@
 logic rng_rdy;
 logic [2-1:0] rng_rdy_cnt;
 
-always_ff @( posedge rng_clk, negedge rng_rst_n ) begin
-   if ( !rng_rst_n )     rng_rdy_cnt <= 2'b00;
-   else if ( !rng_rdy )  rng_rdy_cnt <= rng_rdy_cnt + 1'b1;
+always_ff @( posedge rng_clk_o, negedge rng_rst_n ) begin
+  if ( !rng_rst_n )    rng_rdy_cnt <= 2'b00;
+  else if ( !rng_rdy ) rng_rdy_cnt <= rng_rdy_cnt + 1'b1;
 end
 
 assign rng_rdy = (rng_rdy_cnt == 2'b11);
 
 logic [EntropyStreams-1:0] rng_b;
 
-always_ff @( posedge rng_clk, negedge rng_rst_n ) begin
-   if ( !rng_rst_n )  rng_b <= {EntropyStreams{1'b0}};
-   else               rng_b <= lfsr_val[EntropyStreams-1:0];
+always_ff @( posedge rng_clk_o, negedge rng_rst_n ) begin
+  if ( !rng_rst_n ) rng_b <= {EntropyStreams{1'b0}};
+  else              rng_b <= lfsr_val[EntropyStreams-1:0];
 end
 
-// RNG OK!
-logic rng_ok_r;
+
+// Sync RNG OK to clk_i
+logic rng_rdy_s;
 
 always_ff @( posedge clk_i, negedge rst_ni ) begin
-   if ( !rst_ni ) begin
-      rng_ok_r <= 1'b0;
-      rng_ok_o <= 1'b0;
-   end
-   else begin
-      rng_ok_r <= rng_rdy;
-      rng_ok_o <= rng_ok_r;
-   end
+  if ( !rst_ni ) begin
+    rng_rdy_s <= 1'b0;
+    rng_val_o <= 1'b0;
+  end
+  else begin
+    rng_rdy_s <= rng_rdy;
+    rng_val_o <= rng_rdy_s;
+  end
 end
 
 // Sync RNG Bits to clk_i
 logic [EntropyStreams-1:0] rng_b_r;
 
 always_ff @( posedge clk_i, negedge rst_ni ) begin
-   if ( !rst_ni ) begin
-      rng_b_r <= {EntropyStreams{1'b0}};
-      rng_b_o <= {EntropyStreams{1'b0}};
-   end
-   else begin
-      rng_b_r <= rng_b;
-      rng_b_o <= rng_b_r;
-   end
+  if ( !rst_ni ) begin
+    rng_b_r <= {EntropyStreams{1'b0}};
+    rng_b_o <= {EntropyStreams{1'b0}};
+  end
+  else begin
+    rng_b_r <= rng_b;
+    rng_b_o <= rng_b_r;
+  end
 end
 
 
diff --git a/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv b/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv
index 329d284..11f374e 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv
@@ -2,52 +2,58 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: rng_osc
 // *Module Description: RNG Clock Oscilator
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module rng_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time EN_RDLY = 10us,
-   parameter time EN_FDLY = 100ns
+  parameter time RNG_EN_RDLY = 5us
 // synopsys translate_on
+`endif
 ) (
-   input en_i,                 // RNG Source Clock Enable
-   output logic clk_o,         // RNG Clock Output
-   output logic clk_en_o       // RNG Clock Enable Output
+  input vcaon_pok_i,        // VCAON POK @1.1V
+  input rng_en_i,           // RNG Source Clock Enable
+  output logic rng_clk_o    // RNG Clock Output
 );
 
+// Behavioral Model
+
+`ifndef VERILATOR
 // synopsys translate_off
-logic init_start, clk;
 integer CLK_PERIOD;
+logic clk, en_osc, en_osc_re, en_osc_fe;
 
 initial begin
-   clk = 1'b0;
-   // Seed is set from the vcs run command
-   CLK_PERIOD = 10**9/$urandom_range(70000, 50000);  // ns (50Khz-70Khz)
-   $display( "\nRNG Internal Clock Period: %0dns", CLK_PERIOD);
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
+  clk = 1'b0;
+  // Seed is set from the vcs run command
+  CLK_PERIOD = 10**9/$urandom_range(70000, 50000);  // ns (50Khz-70Khz)
+  $display( "\nRNG Internal Clock Period: %0dns", CLK_PERIOD);
 end
 
+always @( * ) begin
+  if ( !vcaon_pok_i )                 en_osc_re = 1'b0;  // For Startup
+  else if ( rng_en_i && vcaon_pok_i ) en_osc_re = #(RNG_EN_RDLY) 1'b1;
+  else                                en_osc_re = 1'b0;
+end
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk or negedge vcaon_pok_i ) begin
+  if ( !vcaon_pok_i ) en_osc_fe <= 1'b0;
+  else                en_osc_fe <= en_osc_re;
+end
+
+assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
+
 always begin
-   #(CLK_PERIOD/2) clk = ~clk;
+  #(CLK_PERIOD/2) clk = ~clk && en_osc;
 end
 
-assign clk_o = clk;
-
-always_ff @( init_start, posedge en_i, negedge en_i ) begin
-    if ( init_start )
-       clk_en_o <= 1'b0;
-    else if ( !init_start && en_i )
-       clk_en_o <= #(EN_RDLY) en_i;
-    else if ( !init_start && !en_i )
-       clk_en_o <= #(EN_FDLY) en_i;
-end
+assign rng_clk_o = clk;
 // synopsys translate_on
+`endif
 
 
 endmodule  // of rng_osc
diff --git a/hw/top_earlgrey/ip/ast/rtl/sys_clk.sv b/hw/top_earlgrey/ip/ast/rtl/sys_clk.sv
index 103a38f..554ce71 100644
--- a/hw/top_earlgrey/ip/ast/rtl/sys_clk.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/sys_clk.sv
@@ -2,55 +2,60 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: sys_clk
 // *Module Description: System Clock
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module sys_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time SYS_EN_RDLY = 10us,
-   parameter time SYS_EN_FDLY = 100ns,
-   parameter time SYS_JEN_RDLY = 80ns,
-   parameter time SYS_JEN_FDLY = 80ns
+  parameter time SYS_EN_RDLY = 5us
 // synopsys translate_on
+`endif
 ) (
-   input clk_src_sys_en_i,                       // System Source Clock Enable
-   input clk_src_sys_jen_i,                      // System Source Clock Jitter Enable
-   input rst_ni,                                 // SYS Reset
-   output logic clk_src_sys_o,                   // System Source Clock
-   output logic clk_src_sys_val_o                // System Source Clock Valid
+  input vcmain_pok_i,               // VCMAIN POK @1.1V
+  input clk_src_sys_en_i,           // System Source Clock Enable
+  input clk_src_sys_jen_i,          // System Source Clock Jitter Enable
+  output logic clk_src_sys_o,       // System Source Clock
+  output logic clk_src_sys_val_o    // System Source Clock Valid
 );
 
-logic clk, sys_en, clk_en;
+logic clk, sys_clk_val, rst_n;
 
 // Behavioral Model
+assign rst_n = vcmain_pok_i;
 
 // Clock Oscilator
 sys_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-/*P*/ .SYS_EN_RDLY ( SYS_EN_RDLY ),
-/*P*/ .SYS_EN_FDLY ( SYS_EN_FDLY ),
-/*P*/ .SYS_JEN_RDLY ( SYS_JEN_RDLY ),
-/*P*/ .SYS_JEN_FDLY ( SYS_JEN_FDLY )
+/*P*/ .SYS_EN_RDLY ( SYS_EN_RDLY )
 // synopsys translate_on
+`endif
 ) i_sys_osc (
+/*I*/ .vcmain_pok_i ( vcmain_pok_i ),
 /*I*/ .sys_en_i ( clk_src_sys_en_i ),
 /*I*/ .sys_jen_i ( clk_src_sys_jen_i ),
-/*O*/ .sys_clk_o ( clk ),
-/*O*/ .sys_clk_en_o ( sys_en )
+/*O*/ .sys_clk_o ( clk )
 );
 
-always_ff @( posedge clk, negedge rst_ni ) begin
-   if ( !rst_ni )  clk_en <= 1'b0;
-   else            clk_en <= sys_en;
-end
 
 // Clock & Valid
-assign clk_src_sys_o = clk_en ? ~clk : 1'b0;
-assign clk_src_sys_val_o = clk_en;
+assign clk_src_sys_o = clk;
+
+wire rst_val_n = rst_n && clk_src_sys_en_i;
+
+// 2-stage deassertion
+always_ff @( posedge clk, negedge rst_val_n ) begin
+  if ( !rst_val_n ) begin
+    sys_clk_val       <= 1'b0;
+    clk_src_sys_val_o <= 1'b0;
+  end else begin
+    sys_clk_val       <= 1'b1;
+    clk_src_sys_val_o <= sys_clk_val;
+  end
+end
 
 
 endmodule  // of sys_clk
diff --git a/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv b/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv
index 26810fb..f5bca98 100644
--- a/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv
@@ -2,59 +2,61 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-// 
 // *Name: sys_osc
 // *Module Description: System Clock Oscilator
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 1ps
 
 module sys_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time SYS_EN_RDLY = 10us,
-   parameter time SYS_EN_FDLY = 100ns,
-   parameter time SYS_JEN_RDLY = 80ns,
-   parameter time SYS_JEN_FDLY = 80ns
+  parameter time SYS_EN_RDLY = 5us
 // synopsys translate_on
+`endif
 ) (
-   input sys_en_i,              // System Source Clock Enable
-   input sys_jen_i,             // System Source Clock Jitter Enable
-   output logic sys_clk_o,      // System Clock Output
-   output logic sys_clk_en_o    // System Clock Enable Output
+  input vcmain_pok_i,     // VCMAIN POK @1.1V
+  input sys_en_i,         // System Source Clock Enable
+  input sys_jen_i,        // System Source Clock Jitter Enable
+  output logic sys_clk_o  // System Clock Output
 );
 
+// Behavioral Model
+
+`ifndef VERILATOR
 // synopsys translate_off
 localparam real SYS_CLK_PERIOD = 10000; // 10000ps (100Mhz)
 
-logic init_start, clk;
+logic clk, en_osc, en_osc_re, en_osc_fe;
 shortreal jitter;
 
 initial begin
-   clk  = 1'b0;
-   $display("\nSYS Clock Period: %0dps", SYS_CLK_PERIOD);
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
+  clk  = 1'b0;
+  $display("\nSYS Clock Period: %0dps", SYS_CLK_PERIOD);
 end
 
-wire #(SYS_JEN_RDLY, SYS_JEN_FDLY) sys_jen = sys_jen_i; 
+always @( * ) begin
+  if ( !vcmain_pok_i )                 en_osc_re = 1'b0;  // For Startup
+  else if ( sys_en_i && vcmain_pok_i ) en_osc_re = #(SYS_EN_RDLY) 1'b1;
+  else                                 en_osc_re = 1'b0;
+end
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk or negedge vcmain_pok_i ) begin
+  if ( !vcmain_pok_i ) en_osc_fe <= 1'b0;
+  else                 en_osc_fe <= en_osc_re;
+end
+
+assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
 
 always begin
-   // 0-2000ps is upto +20% Jitter
-   jitter = sys_jen ? $urandom_range(2000, 0) : 0; 
-   #((SYS_CLK_PERIOD+jitter)/2000) clk = ~clk;
+  // 0-2000ps is upto +20% Jitter
+  jitter = sys_jen_i ? $urandom_range(2000, 0) : 0; 
+  #((SYS_CLK_PERIOD+jitter)/2000) clk = ~clk && en_osc;
 end
 
 assign sys_clk_o = clk;
-
-always_ff @( init_start, posedge sys_en_i, negedge sys_en_i ) begin
-    if ( init_start )
-       sys_clk_en_o <= 1'b0;
-    else if ( !init_start && sys_en_i )
-       sys_clk_en_o <= #(SYS_EN_RDLY) sys_en_i;
-    else if ( !init_start && !sys_en_i )                  
-       sys_clk_en_o <= #(SYS_EN_FDLY) sys_en_i;
-end
 // synopsys translate_on
+`endif
 
 
 endmodule  // of sys_osc
diff --git a/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv b/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv
index d799ece..623db97 100644
--- a/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv
@@ -2,58 +2,68 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-//
 // *Name: usb_clk
 // *Module Description: USB Clock
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 10ps
 
 module usb_clk #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time USB_EN_RDLY = 10us,
-   parameter time USB_EN_FDLY = 100ns,
-   parameter time USB_VAL_RDLY = 50ms,
-   parameter time USB_VAL_FDLY = 80ns,
+  parameter time USB_EN_RDLY = 5us,
+  parameter time USB_VAL_RDLY = 50ms,
+  parameter time USB_VAL_FDLY = 80ns
 // synopsys translate_on
-   parameter int UsbCalibWidth = 16
+`endif
 ) (
-   input rst_ni,                             // AST USB Reset
-   input clk_src_usb_en_i,                   // USB Source Clock Enable
-   input usb_ref_pulse_i,                    // USB Reference Pulse
-   input usb_ref_val_i,                      // USB Reference (Pulse) Valid
-   output logic clk_src_usb_o,               // USB Source Clock
-   output logic clk_src_usb_val_o            // USB Source Clock Valid
+  input vcmain_pok_i,              // VCMAIN POK @1.1V
+  input clk_src_usb_en_i,          // USB Source Clock Enable
+  input usb_ref_pulse_i,           // USB Reference Pulse
+  input usb_ref_val_i,             // USB Reference (Pulse) Valid
+  output logic clk_src_usb_o,      // USB Source Clock
+  output logic clk_src_usb_val_o   // USB Source Clock Valid
 );
 
-logic clk, usb_en, clk_en;
+logic clk, usb_clk_val, rst_n;
 
 // Behavioral Model
+assign rst_n = vcmain_pok_i;
 
 // Clock Oscilator
 usb_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
 /*P*/ .USB_EN_RDLY ( USB_EN_RDLY ),
-/*P*/ .USB_EN_FDLY ( USB_EN_FDLY ),
 /*P*/ .USB_VAL_RDLY ( USB_VAL_RDLY ),
 /*P*/ .USB_VAL_FDLY ( USB_VAL_FDLY )
 // synopsys translate_on
+`endif
 ) i_usb_osc (
+/*I*/ .vcmain_pok_i ( vcmain_pok_i ),
 /*I*/ .usb_en_i ( clk_src_usb_en_i ),
 /*I*/ .usb_ref_val_i ( usb_ref_val_i ),
-/*O*/ .usb_clk_o ( clk ),
-/*O*/ .usb_clk_en_o ( usb_en )
+/*O*/ .usb_clk_o ( clk )
 );
 
 
-always_ff @( posedge clk, negedge rst_ni ) begin
-   if ( !rst_ni )  clk_en <= 1'b0;
-   else            clk_en <= usb_en;
-end
-
 // Clock & Valid
-assign clk_src_usb_o = clk_en ? ~clk : 1'b0;
-assign clk_src_usb_val_o = clk_en;
+assign clk_src_usb_o = clk;
+
+// 2-stage assertion
+logic rst_val_n;
+
+assign rst_val_n = rst_n && clk_src_usb_en_i;
+
+always_ff @( posedge clk, negedge rst_val_n ) begin
+  if ( !rst_val_n )  begin
+    usb_clk_val       <= 1'b0;
+    clk_src_usb_val_o <= 1'b0;
+  end
+  else begin
+    usb_clk_val       <= 1'b1;
+    clk_src_usb_val_o <= usb_clk_val;
+  end
+end
 
 
 endmodule  // of usb_clk
diff --git a/hw/top_earlgrey/ip/ast/rtl/usb_osc.sv b/hw/top_earlgrey/ip/ast/rtl/usb_osc.sv
index 929c1be..62c075a 100644
--- a/hw/top_earlgrey/ip/ast/rtl/usb_osc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/usb_osc.sv
@@ -2,61 +2,66 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //############################################################################
-// 
 // *Name: usb_osc
 // *Module Description: USB Clock Oscilator
-//
 //############################################################################
-`timescale 1ns/1ps
+`timescale 1ns / 1ps
 
 module usb_osc #(
+`ifndef VERILATOR
 // synopsys translate_off
-   parameter time USB_EN_RDLY = 10us,
-   parameter time USB_EN_FDLY = 100ns,
-   parameter time USB_VAL_RDLY = 80ns,
-   parameter time USB_VAL_FDLY = 80ns
+  parameter time USB_EN_RDLY = 5us,
+  parameter time USB_VAL_RDLY = 80ns,
+  parameter time USB_VAL_FDLY = 80ns
 // synopsys translate_on
+`endif
 ) (
-   input usb_en_i,              // USB Source Clock Enable
-   input usb_ref_val_i,         // USB Reference Valid
-   output logic usb_clk_o,      // USB Clock Output
-   output logic usb_clk_en_o    // USB Clock Enable Output
+  input vcmain_pok_i,      // VCMAIN POK @1.1V
+  input usb_en_i,          // USB Source Clock Enable
+  input usb_ref_val_i,     // USB Reference Valid
+  output logic usb_clk_o   // USB Clock Output
 );
 
+// Behavioral Model
+
+`ifndef VERILATOR
 // synopsys translate_off
 localparam real USB_CLK_PERIOD = 1000000/48;  // ~20833.33333ps (48Mhz)
-
-logic init_start, clk;
+logic clk, en_osc, en_osc_re, en_osc_fe;
 shortreal drift;
 integer rand32;
 
 initial begin
-   clk = 1'b0;
-   $display("\nUSB Clock Period: %0dps", USB_CLK_PERIOD);
-   rand32 = $urandom_range((9'd416), -(9'd416));  // +/-416ps (+/-2% max)
-   $display("USB Clock Drift: %0dps", rand32);
-   init_start = 1'b1; #1;
-   init_start = 1'b0;
+  clk = 1'b0;
+  $display("\nUSB Clock Period: %0dps", USB_CLK_PERIOD);
+  rand32 = $urandom_range((9'd416), -(9'd416));  // +/-416ps (+/-2% max)
+  $display("USB Clock Drift: %0dps", rand32);
 end
 
+always @( * ) begin
+  if ( !vcmain_pok_i )                 en_osc_re = 1'b0;  // For Startup
+  else if ( usb_en_i && vcmain_pok_i ) en_osc_re = #(USB_EN_RDLY) 1'b1;
+  else                                 en_osc_re = 1'b0;
+end
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk or negedge vcmain_pok_i ) begin
+  if ( !vcmain_pok_i ) en_osc_fe <= 1'b0;
+  else                 en_osc_fe <= en_osc_re;
+end
+
+assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
+
 wire #(USB_VAL_RDLY, USB_VAL_FDLY) ref_val = usb_ref_val_i;
 assign drift = ref_val ? 0 : rand32;
 
 always begin
-   #((USB_CLK_PERIOD+drift)/2000) clk = ~clk;
+  #((USB_CLK_PERIOD + drift)/2000) clk = ~clk && en_osc;
 end
 
 assign usb_clk_o = clk;
-
-always_ff @( init_start, posedge usb_en_i, negedge usb_en_i ) begin
-    if ( init_start )
-       usb_clk_en_o <= 1'b0;
-    else if ( !init_start && usb_en_i )
-       usb_clk_en_o <= #(USB_EN_RDLY) usb_en_i;
-    else if ( !init_start && !usb_en_i )                  
-       usb_clk_en_o <= #(USB_EN_FDLY) usb_en_i;
-end
 // synopsys translate_on
+`endif
 
 
 endmodule  // of usb_osc