tree e7ac513594d8db04fbac303ac9b667bb1f9bc68c
parent 76da21e7b083017f2c0075f22011e927ff4fef82
author Tarik Graba <tarik.graba@telecom-paris.fr> 1615208310 +0100
committer Philipp Wagner <mail@philipp-wagner.com> 1615288109 +0000

[dv/dpi] Fix assignment to SystemVerilog chandle

Section 6.14 of the standard states that assignment to chandle can only
be made from `null` or an other chandle, not from an integer literal.

This patch allows the compilation of the simulation models with modelsim

Signed-off-by: Tarik Graba <tarik.graba@telecom-paris.fr>