diff --git a/hw/ip/prim/rtl/prim_gate_gen.sv b/hw/ip/prim/rtl/prim_gate_gen.sv
index bb7bde2..dac761f 100644
--- a/hw/ip/prim/rtl/prim_gate_gen.sv
+++ b/hw/ip/prim/rtl/prim_gate_gen.sv
@@ -2,48 +2,34 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Simple parameterizable gate generator. Used to fill up the netlist
-// with gates that cannot be optimized away.
+// Simple parameterizable gate generator. Used to fill up the netlist with gates that cannot be
+// optimized away.
 //
-// The module leverages 4bit SBoxes from the PRINCE cipher, and interleaves
-// them with registers, resulting in a split of around 50/50 between logic and
-// sequential cells.
+// The module leverages 4bit SBoxes from the PRINCE cipher, and interleaves them with registers,
+// resulting in a split of around 50/50 between logic and sequential cells.
 //
-// This generator has been tested with 32bit wide data, and produces
-// the following results:
+// This generator has been tested with 32bit wide data, and produces the following results:
 //
-// if valid_i constantly set to 1'b1:
 // -------------+-----------+----------
 // requested GE | actual GE | GE error
 // -------------+-----------+----------
-// 500          |   679     |   179
-// 1000         |   1018    |   18
-// 1500         |   1696    |   196
-// 2500         |   2714    |   214
-// 5000         |   5210    |   210
-// 7500         |   7456    |   -44
-// 10000        |   10015   |   15
-// 15000        |   15191   |   191
-// 25000        |   25228   |   228
-// 50000        |   50485   |   485
+// 500          |  483      |  -17
+// 1000         |  964      |  -36
+// 1500         |  1447     |  -53
+// 2500         |  2892     |  392
+// 5000         |  5299     |  299
+// 7500         |  8030     |  530
+// 10000        |  10393    |  393
+// 15000        |  15575    |  575
+// 25000        |  26422    |  1422
+// 50000        |  52859    |  2859
+// 100000       |  105270   |  5270
 //
-// otherwise, with clock gating enabled:
-// -------------+-----------+----------
-// requested GE | actual GE | GE error
-// -------------+-----------+----------
-// 500          |   696     |   196
-// 1000         |   1043    |   43
-// 1500         |   1737    |   237
-// 2500         |   2779    |   279
-// 5000         |   5340    |   340
-// 7500         |   7634    |   134
-// 10000        |   10284   |   284
-// 15000        |   15585   |   585
-// 25000        |   25855   |   855
-// 50000        |   51732   |   1732
+// Note that the generator is not very accurate for smaller gate counts due to the generate loop
+// granularity. Hence, do not use for fever than 500 GE.
 //
-// Note that the generator is not very accurate for smaller gate counts due
-// to the generate loop granularity. Hence, do not use for fever than 500 GE.
+// If valid_i constantly set to 1'b1, the gate generator produces around 2.5% smaller designs for
+// the configurations listed in the table above.
 
 `include "prim_assert.sv"
 module prim_gate_gen #(
@@ -66,7 +52,7 @@
   // technology specific tuning, do not modify.
   // an inner round is comprised of a 2bit rotation, followed by a 4bit SBox Layer.
   localparam int NumInnerRounds = 2;
-  localparam int GatesPerRound  = DataWidth * 10;
+  localparam int GatesPerRound  = DataWidth * 14;
   // an outer round consists of NumInnerRounds, followed by a register.
   localparam int NumOuterRounds = (NumGates + GatesPerRound / 2) / GatesPerRound;