diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index d81559c..4a29e76 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -236,10 +236,10 @@
       fusesoc --cores-root=. \
         run --flag=fileset_top --target=sim --setup --build \
         --build-root="$OBJ_DIR/hw" \
-        lowrisc:systems:chip_earlgrey_verilator \
+        lowrisc:dv:chip_verilator_sim \
         --verilator_options="--threads 4"
 
-      cp "$OBJ_DIR/hw/sim-verilator/Vchip_earlgrey_verilator_tb" \
+      cp "$OBJ_DIR/hw/sim-verilator/Vchip_sim_tb" \
         "$BIN_DIR/hw/top_earlgrey/Vchip_earlgrey_verilator"
     displayName: Build simulation with Verilator
   - template: ci/upload-artifacts-template.yml
diff --git a/doc/ug/getting_started_verilator.md b/doc/ug/getting_started_verilator.md
index fb1240b..b2bfab4 100644
--- a/doc/ug/getting_started_verilator.md
+++ b/doc/ug/getting_started_verilator.md
@@ -19,7 +19,7 @@
 
 ```console
 $ cd $REPO_TOP
-$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:systems:chip_earlgrey_verilator
+$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:dv:chip_verilator_sim
 ```
 The fsel_top flag used above is specific to the OpenTitan project to select the correct fileset.
 
@@ -46,7 +46,7 @@
 
 ```console
 $ cd $REPO_TOP
-$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
+$ build/lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb \
   --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
   --meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
   --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
@@ -103,10 +103,10 @@
 A full command-line invocation of the simulation could then look like that:
 ```console
 $ cd $REPO_TOP
-$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
+$ build/lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb \
   --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
   --meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
-  --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
+  --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
   +UARTDPI_LOG_uart0=-
 ```
 
@@ -195,10 +195,10 @@
 
 ```console
 $ cd $REPO_TOP
-$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
+$ build/lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb \
   --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
   --meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
-  --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
+  --meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
   --trace
 $ gtkwave sim.fst
 ```
diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core
index d87a1bc..81f3b4d 100644
--- a/hw/top_earlgrey/chip_earlgrey_verilator.core
+++ b/hw/top_earlgrey/chip_earlgrey_verilator.core
@@ -9,118 +9,17 @@
     depend:
       - lowrisc:systems:top_earlgrey:0.1
       - lowrisc:systems:top_earlgrey_pkg
-      - lowrisc:dv_dpi:uartdpi
-      - lowrisc:dv_dpi:gpiodpi
-      - lowrisc:dv_dpi:jtagdpi
-      - lowrisc:dv_dpi:dmidpi
-      - lowrisc:dv_dpi:spidpi
-      - lowrisc:dv_dpi:usbdpi
-      - lowrisc:dv_verilator:memutil_verilator
-      - lowrisc:dv_verilator:simutil_verilator
       - lowrisc:ibex:ibex_tracer
-      - lowrisc:dv:sim_sram
-      - lowrisc:dv:sw_test_status
-      - lowrisc:dv:dv_test_status
       - lowrisc:prim:clock_div
 
     files:
-      - dv/tb/chip_earlgrey_verilator_tb.sv: { file_type: systemVerilogSource }
       - rtl/chip_earlgrey_verilator.sv: { file_type: systemVerilogSource }
-      - chip_earlgrey_verilator.cc: { file_type: cppSource }
-
-parameters:
-  # For value definition, please see ip/prim/rtl/prim_pkg.sv
-  PRIM_DEFAULT_IMPL:
-    datatype: str
-    paramtype: vlogdefine
-    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
-  RVFI:
-    datatype: bool
-    paramtype: vlogdefine
-    description: Enable the RISC-V Verification Interface and instruction tracing
-  VERILATOR_MEM_BASE:
-    datatype: int
-    paramtype: vlogdefine
-    description: Main memory mem base.
-  VERILATOR_TEST_STATUS_ADDR:
-    datatype: int
-    paramtype: vlogdefine
-    description: Verilator specific address to write to, to report the test status. This value should be at a word offset in the unmapped address space.
-  flashinit:
-    datatype : file
-    description : Application to load into Flash (in Verilog hex format)
-    paramtype : cmdlinearg
-  rominit:
-    datatype : file
-    description : Application to load into Boot ROM (in Verilog hex format)
-    paramtype : cmdlinearg
-  otpinit:
-    datatype : file
-    description : Image to load into the OTP (in Verilog hex format)
-    paramtype : cmdlinearg
-  DMIDirectTAP:
-    datatype: bool
-    paramtype: vlogdefine
-    default: true
-    description: Replace JTAG TAP with an OpenOCD direct connection
-  UART_LOG_uart0:
-    datatype: string
-    paramtype: plusarg
-    description: Write a log of output from uart0 to the given log file. Use "-" for stdout.
-  RV_CORE_IBEX_SIM_SRAM:
-    datatype: bool
-    paramtype: vlogdefine
-    description: Disconnect the TL data output of rv_core_ibex so that we can attach the simulation SRAM.
 
 targets:
   default: &default_target
     filesets:
       - files_sim_verilator
-    toplevel: chip_earlgrey_verilator_tb
-
-  sim:
-    parameters:
-      - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
-      - RVFI=true
-      - VERILATOR_MEM_BASE=0x10000000
-      - VERILATOR_TEST_STATUS_ADDR=0x30000000
-      - flashinit
-      - rominit
-      - otpinit
-      - DMIDirectTAP
-      # Always build OTBN with model and RTL. Switch between the two at runtime
-      # by passing "+OTBN_USE_MODEL=1" to the simulation.
-      - OTBN_BUILD_MODEL=true
-      - RV_CORE_IBEX_SIM_SRAM=true
-    default_tool: verilator
-    filesets:
-      - files_sim_verilator
-    toplevel: chip_earlgrey_verilator_tb
-    tools:
-      verilator:
-        mode: cc
-        verilator_options:
-          # Disabling tracing reduces compile times but doesn't have a
-          # huge influence on runtime performance.
-          - '--trace'
-          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
-          # Remove FST options for VCD trace
-          - '--trace-structs'
-          - '--trace-params'
-          - '--trace-max-array 1024'
-          - '--unroll-count 512'
-          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_earlgrey_verilator_tb"'
-          - '-LDFLAGS "-pthread -lutil -lelf"'
-          - '-Wall'
-          # Execute simulation with four threads by default, which works best
-          # with four physical CPU cores.
-          # Users can override this setting by appending e.g.
-          # --verilator_options '--threads 2'
-          # to the end of the fusesoc invocation when compiling the simulation.
-          - '--threads 4'
-          # XXX: Cleanup all warnings and remove this option
-          # (or make it more fine-grained at least)
-          - '-Wno-fatal'
+    toplevel: chip_earlgrey_verilator
 
   lint:
     <<: *default_target
diff --git a/hw/top_earlgrey/dv/verilator/chip_sim.core b/hw/top_earlgrey/dv/verilator/chip_sim.core
new file mode 100644
index 0000000..1dc9e1c
--- /dev/null
+++ b/hw/top_earlgrey/dv/verilator/chip_sim.core
@@ -0,0 +1,127 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:chip_verilator_sim:0.1"
+description: "Earl Grey toplevel for simulation with Verilator"
+filesets:
+  files_sim_verilator:
+    depend:
+      - lowrisc:dv_dpi:uartdpi
+      - lowrisc:dv_dpi:gpiodpi
+      - lowrisc:dv_dpi:jtagdpi
+      - lowrisc:dv_dpi:dmidpi
+      - lowrisc:dv_dpi:spidpi
+      - lowrisc:dv_dpi:usbdpi
+      - lowrisc:dv_verilator:memutil_verilator
+      - lowrisc:dv_verilator:simutil_verilator
+      - lowrisc:dv:sim_sram
+      - lowrisc:dv:sw_test_status
+      - lowrisc:dv:dv_test_status
+      - lowrisc:systems:chip_earlgrey_verilator
+    files:
+      - chip_sim_tb.sv: { file_type: systemVerilogSource }
+      - chip_sim_tb.cc: { file_type: cppSource }
+
+parameters:
+  # For value definition, please see ip/prim/rtl/prim_pkg.sv
+  PRIM_DEFAULT_IMPL:
+    datatype: str
+    paramtype: vlogdefine
+    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
+  RVFI:
+    datatype: bool
+    paramtype: vlogdefine
+    description: Enable the RISC-V Verification Interface and instruction tracing
+  VERILATOR_MEM_BASE:
+    datatype: int
+    paramtype: vlogdefine
+    description: Main memory mem base.
+  VERILATOR_TEST_STATUS_ADDR:
+    datatype: int
+    paramtype: vlogdefine
+    description: Verilator specific address to write to, to report the test status. This value should be at a word offset in the unmapped address space.
+  flashinit:
+    datatype : file
+    description : Application to load into Flash (in Verilog hex format)
+    paramtype : cmdlinearg
+  rominit:
+    datatype : file
+    description : Application to load into Boot ROM (in Verilog hex format)
+    paramtype : cmdlinearg
+  otpinit:
+    datatype : file
+    description : Image to load into the OTP (in Verilog hex format)
+    paramtype : cmdlinearg
+  DMIDirectTAP:
+    datatype: bool
+    paramtype: vlogdefine
+    default: true
+    description: Replace JTAG TAP with an OpenOCD direct connection
+  UART_LOG_uart0:
+    datatype: string
+    paramtype: plusarg
+    description: Write a log of output from uart0 to the given log file. Use "-" for stdout.
+  RV_CORE_IBEX_SIM_SRAM:
+    datatype: bool
+    paramtype: vlogdefine
+    description: Disconnect the TL data output of rv_core_ibex so that we can attach the simulation SRAM.
+
+targets:
+  default: &default_target
+    filesets:
+      - files_sim_verilator
+    toplevel: chip_sim_tb
+
+  sim:
+    parameters:
+      - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
+      - RVFI=true
+      - VERILATOR_MEM_BASE=0x10000000
+      - VERILATOR_TEST_STATUS_ADDR=0x30000000
+      - flashinit
+      - rominit
+      - otpinit
+      - DMIDirectTAP
+      # Always build OTBN with model and RTL. Switch between the two at runtime
+      # by passing "+OTBN_USE_MODEL=1" to the simulation.
+      - OTBN_BUILD_MODEL=true
+      - RV_CORE_IBEX_SIM_SRAM=true
+    default_tool: verilator
+    filesets:
+      - files_sim_verilator
+    toplevel: chip_sim_tb
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+          # Disabling tracing reduces compile times but doesn't have a
+          # huge influence on runtime performance.
+          - '--trace'
+          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
+          # Remove FST options for VCD trace
+          - '--trace-structs'
+          - '--trace-params'
+          - '--trace-max-array 1024'
+          - '--unroll-count 512'
+          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_sim_tb"'
+          - '-LDFLAGS "-pthread -lutil -lelf"'
+          - '-Wall'
+          # Execute simulation with four threads by default, which works best
+          # with four physical CPU cores.
+          # Users can override this setting by appending e.g.
+          # --verilator_options '--threads 2'
+          # to the end of the fusesoc invocation when compiling the simulation.
+          - '--threads 4'
+          # XXX: Cleanup all warnings and remove this option
+          # (or make it more fine-grained at least)
+          - '-Wno-fatal'
+
+  lint:
+    <<: *default_target
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"
diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.cc b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc
similarity index 94%
rename from hw/top_earlgrey/chip_earlgrey_verilator.cc
rename to hw/top_earlgrey/dv/verilator/chip_sim_tb.cc
index e4486c4..16df032 100644
--- a/hw/top_earlgrey/chip_earlgrey_verilator.cc
+++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc
@@ -10,13 +10,13 @@
 #include "verilator_sim_ctrl.h"
 
 int main(int argc, char **argv) {
-  chip_earlgrey_verilator_tb top;
+  chip_sim_tb top;
   VerilatorMemUtil memutil;
   VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
   simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
                  VerilatorSimCtrlFlags::ResetPolarityNegative);
 
-  std::string top_scope("TOP.chip_earlgrey_verilator_tb.u_dut.top_earlgrey");
+  std::string top_scope("TOP.chip_sim_tb.u_dut.top_earlgrey");
   std::string ram1p_adv_scope(
       "u_prim_ram_1p_adv.u_mem."
       "gen_generic.u_impl_generic");
diff --git a/hw/top_earlgrey/dv/tb/chip_earlgrey_verilator_tb.sv b/hw/top_earlgrey/dv/verilator/chip_sim_tb.sv
similarity index 98%
rename from hw/top_earlgrey/dv/tb/chip_earlgrey_verilator_tb.sv
rename to hw/top_earlgrey/dv/verilator/chip_sim_tb.sv
index 234cc42..d92927a 100644
--- a/hw/top_earlgrey/dv/tb/chip_earlgrey_verilator_tb.sv
+++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module chip_earlgrey_verilator_tb (
+module chip_sim_tb (
   // Clock and Reset
   input clk_i,
   input rst_ni
@@ -207,4 +207,4 @@
   `undef SIM_SRAM_IF
 
 
-endmodule // chip_earlgrey_verilator_tb
+endmodule // chip_sim_tb
diff --git a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson
similarity index 100%
rename from hw/top_earlgrey/dv/verilator_sim_cfg.hjson
rename to hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson