)]}'
{
  "commit": "b0005d08060d8f5b0e8aee32ef3e57b7ba8f7629",
  "tree": "6bdd69b7eac95ee5b28d906350b1f87031cb9fc4",
  "parents": [
    "456e53d6f541a3fd3dcc1cdc310c9c5bf8f789b4"
  ],
  "author": {
    "name": "Pirmin Vogel",
    "email": "vogelpi@lowrisc.org",
    "time": "Tue Sep 29 17:31:55 2020 +0200"
  },
  "committer": {
    "name": "Pirmin Vogel",
    "email": "vogelpi@lowrisc.org",
    "time": "Thu Oct 01 10:04:11 2020 +0200"
  },
  "message": "[fpga] Fix clock constraint\n\nFor some reason, Vivado moves one of the clock dividers inside clkmgr\nto the outside of clkmgr. As a result, the path used to find the\nrelevant cell is wrong and the divided clock cannot be properly\nconstrained. This leads to a bunch of critical warnings.\n\nThis commit fixes the path such that the clock can be constrained.\n\nSigned-off-by: Pirmin Vogel \u003cvogelpi@lowrisc.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "973434dfee80a298895860e3f1daeb2d25f6c43c",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/data/clocks.xdc",
      "new_id": "c5d6cdc74d7a2bc95d49ffd5c7bbbb65d8d2a090",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/data/clocks.xdc"
    }
  ]
}