diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index aacc643..71c69b1 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -24,7 +24,8 @@
   input        otp_flash_t otp_i,
   input        lc_flash_req_t lc_i,
   output       lc_flash_rsp_t lc_o,
-  input        pwrmgr_flash_t pwrmgr_i,
+  input        pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
+  output       pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
   input        edn_entropy_t edn_i,
 
   // Interrupts
@@ -269,7 +270,8 @@
     .clk_i,
     .rst_ni,
 
-    .init_i(pwrmgr_i.init),
+    .init_i(pwrmgr_i.flash_init),
+    .init_done_o(pwrmgr_o.flash_done),
     .provision_en_i(lc_i.provision_en),
 
     // interface to ctrl arb control ports
@@ -385,9 +387,6 @@
     .flash_error_i  (flash_mp_error)
   );
 
-  // Read FIFO
-
-
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       adapter_rvalid <= 1'b0;
@@ -636,6 +635,23 @@
   assign flash_rd_data = flash_i.rd_data;
   assign flash_phy_busy = flash_i.init_busy;
 
+  // Interface to pwrmgr
+  // flash is not idle as long as there is a stateful operation ongoing
+  logic flash_idle_d;
+  assign flash_idle_d = ~(flash_o.req &
+                          (flash_o.prog | flash_o.pg_erase | flash_o.bk_erase));
+
+  prim_flop #(
+    .Width(1),
+    .ResetValue(1'b1)
+  ) u_reg_idle (
+    .clk_i,
+    .rst_ni,
+    .d_i(flash_idle_d),
+    .q_o(pwrmgr_o.flash_idle)
+  );
+
+
   // Interrupts
   // Generate edge triggered signals for sources that are level
   logic [3:0] intr_src;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv
index 181588d..f14534c 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv
@@ -60,7 +60,7 @@
   output logic prog_fifo_wvalid_o,
   input logic prog_fifo_wready_i,
 
-  // flash phy initilization ongoing
+  // flash phy initialization ongoing
   input logic flash_phy_busy_i,
 
   // clear fifo contents
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
index fcf14f0..cd32191 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
@@ -11,6 +11,7 @@
 
   // initialization command
   input init_i,
+  output logic init_done_o,
 
   // only access seeds when provisioned
   input provision_en_i,
@@ -81,6 +82,7 @@
   } state_e;
 
   state_e state_q, state_d;
+  logic init_done_d;
   logic validate_q, validate_d;
   logic [SeedCntWidth-1:0] seed_cnt_q;
   logic [CntWidth-1:0] addr_cnt_q;
@@ -97,9 +99,11 @@
     if (!rst_ni) begin
       state_q <= StIdle;
       validate_q <= 1'b0;
+      init_done_o <= 1'b0;
     end else begin
       state_q <= state_d;
       validate_q <= validate_d;
+      init_done_o <= init_done_d;
     end
   end
 
@@ -175,6 +179,19 @@
   // rma phase is erase unless we are validating
   assign op = seed_phase || validate_q ? FlashOpRead : FlashOpErase;
 
+  // synchronize inputs
+  logic init_q;
+
+  prim_flop_2sync #(
+    .Width(1),
+    .ResetValue(0)
+  ) u_sync_flash_init (
+    .clk_i,
+    .rst_ni,
+    .d_i(init_i),
+    .q_o(init_q)
+  );
+
   always_comb begin
 
     // phases of the hardware interface
@@ -202,15 +219,20 @@
     state_d = state_q;
     validate_d = validate_q;
 
+    // init status
+    // flash_ctrl handles its own arbitration between hardware and software.
+    // So once the init kicks off it is safe to ack.  The done signal is still
+    // to give a chance to hold off further power up progression in the future
+    // if required.
+    init_done_d = 1'b1;
+
     unique case (state_q)
 
       StIdle: begin
+        init_done_d = 1'b0;
         phase = PhaseSeed;
-        // TBD: provision_en is only a "good" value after otp initilization
-        // Need to qualify this statement with some notion that otp init has
-        // finished.  Since power manager will kick off otp init, it should
-        // also be able to kick off flash_init
-        if (init_i) begin
+        // provision_en is only a "good" value after otp/lc initialization
+        if (init_q) begin
           // if provisioning is not enabled, do not read seeds and skip directly
           // to wait state.
           state_d = provision_en_i ? StReadSeeds : StWait;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index e7f23e1..336f9b6 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -282,11 +282,6 @@
     logic [BusWidth-1:0] rma_ack_token;
   } lc_flash_rsp_t;
 
-  // pwrmgr to flash_ctrl
-  typedef struct packed {
-    logic init;
-  } pwrmgr_flash_t;
-
   // place holder for interface to EDN, replace with real one later
   typedef struct packed {
     logic valid;
@@ -309,10 +304,6 @@
     provision_en: 1'b1
   };
 
-  parameter pwrmgr_flash_t PWRMGR_FLASH_DEFAULT = '{
-    init: 1'b1
-  };
-
   parameter edn_entropy_t EDN_ENTROPY_DEFAULT = '{
     valid: 1'b1,
     entropy: '0