diff --git a/util/fpvgen.py b/util/fpvgen.py
index 91eb061..f2811bf 100755
--- a/util/fpvgen.py
+++ b/util/fpvgen.py
@@ -101,8 +101,8 @@
         dut.deps += ["lowrisc:ip:" + parentpath.stem]
 
     # define template files to iterate over
-    template_files = [(Path(__file__).parent.joinpath("fpvgen/fpv.sv.tpl"),                  \
-                       outpath.joinpath("tb").joinpath(mod_path.stem + "_fpv.sv")),          \
+    template_files = [(Path(__file__).parent.joinpath("fpvgen/tb.sv.tpl"),                  \
+                       outpath.joinpath("tb").joinpath(mod_path.stem + "_tb.sv")),          \
                       (Path(__file__).parent.joinpath("fpvgen/bind_fpv.sv.tpl"),             \
                         outpath.joinpath("tb").joinpath(mod_path.stem + "_bind_fpv.sv")),    \
                       (Path(__file__).parent.joinpath("fpvgen/assert_fpv.sv.tpl"),           \
diff --git a/util/fpvgen/fusesoc.core.tpl b/util/fpvgen/fusesoc.core.tpl
index 10afa50..75f4c3a 100644
--- a/util/fpvgen/fusesoc.core.tpl
+++ b/util/fpvgen/fusesoc.core.tpl
@@ -17,7 +17,7 @@
     files:
       - vip/${dut.name}_assert_fpv.sv
       - tb/${dut.name}_bind_fpv.sv
-      - tb/${dut.name}_fpv.sv
+      - tb/${dut.name}_tb.sv
     file_type: systemVerilogSource
 
 % if dut.is_cip:
@@ -40,7 +40,7 @@
     generate:
       - csr_assert_gen
 % endif
-    toplevel: ${dut.name}_fpv
+    toplevel: ${dut.name}_tb
 
   formal:
     <<: *default_target
diff --git a/util/fpvgen/fpv.sv.tpl b/util/fpvgen/tb.sv.tpl
similarity index 91%
rename from util/fpvgen/fpv.sv.tpl
rename to util/fpvgen/tb.sv.tpl
index af7c621..0778e01 100644
--- a/util/fpvgen/fpv.sv.tpl
+++ b/util/fpvgen/tb.sv.tpl
@@ -6,7 +6,7 @@
 // Intended to be used with a formal tool.
 
 % if len(dut.pkgs) > 0:
-module ${dut.name}_fpv
+module ${dut.name}_tb
 % for pkg in dut.pkgs:
   import ${pkg};
 % endfor
@@ -17,9 +17,9 @@
 % endif
 % else:
 % if dut.params:
-module ${dut.name}_fpv #(
+module ${dut.name}_tb #(
 % else:
-module ${dut.name}_fpv (
+module ${dut.name}_tb (
 % endif
 % endif
 % if dut.params:
@@ -49,4 +49,4 @@
   );
 
 
-endmodule : ${dut.name}_fpv
+endmodule : ${dut.name}_tb