diff --git a/hw/dv/data/sim.mk b/hw/dv/data/sim.mk
index 0d69912..8b8fe30 100644
--- a/hw/dv/data/sim.mk
+++ b/hw/dv/data/sim.mk
@@ -63,7 +63,15 @@
 	cp ${sw_build_dir}/build-out/sw/device/boot_rom/boot_rom_${sw_build_device}.32.vmem \
 		${run_dir}/rom.32.vmem
 
-ifeq (${sw_test_is_prebuilt},)
+ifeq (${sw_test_is_prebuilt},1)
+	# Copy over the sw test image and related sources to the run_dir.
+	cp ${proj_root}/${sw_test}.32.vmem ${run_dir}/sw.32.vmem
+	# Optionally, assume that ${sw_test}_logs.txt exists and copy over to the run_dir.
+	# Ignore copy error if it actually doesn't exist. Likewise for ${sw_test}_rodata.txt.
+	-cp ${proj_root}/${sw_test}_logs.txt ${run_dir}/sw_logs.txt
+	-cp ${proj_root}/${sw_test}_rodata.txt ${run_dir}/sw_rodata.txt
+
+else
 	# Compile the sw test code and generate the image.
 	${LOCK_SW_BUILD} "ninja -C ${sw_build_dir}/build-out \
 		${sw_test}_export_${sw_build_device}"
@@ -75,12 +83,7 @@
 	# Copy over the sw test image to the run_dir.
 	cp ${sw_build_dir}/build-out/${sw_test}_${sw_build_device}.32.vmem \
 		${run_dir}/sw.32.vmem
-else
-	# Copy over the sw test image and related sources to the run_dir.
-	cp ${proj_root}/${sw_test}.32.vmem ${run_dir}/sw.32.vmem
-	# Optionally, copy ${sw_test}_logs.txt over to the run_dir if it exists.
-	-cp ${proj_root}/${sw_test}_logs.txt ${run_dir}/sw_logs.txt
-	-cp ${proj_root}/${sw_test}_rodata.txt ${run_dir}/sw_rodata.txt
+
 endif
 
 endif
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index f71b6c7..c4effc5 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -129,6 +129,17 @@
       run_opts: ["+en_uart_logger=1",
                  "+sw_test_timeout_ns=22000000"]
     }
+    {
+      name: chip_opentitan_tock
+      uvm_test_seq: chip_sw_base_vseq
+      sw_test: sw/device/tock/prebuilt/opentitan
+      sw_test_is_prebuilt: 1
+      run_opts: ["+en_uart_logger=1",
+                 // TODO #2241: tock reads an uninitialized part of stack, which causes
+                 // assertion errors to be thrown. This is a temporary workaround.
+                 "+initialize_ram=1",
+                 "+sw_test_timeout_ns=50000000"]
+    }
 
     // The test below is added in the included tl_access_tests.hjson.
     // We just need to append the stub_cpu run mode to it.
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index b4302e3..3ed6a44 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -7,7 +7,9 @@
   // Testbench settings
   bit                 stub_cpu;
   bit                 en_uart_logger;
+  int                 uart_baud_rate = uart_agent_pkg::BaudRate2Mbps;
   bit                 use_gpio_for_sw_test_status;
+  bit                 initialize_ram;
 
   // chip top interfaces
   virtual clk_rst_if  usb_clk_rst_vif;
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
index 7d243be..ffdfe5b 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -18,10 +18,9 @@
 
   // Backdoor load the sw test image, setup UART, logger and test status interfaces.
   virtual task cpu_init();
-    // Set 'default' UART baud rate of 2Mbps - this is also programmed by the C test.
     // TODO: Fixing this for now - need to find a way to pass this on to the SW test.
     cfg.m_uart_agent_cfg.set_parity(1'b0, 1'b0);
-    cfg.m_uart_agent_cfg.set_baud_rate(BaudRate2Mbps);
+    cfg.m_uart_agent_cfg.set_baud_rate(cfg.uart_baud_rate);
 
     // initialize the sw logger interface
     foreach (cfg.sw_types[i]) begin
@@ -33,7 +32,8 @@
     // initialize the sw test status
     cfg.sw_test_status_vif.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
 
-    // Initialize the flash to all 1s.
+    // Initialize the RAM to 0s and flash to all 1s.
+    if (cfg.initialize_ram) cfg.mem_bkdr_vifs[Ram].clear_mem();
     cfg.mem_bkdr_vifs[FlashBank0].set_mem();
     cfg.mem_bkdr_vifs[FlashBank1].set_mem();
 
diff --git a/hw/top_earlgrey/dv/tests/chip_base_test.sv b/hw/top_earlgrey/dv/tests/chip_base_test.sv
index 0a8c9b4..b644fee 100644
--- a/hw/top_earlgrey/dv/tests/chip_base_test.sv
+++ b/hw/top_earlgrey/dv/tests/chip_base_test.sv
@@ -9,28 +9,34 @@
   `uvm_component_utils(chip_base_test)
   `uvm_component_new
 
-  // the base class dv_base_test creates the following instances:
+  // The base class dv_base_test creates the following instances:
   // chip_env_cfg: cfg
   // chip_env:     env
 
-  // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
-  // the run_phase; as such, nothing more needs to be done
+  // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
+  // the run_phase; as such, nothing more needs to be done.
 
   virtual function void build_phase(uvm_phase phase);
     super.build_phase(phase);
-    // knob to en/dis stubbing cpu (disabled by default)
+    // Knob to en/dis stubbing cpu (disabled by default).
     void'($value$plusargs("stub_cpu=%0b", cfg.stub_cpu));
     // Set tl_agent's is_active bit based on the retrieved stub_cpu value.
     cfg.m_tl_agent_cfg.is_active = cfg.stub_cpu;
 
-    // knob to enable logging via uart
+    // Knob to set the UART baud rate (set to 2M by default).
+    void'($value$plusargs("uart_baud_rate=%0d", cfg.uart_baud_rate));
+
+    // Knob to enable logging over UART (disabled by default).
     void'($value$plusargs("en_uart_logger=%0b", cfg.en_uart_logger));
     cfg.m_uart_agent_cfg.en_logger = cfg.en_uart_logger;
     cfg.m_uart_agent_cfg.logger_msg_id  = "SW_LOGS";
 
-    // Set the sw_test_timeout_ns knob from plusarg if available.
+    // Knob to set the sw_test_timeout_ns (set to 5ms by default).
     void'($value$plusargs("sw_test_timeout_ns=%0d", cfg.sw_test_timeout_ns));
 
+    // Knob to pre-initialize RAM to 0s (disabled by default).
+    void'($value$plusargs("initialize_ram=%0b", cfg.initialize_ram));
+
     // override tl_seq_item to apply constraint on source_id
     tl_seq_item::type_id::set_type_override(chip_tl_seq_item::get_type());
   endfunction : build_phase