diff --git a/hw/ip/otbn/data/otbn_testplan.hjson b/hw/ip/otbn/data/otbn_testplan.hjson
index 2e77b4d..16b5b6b 100644
--- a/hw/ip/otbn/data/otbn_testplan.hjson
+++ b/hw/ip/otbn/data/otbn_testplan.hjson
@@ -10,6 +10,7 @@
                      "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                      "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
                      "hw/dv/tools/dvsim/testplans/passthru_mem_intg_testplan.hjson",
+                     "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
                      "otbn_sec_cm_testplan.hjson"]
   testpoints: [
     {
diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv b/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv
index ede17c8..5b1962d 100644
--- a/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv
+++ b/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv
@@ -84,8 +84,9 @@
     // Tell the CIP base code how many interrupts we have (defaults to zero)
     num_interrupts = 1;
 
-    // Tell the CIP base code what alert we generate if we see a TL fault.
+    // Tell the CIP base code what alert we generate if we see a TL or sec cm fault.
     tl_intg_alert_name = "fatal";
+    sec_cm_alert_name = "fatal";
 
     model_agent_cfg  = otbn_model_agent_cfg  ::type_id::create("model_agent_cfg");
     keymgr_sideload_agent_cfg = otbn_sideload_agent_cfg::type_id::create(
diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv b/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv
index 53c5e5e..d6864f9 100644
--- a/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv
+++ b/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv
@@ -18,6 +18,7 @@
   import prim_util_pkg::vbits;
   import prim_mubi_pkg::*;
   import key_sideload_agent_pkg::*;
+  import sec_cm_pkg::*;
 
   // autogenerated RAL model
   import otbn_reg_pkg::*;
diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv
index 4dbfc65..c7dd4a5 100644
--- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv
+++ b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv
@@ -107,4 +107,21 @@
 
   endfunction
 
+  virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy);
+    super.check_sec_cm_fi_resp(if_proxy);
+    csr_utils_pkg::csr_rd_check(.ptr(ral.fatal_alert_cause.bad_internal_state), .compare_value(1));
+    csr_utils_pkg::csr_rd_check(.ptr(ral.status), .compare_value('hFF));
+  endtask : check_sec_cm_fi_resp
+
+  virtual function void sec_cm_fi_ctrl_svas(sec_cm_base_if_proxy if_proxy, bit enable);
+    if (enable) begin
+      $asserton(0, "tb.dut.u_otbn_core.u_otbn_controller.ControllerStateValid");
+      $asserton(0, "tb.MatchingStatus_A");
+    end else begin
+      $assertoff(0, "tb.dut.u_otbn_core.u_otbn_controller.ControllerStateValid");
+      $assertoff(0, "tb.MatchingStatus_A");
+    end
+  endfunction: sec_cm_fi_ctrl_svas
+
+
 endclass
diff --git a/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson b/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson
index 11fc598..b6a4c4b 100644
--- a/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson
+++ b/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson
@@ -42,7 +42,8 @@
       "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
       "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
       "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
-      "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"
+      "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
+      "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
       "{proj_root}/hw/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson"
   ]
 
@@ -53,7 +54,7 @@
                    "{tool}_memutil_dpi_scrambled_build_opts"]
 
   // Add additional tops for simulation.
-  sim_tops: ["otbn_bind"]
+  sim_tops: ["otbn_bind", "sec_cm_prim_sparse_fsm_flop_bind"]
 
   // Default iterations for all tests - each test entry can override this.
   reseed: 50