tree 3509c35528b7c280e601a32fa92c97bb61afbb0a
parent 6442e7ed8775f563d8568b331ddf78dad20d1611
author Rupert Swarbrick <rswarbrick@lowrisc.org> 1614266360 +0000
committer Rupert Swarbrick <rswarbrick@gmail.com> 1614435290 +0000

[otbn] Remove enable_i input from otbn_core_model

The previous code had a race in the initial blocks when used in
otbn.sv. The obvious way to fix this in the SystemVerilog code would
be to call otbn_model_init() just before we first call
otbn_model_step. Unfortunately, you can't do that (for Verilator, at
least) because that ends up mixing blocking and non-blocking
assignments.

Rather than think hard about how to do this properly in Verilog, we
can just put in a simple layer of indirection in the C++ and only
start the subprocess when we see start_i for the first time.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>