diff --git a/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
index 38047bb..ba0eb8e 100644
--- a/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
+++ b/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
@@ -52,6 +52,9 @@
   // Default iterations for all tests - each test entry can override this.
   reseed: 50
 
+  // Add default run opt
+  run_opts: ["+flash_rand_delay_en=1"]
+
   // Default UVM test and seq class name.
   uvm_test: flash_ctrl_base_test
   uvm_test_seq: flash_ctrl_base_vseq
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv b/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv
index d61a9a6..b6e0d8b 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv
@@ -53,9 +53,19 @@
     int EraseLatency  = 200;
 
     initial begin
+      bit flash_rand_delay_en;
+      void'($value$plusargs("flash_rand_delay_en=%0b", flash_rand_delay_en));
+
+      if (flash_rand_delay_en) begin
+        ReadLatency  = $urandom_range(1, 5);
+        ProgLatency  = $urandom_range(25, 50);
+        EraseLatency = $urandom_range(125, 200);
+      end
       void'($value$plusargs("flash_read_latency=%0d", ReadLatency));
       void'($value$plusargs("flash_program_latency=%0d", ProgLatency));
       void'($value$plusargs("flash_erase_latency=%0d", EraseLatency));
+      $display("%m: ReadLatency:%0d ProgLatency:%0d EraseLatency:%0d",
+               ReadLatency, ProgLatency, EraseLatency);
     end
   `endif