diff --git a/hw/formal/tools/jaspergold/conn.tcl b/hw/formal/tools/jaspergold/conn.tcl
index e399575..ca77944 100644
--- a/hw/formal/tools/jaspergold/conn.tcl
+++ b/hw/formal/tools/jaspergold/conn.tcl
@@ -35,7 +35,7 @@
   clock clk_io_i
   clock clk_usb_i
   clock clk_aon_i
-  reset -expr {rst_ni}
+  reset -expr {por_n_i}
 }
 
 #-------------------------------------------------------------------------
diff --git a/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv b/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
index ae63bc4..463f353 100644
--- a/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
+++ b/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
@@ -2,6 +2,10 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
+# Run these checks with
+#  cd hw/top_earlgrey/formal
+#  ../../../util/dvsim/dvsim.py chip_conn_cfg.hjson
+#
 # TODO: use chip_earlgrey_asic once the ast compile error fixed
 
 ,NAME,SRC BLOCK,SRC SIGNAL,DEST BLOCK,DEST SIGNAL,,,,,,