diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 1801cf3..adb4b1e 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -41,6 +41,12 @@
     { name: "fatal_err",
       desc: "flash fatal errors"
     },
+    { name: "fatal_prim_flash_alert",
+      desc: "Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface."
+    },
+    { name: "recov_prim_flash_alert",
+      desc: "Recoverable alert triggered inside the flash primitive."
+    }
   ],
 
   // Define flash_ctrl <-> flash_phy struct package
@@ -91,12 +97,6 @@
       act: "none"
       name: "flash_test_voltage_h"
     },
-    { struct: "ast_dif",
-      package: "ast_pkg",
-      type: "uni"
-      act: "req"
-      name: "flash_alert"
-    },
 
     { struct:  "lc_tx"
       type:    "uni"
@@ -3010,7 +3010,7 @@
           {
             bits: "2",
             name: "field2",
-            swaccess: "rw1c",
+            swaccess: "ro",
             hwaccess: "hrw",
             resval: "0",
             tags: [],
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
index cbd1977..ff34ec5 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -52,6 +52,12 @@
     { name: "fatal_err",
       desc: "flash fatal errors"
     },
+    { name: "fatal_prim_flash_alert",
+      desc: "Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface."
+    },
+    { name: "recov_prim_flash_alert",
+      desc: "Recoverable alert triggered inside the flash primitive."
+    }
   ],
 
   // Define flash_ctrl <-> flash_phy struct package
@@ -102,12 +108,6 @@
       act: "none"
       name: "flash_test_voltage_h"
     },
-    { struct: "ast_dif",
-      package: "ast_pkg",
-      type: "uni"
-      act: "req"
-      name: "flash_alert"
-    },
 
     { struct:  "lc_tx"
       type:    "uni"
@@ -2485,7 +2485,7 @@
           {
             bits: "2",
             name: "field2",
-            swaccess: "rw1c",
+            swaccess: "ro",
             hwaccess: "hrw",
             resval: "0",
             tags: [],
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index 02743b6..9c536fa 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -87,8 +87,7 @@
   input flash_power_down_h_i,
   input flash_power_ready_h_i,
   inout [1:0] flash_test_mode_a_io,
-  inout flash_test_voltage_h_io,
-  output ast_pkg::ast_dif_t flash_alert_o
+  inout flash_test_voltage_h_io
 );
 
   //////////////////////////////////////////////////////////
@@ -889,6 +888,7 @@
 
   logic [NumAlerts-1:0] alert_srcs;
   logic [NumAlerts-1:0] alert_tests;
+  logic fatal_prim_flash_alert, recov_prim_flash_alert;
 
   // An excessive number of recoverable errors may also indicate an attack
   logic recov_err;
@@ -904,17 +904,23 @@
   lc_ctrl_pkg::lc_tx_t local_esc;
   assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
 
-  assign alert_srcs = { fatal_err,
-                        fatal_std_err,
-                        recov_err
-                      };
+  assign alert_srcs = {
+    fatal_prim_flash_alert,
+    recov_prim_flash_alert,
+    fatal_err,
+    fatal_std_err,
+    recov_err
+  };
 
-  assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
-                         reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
-                         reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
-                       };
+  assign alert_tests = {
+    reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe,
+    reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe,
+    reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+    reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
+    reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
+  };
 
-  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b1, 1'b0};
+  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0, 1'b1, 1'b1, 1'b0};
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
     prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
@@ -1325,7 +1331,8 @@
     .flash_power_ready_h_i,
     .flash_test_mode_a_io,
     .flash_test_voltage_h_io,
-    .flash_alert_o,
+    .fatal_prim_flash_alert_o(fatal_prim_flash_alert),
+    .recov_prim_flash_alert_o(recov_prim_flash_alert),
     .scanmode_i,
     .scan_en_i,
     .scan_rst_ni
@@ -1436,12 +1443,13 @@
   // Alert assertions for reg_we onehot check
   `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1])
 
+  // Assertions for countermeasures inside prim_flash
   `ifndef PRIM_DEFAULT_IMPL
     `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
   `endif
   if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic
     `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A,
-        u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[1])
+        u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3])
   end
 
 endmodule
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
index 6798eca..c1c2fbf 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
@@ -27,12 +27,13 @@
   `include "dv_macros.svh"
 
   // parameters
-  parameter string LIST_OF_ALERTS[] = {"recov_err", "fatal_std_err", "fatal_err"};
+  parameter string LIST_OF_ALERTS[] = {"recov_err", "fatal_std_err", "fatal_err",
+                                       "fatal_prim_flash_alert", "recov_prim_flash_alert"};
 
-  parameter uint NUM_ALERTS = 3;
+  parameter uint NUM_ALERTS = 5;
   parameter uint FlashNumPages = flash_ctrl_pkg::NumBanks * flash_ctrl_pkg::PagesPerBank;
-  parameter uint FlashSizeBytes         = FlashNumPages * flash_ctrl_pkg::WordsPerPage *
-                                            flash_ctrl_pkg::DataWidth / 8;
+  parameter uint FlashSizeBytes = FlashNumPages * flash_ctrl_pkg::WordsPerPage *
+                                  flash_ctrl_pkg::DataWidth / 8;
 
   parameter uint ProgFifoDepth = 4;
   parameter uint ReadFifoDepth = 16;
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv
index 25be806..6c6f0dd 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv
@@ -40,9 +40,6 @@
   logic                             cio_tdo_en;
   logic                             cio_tdo;
 
-  // alert
-  ast_dif_t                         flash_alert;
-
   // power ready
   logic                             power_ready_h = 1'b1;
 
diff --git a/hw/ip/flash_ctrl/dv/tb/tb.sv b/hw/ip/flash_ctrl/dv/tb/tb.sv
index a26c3cc..ac89784 100644
--- a/hw/ip/flash_ctrl/dv/tb/tb.sv
+++ b/hw/ip/flash_ctrl/dv/tb/tb.sv
@@ -193,8 +193,7 @@
     .intr_op_done_o   (intr_op_done),
     .intr_corr_err_o  (intr_err),
     .alert_rx_i       (alert_rx),
-    .alert_tx_o       (alert_tx),
-    .flash_alert_o    (flash_ctrl_if.flash_alert)
+    .alert_tx_o       (alert_tx)
   );
 
   // Create edge in flash_power_down_h_i, whenever reset is asserted
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 55d7a19..af80c31 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -87,8 +87,7 @@
   input flash_power_down_h_i,
   input flash_power_ready_h_i,
   inout [1:0] flash_test_mode_a_io,
-  inout flash_test_voltage_h_io,
-  output ast_pkg::ast_dif_t flash_alert_o
+  inout flash_test_voltage_h_io
 );
 
   //////////////////////////////////////////////////////////
@@ -890,6 +889,7 @@
 
   logic [NumAlerts-1:0] alert_srcs;
   logic [NumAlerts-1:0] alert_tests;
+  logic fatal_prim_flash_alert, recov_prim_flash_alert;
 
   // An excessive number of recoverable errors may also indicate an attack
   logic recov_err;
@@ -905,17 +905,23 @@
   lc_ctrl_pkg::lc_tx_t local_esc;
   assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
 
-  assign alert_srcs = { fatal_err,
-                        fatal_std_err,
-                        recov_err
-                      };
+  assign alert_srcs = {
+    fatal_prim_flash_alert,
+    recov_prim_flash_alert,
+    fatal_err,
+    fatal_std_err,
+    recov_err
+  };
 
-  assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
-                         reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
-                         reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
-                       };
+  assign alert_tests = {
+    reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe,
+    reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe,
+    reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+    reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
+    reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
+  };
 
-  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b1, 1'b0};
+  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0, 1'b1, 1'b1, 1'b0};
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
     prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
@@ -1326,7 +1332,8 @@
     .flash_power_ready_h_i,
     .flash_test_mode_a_io,
     .flash_test_voltage_h_io,
-    .flash_alert_o,
+    .fatal_prim_flash_alert_o(fatal_prim_flash_alert),
+    .recov_prim_flash_alert_o(recov_prim_flash_alert),
     .scanmode_i,
     .scan_en_i,
     .scan_rst_ni
@@ -1437,12 +1444,13 @@
   // Alert assertions for reg_we onehot check
   `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1])
 
+  // Assertions for countermeasures inside prim_flash
   `ifndef PRIM_DEFAULT_IMPL
     `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
   `endif
   if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic
     `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A,
-        u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[1])
+        u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3])
   end
 
 endmodule
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
index dec5b10..6e01fc0 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
@@ -221,6 +221,8 @@
   logic alert_test_recov_err_wd;
   logic alert_test_fatal_std_err_wd;
   logic alert_test_fatal_err_wd;
+  logic alert_test_fatal_prim_flash_alert_wd;
+  logic alert_test_recov_prim_flash_alert_wd;
   logic dis_we;
   logic [3:0] dis_qs;
   logic [3:0] dis_wd;
@@ -1436,7 +1438,7 @@
 
   // R[alert_test]: V(True)
   logic alert_test_qe;
-  logic [2:0] alert_test_flds_we;
+  logic [4:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
   //   F[recov_err]: 0:0
   prim_subreg_ext #(
@@ -1486,6 +1488,38 @@
   );
   assign reg2hw.alert_test.fatal_err.qe = alert_test_qe;
 
+  //   F[fatal_prim_flash_alert]: 3:3
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_alert_test_fatal_prim_flash_alert (
+    .re     (1'b0),
+    .we     (alert_test_we),
+    .wd     (alert_test_fatal_prim_flash_alert_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (alert_test_flds_we[3]),
+    .q      (reg2hw.alert_test.fatal_prim_flash_alert.q),
+    .ds     (),
+    .qs     ()
+  );
+  assign reg2hw.alert_test.fatal_prim_flash_alert.qe = alert_test_qe;
+
+  //   F[recov_prim_flash_alert]: 4:4
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_alert_test_recov_prim_flash_alert (
+    .re     (1'b0),
+    .we     (alert_test_we),
+    .wd     (alert_test_recov_prim_flash_alert_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (alert_test_flds_we[4]),
+    .q      (reg2hw.alert_test.recov_prim_flash_alert.q),
+    .ds     (),
+    .qs     ()
+  );
+  assign reg2hw.alert_test.recov_prim_flash_alert.qe = alert_test_qe;
+
 
   // R[dis]: V(False)
   prim_subreg #(
@@ -11602,6 +11636,10 @@
   assign alert_test_fatal_std_err_wd = reg_wdata[1];
 
   assign alert_test_fatal_err_wd = reg_wdata[2];
+
+  assign alert_test_fatal_prim_flash_alert_wd = reg_wdata[3];
+
+  assign alert_test_recov_prim_flash_alert_wd = reg_wdata[4];
   assign dis_we = addr_hit[4] & reg_we & !reg_error;
 
   assign dis_wd = reg_wdata[3:0];
@@ -12503,6 +12541,8 @@
         reg_rdata_next[0] = '0;
         reg_rdata_next[1] = '0;
         reg_rdata_next[2] = '0;
+        reg_rdata_next[3] = '0;
+        reg_rdata_next[4] = '0;
       end
 
       addr_hit[4]: begin
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv
index c0d0ae2..cc636be 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv
@@ -263,7 +263,6 @@
   logic csr20_field1_qs;
   logic csr20_field1_wd;
   logic csr20_field2_qs;
-  logic csr20_field2_wd;
 
   // Register instances
   // R[csr0_regwen]: V(False)
@@ -1916,15 +1915,15 @@
   //   F[field2]: 2:2
   prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_csr20_field2 (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
-    .we     (csr20_we),
-    .wd     (csr20_field2_wd),
+    .we     (1'b0),
+    .wd     ('0),
 
     // from internal hardware
     .de     (hw2reg.csr20.field2.de),
@@ -2138,8 +2137,6 @@
 
   assign csr20_field1_wd = reg_wdata[1];
 
-  assign csr20_field2_wd = reg_wdata[2];
-
   // Assign write-enables to checker logic vector.
   always_comb begin
     reg_we_check = '0;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index 26c8ab2..85deb10 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -24,7 +24,7 @@
   parameter int unsigned ExecEn = 32'ha26a38f7;
   parameter int MaxFifoDepth = 16;
   parameter int MaxFifoWidth = 5;
-  parameter int NumAlerts = 3;
+  parameter int NumAlerts = 5;
 
   // Address widths within the block
   parameter int CoreAw = 9;
@@ -117,6 +117,14 @@
       logic        q;
       logic        qe;
     } fatal_err;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } fatal_prim_flash_alert;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } recov_prim_flash_alert;
   } flash_ctrl_reg2hw_alert_test_reg_t;
 
   typedef struct packed {
@@ -723,10 +731,10 @@
 
   // Register -> HW type for core interface
   typedef struct packed {
-    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [1322:1317]
-    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [1316:1311]
-    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [1310:1299]
-    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [1298:1293]
+    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [1326:1321]
+    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [1320:1315]
+    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [1314:1303]
+    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [1302:1293]
     flash_ctrl_reg2hw_dis_reg_t dis; // [1292:1289]
     flash_ctrl_reg2hw_exec_reg_t exec; // [1288:1257]
     flash_ctrl_reg2hw_init_reg_t init; // [1256:1256]
@@ -889,10 +897,12 @@
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
-  parameter logic [2:0] FLASH_CTRL_ALERT_TEST_RESVAL = 3'h 0;
+  parameter logic [4:0] FLASH_CTRL_ALERT_TEST_RESVAL = 5'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
+  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_RESVAL = 1'h 0;
+  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
   parameter logic [10:0] FLASH_CTRL_DEBUG_STATE_RESVAL = 11'h 0;
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 7291ba5..6b8b52b 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -40,7 +40,8 @@
   input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i,
   input ast_pkg::ast_obs_ctrl_t obs_ctrl_i,
   output logic [7:0] fla_obs_o,
-  output ast_pkg::ast_dif_t flash_alert_o
+  output logic fatal_prim_flash_alert_o,
+  output logic recov_prim_flash_alert_o
 );
 
   import prim_mubi_pkg::MuBi4False;
@@ -354,8 +355,8 @@
     .flash_test_mode_a_io,
     .flash_test_voltage_h_io,
     .flash_err_o(flash_ctrl_o.macro_err),
-    // There alert signals are forwarded to both flash controller and ast
-    .fl_alert_src_o(flash_alert_o)
+    .fatal_alert_o(fatal_prim_flash_alert_o),
+    .recov_alert_o(recov_prim_flash_alert_o)
   );
   logic unused_alert;
   assign unused_alert = flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack;
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
index b193b31..e67e25a 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
@@ -34,7 +34,9 @@
   inout [TestModeWidth-1:0] flash_test_mode_a_io,
   inout flash_test_voltage_h_io,
   output logic flash_err_o,
-  output ast_pkg::ast_dif_t fl_alert_src_o,
+  // Alert indication (to be connected to alert sender in the instantiating IP)
+  output logic fatal_alert_o,
+  output logic recov_alert_o,
   input tlul_pkg::tl_h2d_t tl_i,
   output tlul_pkg::tl_d2h_t tl_o,
   // Observability
@@ -114,6 +116,7 @@
   // TL-UL Test Interface Emulation //
   ////////////////////////////////////
 
+  logic intg_err;
   flash_ctrl_reg_pkg::flash_ctrl_prim_reg2hw_t reg2hw;
   flash_ctrl_reg_pkg::flash_ctrl_prim_hw2reg_t hw2reg;
   flash_ctrl_prim_reg_top u_reg_top (
@@ -123,7 +126,7 @@
     .tl_o      (tl_o),
     .reg2hw    (reg2hw),
     .hw2reg    (hw2reg),
-    .intg_err_o(), // TODO: do we need to wire this up?
+    .intg_err_o(intg_err),
     .devmode_i (1'b1)
   );
 
@@ -137,8 +140,8 @@
   // open source model has no error response at the moment
   assign flash_err_o = 1'b0;
 
-  // default alert assignments
-  assign fl_alert_src_o = '{p: '0, n: '1};
+  assign fatal_alert_o = intg_err;
+  assign recov_alert_o = 1'b0;
 
   logic unused_obs;
   assign unused_obs = |obs_ctrl_i;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 395fa84..306fa9d 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -4690,20 +4690,6 @@
           index: -1
         }
         {
-          name: flash_alert
-          struct: ast_dif
-          package: ast_pkg
-          type: uni
-          act: req
-          width: 1
-          inst_name: flash_ctrl
-          default: ""
-          external: true
-          top_signame: flash_alert
-          conn_type: false
-          index: -1
-        }
-        {
           name: lc_creator_seed_sw_rw_en
           struct: lc_tx
           package: lc_ctrl_pkg
@@ -8315,7 +8301,6 @@
       clkmgr_aon.hi_speed_sel: hi_speed_sel
       clkmgr_aon.div_step_down_req: div_step_down_req
       clkmgr_aon.calib_rdy: calib_rdy
-      flash_ctrl.flash_alert: flash_alert
       flash_ctrl.flash_bist_enable: flash_bist_enable
       flash_ctrl.flash_power_down_h: flash_power_down_h
       flash_ctrl.flash_power_ready_h: flash_power_ready_h
@@ -13983,6 +13968,24 @@
       lpg_idx: 18
     }
     {
+      name: flash_ctrl_fatal_prim_flash_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: flash_ctrl
+      lpg_name: infra_sys_0
+      lpg_idx: 18
+    }
+    {
+      name: flash_ctrl_recov_prim_flash_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: flash_ctrl
+      lpg_name: infra_sys_0
+      lpg_idx: 18
+    }
+    {
       name: rv_dm_fatal_fault
       width: 1
       type: alert
@@ -16940,20 +16943,6 @@
         index: -1
       }
       {
-        name: flash_alert
-        struct: ast_dif
-        package: ast_pkg
-        type: uni
-        act: req
-        width: 1
-        inst_name: flash_ctrl
-        default: ""
-        external: true
-        top_signame: flash_alert
-        conn_type: false
-        index: -1
-      }
-      {
         name: lc_creator_seed_sw_rw_en
         struct: lc_tx
         package: lc_ctrl_pkg
@@ -19434,18 +19423,6 @@
         netname: calib_rdy
       }
       {
-        package: ast_pkg
-        struct: ast_dif
-        signame: flash_alert_o
-        width: 1
-        type: uni
-        default: ""
-        direction: out
-        conn_type: false
-        index: -1
-        netname: flash_alert
-      }
-      {
         package: prim_mubi_pkg
         struct: mubi4
         signame: flash_bist_enable_i
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index fe4e2d4..bead433 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -1047,7 +1047,6 @@
         'clkmgr_aon.hi_speed_sel'         : 'hi_speed_sel',
         'clkmgr_aon.div_step_down_req'    : 'div_step_down_req',
         'clkmgr_aon.calib_rdy'            : 'calib_rdy',
-        'flash_ctrl.flash_alert'          : 'flash_alert',
         'flash_ctrl.flash_bist_enable'    : 'flash_bist_enable',
         'flash_ctrl.flash_power_down_h'   : 'flash_power_down_h',
         'flash_ctrl.flash_power_ready_h'  : 'flash_power_ready_h',
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 3e8a103..bdf67cd 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -42,28 +42,30 @@
 assign alert_if[35].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
 assign alert_if[36].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
 assign alert_if[37].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[43].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[44].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1];
-assign alert_if[45].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[46].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[47].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[48].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[49].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[50].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
-assign alert_if[51].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[52].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[53].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[54].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
-assign alert_if[55].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[56].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
-assign alert_if[57].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[58].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
-assign alert_if[59].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
-assign alert_if[60].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
-assign alert_if[61].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
-assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[4];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[48].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[49].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[50].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[51].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[52].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
+assign alert_if[53].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[55].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[56].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
+assign alert_if[57].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[58].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
+assign alert_if[59].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[60].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[61].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
+assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
+assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
+assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 52893cd..f68360e 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -43,6 +43,8 @@
   "flash_ctrl_recov_err",
   "flash_ctrl_fatal_std_err",
   "flash_ctrl_fatal_err",
+  "flash_ctrl_fatal_prim_flash_alert",
+  "flash_ctrl_recov_prim_flash_alert",
   "rv_dm_fatal_fault",
   "rv_plic_fatal_fault",
   "aes_recov_ctrl_update_err",
@@ -70,4 +72,4 @@
   "rv_core_ibex_recov_hw_err"
 };
 
-parameter uint NUM_ALERTS = 63;
+parameter uint NUM_ALERTS = 65;
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index 2419b8f..3ab715d 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -47,6 +47,12 @@
     { name: "fatal_err",
       desc: "flash fatal errors"
     },
+    { name: "fatal_prim_flash_alert",
+      desc: "Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface."
+    },
+    { name: "recov_prim_flash_alert",
+      desc: "Recoverable alert triggered inside the flash primitive."
+    }
   ],
 
   // Define flash_ctrl <-> flash_phy struct package
@@ -97,12 +103,6 @@
       act: "none"
       name: "flash_test_voltage_h"
     },
-    { struct: "ast_dif",
-      package: "ast_pkg",
-      type: "uni"
-      act: "req"
-      name: "flash_alert"
-    },
 
     { struct:  "lc_tx"
       type:    "uni"
@@ -3016,7 +3016,7 @@
           {
             bits: "2",
             name: "field2",
-            swaccess: "rw1c",
+            swaccess: "ro",
             hwaccess: "hrw",
             resval: "0",
             tags: [],
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 0115eff..1e11bfc 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -93,8 +93,7 @@
   input flash_power_down_h_i,
   input flash_power_ready_h_i,
   inout [1:0] flash_test_mode_a_io,
-  inout flash_test_voltage_h_io,
-  output ast_pkg::ast_dif_t flash_alert_o
+  inout flash_test_voltage_h_io
 );
 
   //////////////////////////////////////////////////////////
@@ -896,6 +895,7 @@
 
   logic [NumAlerts-1:0] alert_srcs;
   logic [NumAlerts-1:0] alert_tests;
+  logic fatal_prim_flash_alert, recov_prim_flash_alert;
 
   // An excessive number of recoverable errors may also indicate an attack
   logic recov_err;
@@ -911,17 +911,23 @@
   lc_ctrl_pkg::lc_tx_t local_esc;
   assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
 
-  assign alert_srcs = { fatal_err,
-                        fatal_std_err,
-                        recov_err
-                      };
+  assign alert_srcs = {
+    fatal_prim_flash_alert,
+    recov_prim_flash_alert,
+    fatal_err,
+    fatal_std_err,
+    recov_err
+  };
 
-  assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
-                         reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
-                         reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
-                       };
+  assign alert_tests = {
+    reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe,
+    reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe,
+    reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+    reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
+    reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
+  };
 
-  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b1, 1'b0};
+  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0, 1'b1, 1'b1, 1'b0};
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
     prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
@@ -1332,7 +1338,8 @@
     .flash_power_ready_h_i,
     .flash_test_mode_a_io,
     .flash_test_voltage_h_io,
-    .flash_alert_o,
+    .fatal_prim_flash_alert_o(fatal_prim_flash_alert),
+    .recov_prim_flash_alert_o(recov_prim_flash_alert),
     .scanmode_i,
     .scan_en_i,
     .scan_rst_ni
@@ -1443,12 +1450,13 @@
   // Alert assertions for reg_we onehot check
   `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1])
 
+  // Assertions for countermeasures inside prim_flash
   `ifndef PRIM_DEFAULT_IMPL
     `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
   `endif
   if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic
     `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A,
-        u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[1])
+        u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3])
   end
 
 endmodule
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
index dec5b10..6e01fc0 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
@@ -221,6 +221,8 @@
   logic alert_test_recov_err_wd;
   logic alert_test_fatal_std_err_wd;
   logic alert_test_fatal_err_wd;
+  logic alert_test_fatal_prim_flash_alert_wd;
+  logic alert_test_recov_prim_flash_alert_wd;
   logic dis_we;
   logic [3:0] dis_qs;
   logic [3:0] dis_wd;
@@ -1436,7 +1438,7 @@
 
   // R[alert_test]: V(True)
   logic alert_test_qe;
-  logic [2:0] alert_test_flds_we;
+  logic [4:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
   //   F[recov_err]: 0:0
   prim_subreg_ext #(
@@ -1486,6 +1488,38 @@
   );
   assign reg2hw.alert_test.fatal_err.qe = alert_test_qe;
 
+  //   F[fatal_prim_flash_alert]: 3:3
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_alert_test_fatal_prim_flash_alert (
+    .re     (1'b0),
+    .we     (alert_test_we),
+    .wd     (alert_test_fatal_prim_flash_alert_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (alert_test_flds_we[3]),
+    .q      (reg2hw.alert_test.fatal_prim_flash_alert.q),
+    .ds     (),
+    .qs     ()
+  );
+  assign reg2hw.alert_test.fatal_prim_flash_alert.qe = alert_test_qe;
+
+  //   F[recov_prim_flash_alert]: 4:4
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_alert_test_recov_prim_flash_alert (
+    .re     (1'b0),
+    .we     (alert_test_we),
+    .wd     (alert_test_recov_prim_flash_alert_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (alert_test_flds_we[4]),
+    .q      (reg2hw.alert_test.recov_prim_flash_alert.q),
+    .ds     (),
+    .qs     ()
+  );
+  assign reg2hw.alert_test.recov_prim_flash_alert.qe = alert_test_qe;
+
 
   // R[dis]: V(False)
   prim_subreg #(
@@ -11602,6 +11636,10 @@
   assign alert_test_fatal_std_err_wd = reg_wdata[1];
 
   assign alert_test_fatal_err_wd = reg_wdata[2];
+
+  assign alert_test_fatal_prim_flash_alert_wd = reg_wdata[3];
+
+  assign alert_test_recov_prim_flash_alert_wd = reg_wdata[4];
   assign dis_we = addr_hit[4] & reg_we & !reg_error;
 
   assign dis_wd = reg_wdata[3:0];
@@ -12503,6 +12541,8 @@
         reg_rdata_next[0] = '0;
         reg_rdata_next[1] = '0;
         reg_rdata_next[2] = '0;
+        reg_rdata_next[3] = '0;
+        reg_rdata_next[4] = '0;
       end
 
       addr_hit[4]: begin
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv
index c0d0ae2..cc636be 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv
@@ -263,7 +263,6 @@
   logic csr20_field1_qs;
   logic csr20_field1_wd;
   logic csr20_field2_qs;
-  logic csr20_field2_wd;
 
   // Register instances
   // R[csr0_regwen]: V(False)
@@ -1916,15 +1915,15 @@
   //   F[field2]: 2:2
   prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_csr20_field2 (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
-    .we     (csr20_we),
-    .wd     (csr20_field2_wd),
+    .we     (1'b0),
+    .wd     ('0),
 
     // from internal hardware
     .de     (hw2reg.csr20.field2.de),
@@ -2138,8 +2137,6 @@
 
   assign csr20_field1_wd = reg_wdata[1];
 
-  assign csr20_field2_wd = reg_wdata[2];
-
   // Assign write-enables to checker logic vector.
   always_comb begin
     reg_we_check = '0;
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
index 26c8ab2..85deb10 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -24,7 +24,7 @@
   parameter int unsigned ExecEn = 32'ha26a38f7;
   parameter int MaxFifoDepth = 16;
   parameter int MaxFifoWidth = 5;
-  parameter int NumAlerts = 3;
+  parameter int NumAlerts = 5;
 
   // Address widths within the block
   parameter int CoreAw = 9;
@@ -117,6 +117,14 @@
       logic        q;
       logic        qe;
     } fatal_err;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } fatal_prim_flash_alert;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } recov_prim_flash_alert;
   } flash_ctrl_reg2hw_alert_test_reg_t;
 
   typedef struct packed {
@@ -723,10 +731,10 @@
 
   // Register -> HW type for core interface
   typedef struct packed {
-    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [1322:1317]
-    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [1316:1311]
-    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [1310:1299]
-    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [1298:1293]
+    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [1326:1321]
+    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [1320:1315]
+    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [1314:1303]
+    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [1302:1293]
     flash_ctrl_reg2hw_dis_reg_t dis; // [1292:1289]
     flash_ctrl_reg2hw_exec_reg_t exec; // [1288:1257]
     flash_ctrl_reg2hw_init_reg_t init; // [1256:1256]
@@ -889,10 +897,12 @@
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
-  parameter logic [2:0] FLASH_CTRL_ALERT_TEST_RESVAL = 3'h 0;
+  parameter logic [4:0] FLASH_CTRL_ALERT_TEST_RESVAL = 5'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
+  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_RESVAL = 1'h 0;
+  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
   parameter logic [10:0] FLASH_CTRL_DEBUG_STATE_RESVAL = 11'h 0;
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
index 2143f4f..7dc245c 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -32,7 +32,7 @@
     { name: "NAlerts",
       desc: "Number of alert channels.",
       type: "int",
-      default: "63",
+      default: "65",
       local: "true"
     },
     { name: "NLpg",
@@ -82,6 +82,8 @@
                  5'd18,
                  5'd18,
                  5'd18,
+                 5'd18,
+                 5'd18,
                  5'd12,
                  5'd17,
                  5'd17,
@@ -203,6 +205,8 @@
                  1'b1,
                  1'b1,
                  1'b1,
+                 1'b1,
+                 1'b1,
                  1'b1
                }
                '''
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
index 8b68a64..b191cf5 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
@@ -5,7 +5,7 @@
   instance_name: top_earlgrey_alert_handler
   param_values:
   {
-    n_alerts: 63
+    n_alerts: 65
     esc_cnt_dw: 32
     accu_cnt_dw: 16
     async_on:
@@ -73,6 +73,8 @@
       1'b1
       1'b1
       1'b1
+      1'b1
+      1'b1
     ]
     n_classes: 4
     n_lpg: 22
@@ -116,6 +118,8 @@
       5'd18
       5'd18
       5'd18
+      5'd18
+      5'd18
       5'd19
       5'd20
       5'd21
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
index 6c6dda2..3581557 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
@@ -7,7 +7,7 @@
 package alert_handler_reg_pkg;
 
   // Param list
-  parameter int NAlerts = 63;
+  parameter int NAlerts = 65;
   parameter int NLpg = 22;
   parameter int NLpgWidth = 5;
   parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = {
@@ -39,6 +39,8 @@
   5'd18,
   5'd18,
   5'd18,
+  5'd18,
+  5'd18,
   5'd12,
   5'd17,
   5'd17,
@@ -140,6 +142,8 @@
   1'b1,
   1'b1,
   1'b1,
+  1'b1,
+  1'b1,
   1'b1
 };
   parameter int N_CLASSES = 4;
@@ -613,15 +617,15 @@
 
   // Register -> HW type
   typedef struct packed {
-    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1151:1148]
-    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1147:1144]
-    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1143:1136]
-    alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1135:1120]
-    alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1119:1119]
-    alert_handler_reg2hw_alert_regwen_mreg_t [62:0] alert_regwen; // [1118:1056]
-    alert_handler_reg2hw_alert_en_shadowed_mreg_t [62:0] alert_en_shadowed; // [1055:993]
-    alert_handler_reg2hw_alert_class_shadowed_mreg_t [62:0] alert_class_shadowed; // [992:867]
-    alert_handler_reg2hw_alert_cause_mreg_t [62:0] alert_cause; // [866:804]
+    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1161:1158]
+    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1157:1154]
+    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1153:1146]
+    alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1145:1130]
+    alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1129:1129]
+    alert_handler_reg2hw_alert_regwen_mreg_t [64:0] alert_regwen; // [1128:1064]
+    alert_handler_reg2hw_alert_en_shadowed_mreg_t [64:0] alert_en_shadowed; // [1063:999]
+    alert_handler_reg2hw_alert_class_shadowed_mreg_t [64:0] alert_class_shadowed; // [998:869]
+    alert_handler_reg2hw_alert_cause_mreg_t [64:0] alert_cause; // [868:804]
     alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797]
     alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0]
         loc_alert_class_shadowed; // [796:783]
@@ -674,8 +678,8 @@
 
   // HW -> register type
   typedef struct packed {
-    alert_handler_hw2reg_intr_state_reg_t intr_state; // [359:352]
-    alert_handler_hw2reg_alert_cause_mreg_t [62:0] alert_cause; // [351:226]
+    alert_handler_hw2reg_intr_state_reg_t intr_state; // [363:356]
+    alert_handler_hw2reg_alert_cause_mreg_t [64:0] alert_cause; // [355:226]
     alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212]
     alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
     alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -765,279 +769,287 @@
   parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108;
   parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c;
   parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 114;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 118;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 11c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 120;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 124;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 128;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 12c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 130;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 134;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 138;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 13c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 140;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 144;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 148;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 14c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 150;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 154;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 158;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 15c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 160;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 164;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 168;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 16c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 170;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 174;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 178;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 17c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 180;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 184;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 188;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 18c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 190;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 194;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 198;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 19c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 1fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 200;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 204;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 208;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 20c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 210;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 214;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 218;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 21c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 220;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 224;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 228;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 22c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 230;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 234;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 238;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 23c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 240;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 244;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 248;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 24c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 250;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 254;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 258;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 25c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 260;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 264;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 268;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 26c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 270;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 274;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 278;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 27c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 280;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 284;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 288;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 28c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 290;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 294;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 298;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 29c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 2f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 2fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 300;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 304;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 308;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 30c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 310;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 314;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 318;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 31c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 320;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 324;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 328;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 32c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 330;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 334;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 338;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 33c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 340;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 344;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 348;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 34c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 350;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 354;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 358;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 35c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 360;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 364;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 368;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 36c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 370;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 374;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 378;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 37c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 380;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 384;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 388;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 38c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 390;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 394;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 398;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 39c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 3f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 3f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 3fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 400;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 404;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 408;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 40c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 410;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 414;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 418;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 41c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 420;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 424;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 428;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 42c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 430;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 434;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 438;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 43c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 440;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 444;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 448;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 44c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 450;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 454;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 458;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 45c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 460;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 464;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 468;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 46c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 470;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 474;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 478;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 47c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 480;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 484;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 488;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 48c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 490;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 494;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 498;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 49c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 500;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 504;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 508;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 50c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 510;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 514;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 518;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 51c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 520;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 524;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 528;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 52c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 530;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 534;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 538;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 53c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 540;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 544;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 548;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 54c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 550;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 554;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 11c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 120;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 124;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 128;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 12c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 130;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 134;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 138;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 13c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 140;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 144;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 148;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 14c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 150;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 154;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 158;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 15c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 160;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 164;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 168;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 16c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 170;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 174;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 178;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 17c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 180;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 184;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 188;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 18c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 190;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 194;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 198;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 19c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 200;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 204;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 208;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 20c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 210;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 214;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 218;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 21c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 220;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 224;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 228;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 22c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 230;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 234;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 238;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 23c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 240;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 244;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 248;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 24c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 250;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 254;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 258;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 25c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 260;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 264;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 268;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 26c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 270;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 274;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 278;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 27c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 280;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 284;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 288;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 28c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 290;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 294;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 298;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 29c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 300;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 304;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 308;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 30c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 310;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 314;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 318;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 31c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 320;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 324;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 328;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 32c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 330;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 334;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 338;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 33c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 340;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 344;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 348;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 34c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 350;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 354;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 358;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 35c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 360;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 364;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 368;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 36c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 370;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 374;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 378;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 37c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 380;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 384;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 388;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 38c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 390;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 394;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 398;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 39c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 400;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 404;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 408;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 40c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 410;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 414;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 418;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 41c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 420;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 424;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 428;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 42c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 430;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 434;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 438;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 43c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 440;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 444;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 448;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 44c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 450;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 454;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 458;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 45c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 460;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 464;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 468;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 46c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 470;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 474;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 478;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 47c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 480;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 484;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 488;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 48c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 490;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 494;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 498;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 49c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 500;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 504;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 508;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 50c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 510;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 514;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 518;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 51c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 520;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 524;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 528;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 52c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 530;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 534;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 538;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 53c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 540;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 544;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 548;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 54c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 550;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 554;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 558;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 55c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 560;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 564;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 568;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 56c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 570;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 574;
 
   // Reset values for hwext registers and their fields
   parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -1129,6 +1141,8 @@
     ALERT_HANDLER_ALERT_REGWEN_60,
     ALERT_HANDLER_ALERT_REGWEN_61,
     ALERT_HANDLER_ALERT_REGWEN_62,
+    ALERT_HANDLER_ALERT_REGWEN_63,
+    ALERT_HANDLER_ALERT_REGWEN_64,
     ALERT_HANDLER_ALERT_EN_SHADOWED_0,
     ALERT_HANDLER_ALERT_EN_SHADOWED_1,
     ALERT_HANDLER_ALERT_EN_SHADOWED_2,
@@ -1192,6 +1206,8 @@
     ALERT_HANDLER_ALERT_EN_SHADOWED_60,
     ALERT_HANDLER_ALERT_EN_SHADOWED_61,
     ALERT_HANDLER_ALERT_EN_SHADOWED_62,
+    ALERT_HANDLER_ALERT_EN_SHADOWED_63,
+    ALERT_HANDLER_ALERT_EN_SHADOWED_64,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_0,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_1,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_2,
@@ -1255,6 +1271,8 @@
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_60,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_61,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_62,
+    ALERT_HANDLER_ALERT_CLASS_SHADOWED_63,
+    ALERT_HANDLER_ALERT_CLASS_SHADOWED_64,
     ALERT_HANDLER_ALERT_CAUSE_0,
     ALERT_HANDLER_ALERT_CAUSE_1,
     ALERT_HANDLER_ALERT_CAUSE_2,
@@ -1318,6 +1336,8 @@
     ALERT_HANDLER_ALERT_CAUSE_60,
     ALERT_HANDLER_ALERT_CAUSE_61,
     ALERT_HANDLER_ALERT_CAUSE_62,
+    ALERT_HANDLER_ALERT_CAUSE_63,
+    ALERT_HANDLER_ALERT_CAUSE_64,
     ALERT_HANDLER_LOC_ALERT_REGWEN_0,
     ALERT_HANDLER_LOC_ALERT_REGWEN_1,
     ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1405,7 +1425,7 @@
   } alert_handler_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] ALERT_HANDLER_PERMIT [342] = '{
+  parameter logic [3:0] ALERT_HANDLER_PERMIT [350] = '{
     4'b 0001, // index[  0] ALERT_HANDLER_INTR_STATE
     4'b 0001, // index[  1] ALERT_HANDLER_INTR_ENABLE
     4'b 0001, // index[  2] ALERT_HANDLER_INTR_TEST
@@ -1475,279 +1495,287 @@
     4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60
     4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61
     4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62
-    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_0
-    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_1
-    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_2
-    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_3
-    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_4
-    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_5
-    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_6
-    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_7
-    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_8
-    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_9
-    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_10
-    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_11
-    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_12
-    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_13
-    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_14
-    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_15
-    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_16
-    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_17
-    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_18
-    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_19
-    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_20
-    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_21
-    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_22
-    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_23
-    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_24
-    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_25
-    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_26
-    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_27
-    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_28
-    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_29
-    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_30
-    4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_31
-    4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_32
-    4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_33
-    4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_34
-    4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_35
-    4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_36
-    4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_37
-    4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_38
-    4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_39
-    4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_40
-    4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_41
-    4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_42
-    4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_43
-    4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_44
-    4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_45
-    4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_46
-    4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_47
-    4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_48
-    4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_49
-    4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_50
-    4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_51
-    4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_52
-    4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_53
-    4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_54
-    4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_55
-    4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_56
-    4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_57
-    4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_58
-    4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_59
-    4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_60
-    4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_61
-    4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_62
-    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
-    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
-    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
-    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
-    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
-    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
-    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
-    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
-    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
-    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
-    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
-    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
-    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
-    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
-    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
-    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
-    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
-    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
-    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
-    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
-    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
-    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
-    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
-    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
-    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
-    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
-    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
-    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
-    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
-    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
-    4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
-    4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
-    4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
-    4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
-    4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
-    4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
-    4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
-    4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
-    4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
-    4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
-    4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
-    4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
-    4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
-    4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
-    4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
-    4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
-    4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
-    4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
-    4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
-    4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
-    4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
-    4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
-    4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
-    4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
-    4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
-    4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
-    4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
-    4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
-    4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
-    4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59
-    4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60
-    4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61
-    4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62
-    4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_0
-    4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_1
-    4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_2
-    4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_3
-    4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_4
-    4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_5
-    4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_6
-    4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_7
-    4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_8
-    4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_9
-    4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_10
-    4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_11
-    4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_12
-    4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_13
-    4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_14
-    4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_15
-    4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_16
-    4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_17
-    4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_18
-    4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_19
-    4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_20
-    4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_21
-    4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_22
-    4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_23
-    4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_24
-    4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_25
-    4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_26
-    4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_27
-    4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_28
-    4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_29
-    4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_30
-    4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_31
-    4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_32
-    4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_33
-    4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_34
-    4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_35
-    4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_36
-    4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_37
-    4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_38
-    4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_39
-    4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_40
-    4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_41
-    4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_42
-    4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_43
-    4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_44
-    4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_45
-    4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_46
-    4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_47
-    4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_48
-    4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_49
-    4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_50
-    4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_51
-    4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_52
-    4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_53
-    4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_54
-    4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_55
-    4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_56
-    4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_57
-    4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_58
-    4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_59
-    4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_60
-    4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_61
-    4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_62
-    4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_REGWEN_0
-    4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_REGWEN_1
-    4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_REGWEN_2
-    4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_REGWEN_3
-    4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_REGWEN_4
-    4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_REGWEN_5
-    4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_REGWEN_6
-    4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
-    4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
-    4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
-    4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
-    4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
-    4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
-    4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
-    4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
-    4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
-    4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
-    4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
-    4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
-    4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
-    4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
-    4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_CAUSE_0
-    4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CAUSE_1
-    4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CAUSE_2
-    4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CAUSE_3
-    4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CAUSE_4
-    4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CAUSE_5
-    4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CAUSE_6
-    4'b 0001, // index[286] ALERT_HANDLER_CLASSA_REGWEN
-    4'b 0011, // index[287] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
-    4'b 0001, // index[288] ALERT_HANDLER_CLASSA_CLR_REGWEN
-    4'b 0001, // index[289] ALERT_HANDLER_CLASSA_CLR_SHADOWED
-    4'b 0011, // index[290] ALERT_HANDLER_CLASSA_ACCUM_CNT
-    4'b 0011, // index[291] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[292] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[293] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[294] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[295] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[296] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[297] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[298] ALERT_HANDLER_CLASSA_ESC_CNT
-    4'b 0001, // index[299] ALERT_HANDLER_CLASSA_STATE
-    4'b 0001, // index[300] ALERT_HANDLER_CLASSB_REGWEN
-    4'b 0011, // index[301] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
-    4'b 0001, // index[302] ALERT_HANDLER_CLASSB_CLR_REGWEN
-    4'b 0001, // index[303] ALERT_HANDLER_CLASSB_CLR_SHADOWED
-    4'b 0011, // index[304] ALERT_HANDLER_CLASSB_ACCUM_CNT
-    4'b 0011, // index[305] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[306] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[307] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[308] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[309] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[310] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[311] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[312] ALERT_HANDLER_CLASSB_ESC_CNT
-    4'b 0001, // index[313] ALERT_HANDLER_CLASSB_STATE
-    4'b 0001, // index[314] ALERT_HANDLER_CLASSC_REGWEN
-    4'b 0011, // index[315] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
-    4'b 0001, // index[316] ALERT_HANDLER_CLASSC_CLR_REGWEN
-    4'b 0001, // index[317] ALERT_HANDLER_CLASSC_CLR_SHADOWED
-    4'b 0011, // index[318] ALERT_HANDLER_CLASSC_ACCUM_CNT
-    4'b 0011, // index[319] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[320] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[321] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[322] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[323] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[324] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[325] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[326] ALERT_HANDLER_CLASSC_ESC_CNT
-    4'b 0001, // index[327] ALERT_HANDLER_CLASSC_STATE
-    4'b 0001, // index[328] ALERT_HANDLER_CLASSD_REGWEN
-    4'b 0011, // index[329] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
-    4'b 0001, // index[330] ALERT_HANDLER_CLASSD_CLR_REGWEN
-    4'b 0001, // index[331] ALERT_HANDLER_CLASSD_CLR_SHADOWED
-    4'b 0011, // index[332] ALERT_HANDLER_CLASSD_ACCUM_CNT
-    4'b 0011, // index[333] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[334] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[335] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[336] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[337] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[338] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[339] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[340] ALERT_HANDLER_CLASSD_ESC_CNT
-    4'b 0001  // index[341] ALERT_HANDLER_CLASSD_STATE
+    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63
+    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64
+    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_0
+    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_1
+    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_2
+    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_3
+    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_4
+    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_5
+    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_6
+    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_7
+    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_8
+    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_9
+    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_10
+    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_11
+    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_12
+    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_13
+    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_14
+    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_15
+    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_16
+    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_17
+    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_18
+    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_19
+    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_20
+    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_21
+    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_22
+    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_23
+    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_24
+    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_25
+    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_26
+    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_27
+    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_28
+    4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_29
+    4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_30
+    4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_31
+    4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_32
+    4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_33
+    4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_34
+    4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_35
+    4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_36
+    4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_37
+    4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_38
+    4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_39
+    4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_40
+    4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_41
+    4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_42
+    4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_43
+    4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_44
+    4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_45
+    4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_46
+    4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_47
+    4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_48
+    4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_49
+    4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_50
+    4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_51
+    4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_52
+    4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_53
+    4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_54
+    4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_55
+    4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_56
+    4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_57
+    4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_58
+    4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_59
+    4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_60
+    4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_61
+    4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_62
+    4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_63
+    4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_64
+    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
+    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
+    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
+    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
+    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
+    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
+    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
+    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
+    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
+    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
+    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
+    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
+    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
+    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
+    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
+    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
+    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
+    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
+    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
+    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
+    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
+    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
+    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
+    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
+    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
+    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
+    4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
+    4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
+    4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
+    4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
+    4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
+    4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
+    4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
+    4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
+    4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
+    4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
+    4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
+    4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
+    4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
+    4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
+    4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
+    4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
+    4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
+    4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
+    4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
+    4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
+    4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
+    4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
+    4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
+    4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
+    4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
+    4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
+    4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
+    4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
+    4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
+    4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
+    4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
+    4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
+    4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
+    4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59
+    4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60
+    4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61
+    4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62
+    4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63
+    4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64
+    4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_0
+    4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_1
+    4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_2
+    4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_3
+    4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_4
+    4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_5
+    4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_6
+    4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_7
+    4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_8
+    4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_9
+    4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_10
+    4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_11
+    4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_12
+    4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_13
+    4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_14
+    4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_15
+    4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_16
+    4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_17
+    4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_18
+    4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_19
+    4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_20
+    4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_21
+    4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_22
+    4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_23
+    4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_24
+    4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_25
+    4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_26
+    4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_27
+    4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_28
+    4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_29
+    4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_30
+    4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_31
+    4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_32
+    4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_33
+    4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_34
+    4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_35
+    4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_36
+    4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_37
+    4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_38
+    4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_39
+    4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_40
+    4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_41
+    4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_42
+    4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_43
+    4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_44
+    4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_45
+    4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_46
+    4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_47
+    4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_48
+    4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_49
+    4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_50
+    4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_51
+    4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_52
+    4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_53
+    4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_54
+    4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_55
+    4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_56
+    4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_57
+    4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_58
+    4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_59
+    4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_60
+    4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_61
+    4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_62
+    4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_63
+    4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_64
+    4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+    4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+    4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+    4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+    4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+    4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_REGWEN_5
+    4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_REGWEN_6
+    4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
+    4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
+    4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
+    4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
+    4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
+    4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
+    4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
+    4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
+    4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
+    4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
+    4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
+    4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
+    4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
+    4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
+    4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+    4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+    4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+    4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+    4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+    4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_5
+    4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_6
+    4'b 0001, // index[294] ALERT_HANDLER_CLASSA_REGWEN
+    4'b 0011, // index[295] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
+    4'b 0001, // index[296] ALERT_HANDLER_CLASSA_CLR_REGWEN
+    4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CLR_SHADOWED
+    4'b 0011, // index[298] ALERT_HANDLER_CLASSA_ACCUM_CNT
+    4'b 0011, // index[299] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[300] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[301] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[302] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[303] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[304] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[305] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[306] ALERT_HANDLER_CLASSA_ESC_CNT
+    4'b 0001, // index[307] ALERT_HANDLER_CLASSA_STATE
+    4'b 0001, // index[308] ALERT_HANDLER_CLASSB_REGWEN
+    4'b 0011, // index[309] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
+    4'b 0001, // index[310] ALERT_HANDLER_CLASSB_CLR_REGWEN
+    4'b 0001, // index[311] ALERT_HANDLER_CLASSB_CLR_SHADOWED
+    4'b 0011, // index[312] ALERT_HANDLER_CLASSB_ACCUM_CNT
+    4'b 0011, // index[313] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[314] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[315] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[316] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[317] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[318] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[319] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[320] ALERT_HANDLER_CLASSB_ESC_CNT
+    4'b 0001, // index[321] ALERT_HANDLER_CLASSB_STATE
+    4'b 0001, // index[322] ALERT_HANDLER_CLASSC_REGWEN
+    4'b 0011, // index[323] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
+    4'b 0001, // index[324] ALERT_HANDLER_CLASSC_CLR_REGWEN
+    4'b 0001, // index[325] ALERT_HANDLER_CLASSC_CLR_SHADOWED
+    4'b 0011, // index[326] ALERT_HANDLER_CLASSC_ACCUM_CNT
+    4'b 0011, // index[327] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[328] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[329] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[330] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[331] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[332] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[333] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[334] ALERT_HANDLER_CLASSC_ESC_CNT
+    4'b 0001, // index[335] ALERT_HANDLER_CLASSC_STATE
+    4'b 0001, // index[336] ALERT_HANDLER_CLASSD_REGWEN
+    4'b 0011, // index[337] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
+    4'b 0001, // index[338] ALERT_HANDLER_CLASSD_CLR_REGWEN
+    4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CLR_SHADOWED
+    4'b 0011, // index[340] ALERT_HANDLER_CLASSD_ACCUM_CNT
+    4'b 0011, // index[341] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[342] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[343] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[344] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[345] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[346] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[347] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[348] ALERT_HANDLER_CLASSD_ESC_CNT
+    4'b 0001  // index[349] ALERT_HANDLER_CLASSD_STATE
   };
 
 endpackage
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
index 1a2e94a..2007d74 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
@@ -59,9 +59,9 @@
 
   // also check for spurious write enables
   logic reg_we_err;
-  logic [341:0] reg_we_check;
+  logic [349:0] reg_we_check;
   prim_reg_we_check #(
-    .OneHotWidth(342)
+    .OneHotWidth(350)
   ) u_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
@@ -352,6 +352,12 @@
   logic alert_regwen_62_we;
   logic alert_regwen_62_qs;
   logic alert_regwen_62_wd;
+  logic alert_regwen_63_we;
+  logic alert_regwen_63_qs;
+  logic alert_regwen_63_wd;
+  logic alert_regwen_64_we;
+  logic alert_regwen_64_qs;
+  logic alert_regwen_64_wd;
   logic alert_en_shadowed_0_re;
   logic alert_en_shadowed_0_we;
   logic alert_en_shadowed_0_qs;
@@ -730,6 +736,18 @@
   logic alert_en_shadowed_62_wd;
   logic alert_en_shadowed_62_storage_err;
   logic alert_en_shadowed_62_update_err;
+  logic alert_en_shadowed_63_re;
+  logic alert_en_shadowed_63_we;
+  logic alert_en_shadowed_63_qs;
+  logic alert_en_shadowed_63_wd;
+  logic alert_en_shadowed_63_storage_err;
+  logic alert_en_shadowed_63_update_err;
+  logic alert_en_shadowed_64_re;
+  logic alert_en_shadowed_64_we;
+  logic alert_en_shadowed_64_qs;
+  logic alert_en_shadowed_64_wd;
+  logic alert_en_shadowed_64_storage_err;
+  logic alert_en_shadowed_64_update_err;
   logic alert_class_shadowed_0_re;
   logic alert_class_shadowed_0_we;
   logic [1:0] alert_class_shadowed_0_qs;
@@ -1108,6 +1126,18 @@
   logic [1:0] alert_class_shadowed_62_wd;
   logic alert_class_shadowed_62_storage_err;
   logic alert_class_shadowed_62_update_err;
+  logic alert_class_shadowed_63_re;
+  logic alert_class_shadowed_63_we;
+  logic [1:0] alert_class_shadowed_63_qs;
+  logic [1:0] alert_class_shadowed_63_wd;
+  logic alert_class_shadowed_63_storage_err;
+  logic alert_class_shadowed_63_update_err;
+  logic alert_class_shadowed_64_re;
+  logic alert_class_shadowed_64_we;
+  logic [1:0] alert_class_shadowed_64_qs;
+  logic [1:0] alert_class_shadowed_64_wd;
+  logic alert_class_shadowed_64_storage_err;
+  logic alert_class_shadowed_64_update_err;
   logic alert_cause_0_we;
   logic alert_cause_0_qs;
   logic alert_cause_0_wd;
@@ -1297,6 +1327,12 @@
   logic alert_cause_62_we;
   logic alert_cause_62_qs;
   logic alert_cause_62_wd;
+  logic alert_cause_63_we;
+  logic alert_cause_63_qs;
+  logic alert_cause_63_wd;
+  logic alert_cause_64_we;
+  logic alert_cause_64_qs;
+  logic alert_cause_64_wd;
   logic loc_alert_regwen_0_we;
   logic loc_alert_regwen_0_qs;
   logic loc_alert_regwen_0_wd;
@@ -3983,6 +4019,62 @@
   );
 
 
+  // Subregister 63 of Multireg alert_regwen
+  // R[alert_regwen_63]: V(False)
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_63 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_regwen_63_we),
+    .wd     (alert_regwen_63_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[63].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_regwen_63_qs)
+  );
+
+
+  // Subregister 64 of Multireg alert_regwen
+  // R[alert_regwen_64]: V(False)
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_64 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_regwen_64_we),
+    .wd     (alert_regwen_64_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[64].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_regwen_64_qs)
+  );
+
+
   // Subregister 0 of Multireg alert_en_shadowed
   // R[alert_en_shadowed_0]: V(False)
   // Create REGWEN-gated WE signal
@@ -6503,6 +6595,86 @@
   );
 
 
+  // Subregister 63 of Multireg alert_en_shadowed
+  // R[alert_en_shadowed_63]: V(False)
+  // Create REGWEN-gated WE signal
+  logic alert_en_shadowed_63_gated_we;
+  assign alert_en_shadowed_63_gated_we = alert_en_shadowed_63_we & alert_regwen_63_qs;
+  prim_subreg_shadow #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .RESVAL  (1'h0)
+  ) u_alert_en_shadowed_63 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+    .rst_shadowed_ni (rst_shadowed_ni),
+
+    // from register interface
+    .re     (alert_en_shadowed_63_re),
+    .we     (alert_en_shadowed_63_gated_we),
+    .wd     (alert_en_shadowed_63_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en_shadowed[63].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_en_shadowed_63_qs),
+
+    // Shadow register phase. Relevant for hwext only.
+    .phase  (),
+
+    // Shadow register error conditions
+    .err_update  (alert_en_shadowed_63_update_err),
+    .err_storage (alert_en_shadowed_63_storage_err)
+  );
+
+
+  // Subregister 64 of Multireg alert_en_shadowed
+  // R[alert_en_shadowed_64]: V(False)
+  // Create REGWEN-gated WE signal
+  logic alert_en_shadowed_64_gated_we;
+  assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs;
+  prim_subreg_shadow #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .RESVAL  (1'h0)
+  ) u_alert_en_shadowed_64 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+    .rst_shadowed_ni (rst_shadowed_ni),
+
+    // from register interface
+    .re     (alert_en_shadowed_64_re),
+    .we     (alert_en_shadowed_64_gated_we),
+    .wd     (alert_en_shadowed_64_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en_shadowed[64].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_en_shadowed_64_qs),
+
+    // Shadow register phase. Relevant for hwext only.
+    .phase  (),
+
+    // Shadow register error conditions
+    .err_update  (alert_en_shadowed_64_update_err),
+    .err_storage (alert_en_shadowed_64_storage_err)
+  );
+
+
   // Subregister 0 of Multireg alert_class_shadowed
   // R[alert_class_shadowed_0]: V(False)
   // Create REGWEN-gated WE signal
@@ -9023,6 +9195,86 @@
   );
 
 
+  // Subregister 63 of Multireg alert_class_shadowed
+  // R[alert_class_shadowed_63]: V(False)
+  // Create REGWEN-gated WE signal
+  logic alert_class_shadowed_63_gated_we;
+  assign alert_class_shadowed_63_gated_we = alert_class_shadowed_63_we & alert_regwen_63_qs;
+  prim_subreg_shadow #(
+    .DW      (2),
+    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .RESVAL  (2'h0)
+  ) u_alert_class_shadowed_63 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+    .rst_shadowed_ni (rst_shadowed_ni),
+
+    // from register interface
+    .re     (alert_class_shadowed_63_re),
+    .we     (alert_class_shadowed_63_gated_we),
+    .wd     (alert_class_shadowed_63_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class_shadowed[63].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_class_shadowed_63_qs),
+
+    // Shadow register phase. Relevant for hwext only.
+    .phase  (),
+
+    // Shadow register error conditions
+    .err_update  (alert_class_shadowed_63_update_err),
+    .err_storage (alert_class_shadowed_63_storage_err)
+  );
+
+
+  // Subregister 64 of Multireg alert_class_shadowed
+  // R[alert_class_shadowed_64]: V(False)
+  // Create REGWEN-gated WE signal
+  logic alert_class_shadowed_64_gated_we;
+  assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs;
+  prim_subreg_shadow #(
+    .DW      (2),
+    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .RESVAL  (2'h0)
+  ) u_alert_class_shadowed_64 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+    .rst_shadowed_ni (rst_shadowed_ni),
+
+    // from register interface
+    .re     (alert_class_shadowed_64_re),
+    .we     (alert_class_shadowed_64_gated_we),
+    .wd     (alert_class_shadowed_64_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class_shadowed[64].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_class_shadowed_64_qs),
+
+    // Shadow register phase. Relevant for hwext only.
+    .phase  (),
+
+    // Shadow register error conditions
+    .err_update  (alert_class_shadowed_64_update_err),
+    .err_storage (alert_class_shadowed_64_storage_err)
+  );
+
+
   // Subregister 0 of Multireg alert_cause
   // R[alert_cause_0]: V(False)
   prim_subreg #(
@@ -10787,6 +11039,62 @@
   );
 
 
+  // Subregister 63 of Multireg alert_cause
+  // R[alert_cause_63]: V(False)
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_63 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_cause_63_we),
+    .wd     (alert_cause_63_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[63].de),
+    .d      (hw2reg.alert_cause[63].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[63].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_cause_63_qs)
+  );
+
+
+  // Subregister 64 of Multireg alert_cause
+  // R[alert_cause_64]: V(False)
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_64 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_cause_64_we),
+    .wd     (alert_cause_64_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[64].de),
+    .d      (hw2reg.alert_cause[64].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[64].q),
+    .ds     (),
+
+    // to register interface (read)
+    .qs     (alert_cause_64_qs)
+  );
+
+
   // Subregister 0 of Multireg loc_alert_regwen
   // R[loc_alert_regwen_0]: V(False)
   prim_subreg #(
@@ -14875,7 +15183,7 @@
 
 
 
-  logic [341:0] addr_hit;
+  logic [349:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -14947,279 +15255,287 @@
     addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET);
     addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET);
     addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET);
-    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
-    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
-    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
-    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
-    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
-    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
-    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
-    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
-    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
-    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
-    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
-    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
-    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
-    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
-    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
-    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
-    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
-    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
-    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
-    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
-    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
-    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
-    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
-    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
-    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
-    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
-    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
-    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
-    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
-    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
-    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
-    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
-    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
-    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
-    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
-    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
-    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
-    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
-    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
-    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
-    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
-    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
-    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
-    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
-    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
-    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
-    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
-    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
-    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
-    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
-    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
-    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
-    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
-    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
-    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
-    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
-    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
-    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
-    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
-    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
-    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET);
-    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET);
-    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET);
-    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
-    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
-    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
-    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
-    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
-    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
-    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
-    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
-    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
-    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
-    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
-    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
-    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
-    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
-    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
-    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
-    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
-    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
-    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
-    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
-    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
-    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
-    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
-    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
-    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
-    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
-    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
-    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
-    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
-    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
-    addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
-    addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
-    addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
-    addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
-    addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
-    addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
-    addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
-    addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
-    addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
-    addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
-    addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
-    addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
-    addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
-    addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
-    addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
-    addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
-    addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
-    addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
-    addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
-    addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
-    addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
-    addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
-    addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
-    addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
-    addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
-    addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
-    addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
-    addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
-    addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
-    addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
-    addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET);
-    addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET);
-    addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET);
-    addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
-    addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
-    addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
-    addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
-    addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
-    addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
-    addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
-    addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
-    addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
-    addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
-    addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
-    addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
-    addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
-    addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
-    addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
-    addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
-    addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
-    addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
-    addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
-    addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
-    addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
-    addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
-    addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
-    addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
-    addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
-    addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
-    addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
-    addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
-    addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
-    addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
-    addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
-    addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
-    addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
-    addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
-    addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
-    addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
-    addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
-    addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
-    addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
-    addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
-    addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
-    addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
-    addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
-    addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
-    addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
-    addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
-    addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
-    addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
-    addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
-    addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
-    addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
-    addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
-    addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
-    addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
-    addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
-    addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
-    addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
-    addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
-    addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
-    addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
-    addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET);
-    addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET);
-    addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET);
-    addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
-    addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
-    addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
-    addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
-    addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
-    addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
-    addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
-    addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
-    addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
-    addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
-    addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
-    addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
-    addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
-    addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
-    addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
-    addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
-    addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
-    addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
-    addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
-    addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
-    addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
-    addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
-    addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
-    addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
-    addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
-    addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
-    addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
-    addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
-    addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
-    addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
-    addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
-    addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
-    addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
-    addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
-    addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
-    addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
-    addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
-    addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
-    addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
-    addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
-    addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
-    addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
-    addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
-    addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
-    addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
-    addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
-    addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
-    addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
-    addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
-    addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
-    addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
-    addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
-    addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
-    addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
-    addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
-    addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET);
+    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET);
+    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
+    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
+    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
+    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
+    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
+    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
+    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
+    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
+    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
+    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
+    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
+    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
+    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
+    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
+    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
+    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
+    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
+    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
+    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
+    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
+    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
+    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
+    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
+    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
+    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
+    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
+    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
+    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
+    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
+    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
+    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
+    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
+    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
+    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
+    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
+    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
+    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
+    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
+    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
+    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
+    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
+    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
+    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
+    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
+    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
+    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
+    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
+    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
+    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
+    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
+    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
+    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
+    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
+    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
+    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
+    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
+    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
+    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
+    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
+    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
+    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET);
+    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET);
+    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET);
+    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET);
+    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET);
+    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
+    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
+    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
+    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
+    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
+    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
+    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
+    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
+    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
+    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
+    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
+    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
+    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
+    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
+    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
+    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
+    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
+    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
+    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
+    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
+    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
+    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
+    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
+    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
+    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
+    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
+    addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
+    addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
+    addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
+    addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
+    addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
+    addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
+    addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
+    addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
+    addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
+    addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
+    addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
+    addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
+    addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
+    addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
+    addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
+    addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
+    addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
+    addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
+    addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
+    addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
+    addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
+    addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
+    addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
+    addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
+    addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
+    addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
+    addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
+    addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
+    addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
+    addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
+    addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
+    addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
+    addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
+    addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
+    addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET);
+    addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET);
+    addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET);
+    addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET);
+    addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET);
+    addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+    addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+    addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+    addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+    addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+    addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+    addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+    addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+    addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+    addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+    addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+    addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+    addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+    addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+    addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+    addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+    addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+    addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+    addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+    addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+    addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+    addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+    addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+    addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+    addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+    addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+    addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+    addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+    addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+    addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+    addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+    addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+    addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+    addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+    addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+    addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+    addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+    addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+    addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+    addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+    addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+    addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+    addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+    addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+    addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+    addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+    addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+    addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+    addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
+    addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
+    addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
+    addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
+    addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
+    addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
+    addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
+    addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
+    addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
+    addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
+    addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
+    addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
+    addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET);
+    addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET);
+    addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET);
+    addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET);
+    addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET);
+    addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+    addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+    addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+    addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+    addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+    addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
+    addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
+    addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
+    addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
+    addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
+    addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
+    addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
+    addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
+    addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
+    addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
+    addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
+    addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
+    addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
+    addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
+    addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
+    addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
+    addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+    addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+    addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+    addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+    addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+    addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
+    addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
+    addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+    addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
+    addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+    addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
+    addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+    addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+    addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+    addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+    addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
+    addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+    addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
+    addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+    addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+    addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+    addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+    addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
+    addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+    addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
+    addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+    addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+    addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+    addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+    addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
+    addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+    addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
+    addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+    addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+    addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -15568,7 +15884,15 @@
                (addr_hit[338] & (|(ALERT_HANDLER_PERMIT[338] & ~reg_be))) |
                (addr_hit[339] & (|(ALERT_HANDLER_PERMIT[339] & ~reg_be))) |
                (addr_hit[340] & (|(ALERT_HANDLER_PERMIT[340] & ~reg_be))) |
-               (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be)))));
+               (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))) |
+               (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) |
+               (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) |
+               (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) |
+               (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) |
+               (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) |
+               (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) |
+               (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) |
+               (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be)))));
   end
 
   // Generate write-enables
@@ -15799,802 +16123,830 @@
   assign alert_regwen_62_we = addr_hit[68] & reg_we & !reg_error;
 
   assign alert_regwen_62_wd = reg_wdata[0];
-  assign alert_en_shadowed_0_re = addr_hit[69] & reg_re & !reg_error;
-  assign alert_en_shadowed_0_we = addr_hit[69] & reg_we & !reg_error;
+  assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error;
+
+  assign alert_regwen_63_wd = reg_wdata[0];
+  assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error;
+
+  assign alert_regwen_64_wd = reg_wdata[0];
+  assign alert_en_shadowed_0_re = addr_hit[71] & reg_re & !reg_error;
+  assign alert_en_shadowed_0_we = addr_hit[71] & reg_we & !reg_error;
 
   assign alert_en_shadowed_0_wd = reg_wdata[0];
-  assign alert_en_shadowed_1_re = addr_hit[70] & reg_re & !reg_error;
-  assign alert_en_shadowed_1_we = addr_hit[70] & reg_we & !reg_error;
+  assign alert_en_shadowed_1_re = addr_hit[72] & reg_re & !reg_error;
+  assign alert_en_shadowed_1_we = addr_hit[72] & reg_we & !reg_error;
 
   assign alert_en_shadowed_1_wd = reg_wdata[0];
-  assign alert_en_shadowed_2_re = addr_hit[71] & reg_re & !reg_error;
-  assign alert_en_shadowed_2_we = addr_hit[71] & reg_we & !reg_error;
+  assign alert_en_shadowed_2_re = addr_hit[73] & reg_re & !reg_error;
+  assign alert_en_shadowed_2_we = addr_hit[73] & reg_we & !reg_error;
 
   assign alert_en_shadowed_2_wd = reg_wdata[0];
-  assign alert_en_shadowed_3_re = addr_hit[72] & reg_re & !reg_error;
-  assign alert_en_shadowed_3_we = addr_hit[72] & reg_we & !reg_error;
+  assign alert_en_shadowed_3_re = addr_hit[74] & reg_re & !reg_error;
+  assign alert_en_shadowed_3_we = addr_hit[74] & reg_we & !reg_error;
 
   assign alert_en_shadowed_3_wd = reg_wdata[0];
-  assign alert_en_shadowed_4_re = addr_hit[73] & reg_re & !reg_error;
-  assign alert_en_shadowed_4_we = addr_hit[73] & reg_we & !reg_error;
+  assign alert_en_shadowed_4_re = addr_hit[75] & reg_re & !reg_error;
+  assign alert_en_shadowed_4_we = addr_hit[75] & reg_we & !reg_error;
 
   assign alert_en_shadowed_4_wd = reg_wdata[0];
-  assign alert_en_shadowed_5_re = addr_hit[74] & reg_re & !reg_error;
-  assign alert_en_shadowed_5_we = addr_hit[74] & reg_we & !reg_error;
+  assign alert_en_shadowed_5_re = addr_hit[76] & reg_re & !reg_error;
+  assign alert_en_shadowed_5_we = addr_hit[76] & reg_we & !reg_error;
 
   assign alert_en_shadowed_5_wd = reg_wdata[0];
-  assign alert_en_shadowed_6_re = addr_hit[75] & reg_re & !reg_error;
-  assign alert_en_shadowed_6_we = addr_hit[75] & reg_we & !reg_error;
+  assign alert_en_shadowed_6_re = addr_hit[77] & reg_re & !reg_error;
+  assign alert_en_shadowed_6_we = addr_hit[77] & reg_we & !reg_error;
 
   assign alert_en_shadowed_6_wd = reg_wdata[0];
-  assign alert_en_shadowed_7_re = addr_hit[76] & reg_re & !reg_error;
-  assign alert_en_shadowed_7_we = addr_hit[76] & reg_we & !reg_error;
+  assign alert_en_shadowed_7_re = addr_hit[78] & reg_re & !reg_error;
+  assign alert_en_shadowed_7_we = addr_hit[78] & reg_we & !reg_error;
 
   assign alert_en_shadowed_7_wd = reg_wdata[0];
-  assign alert_en_shadowed_8_re = addr_hit[77] & reg_re & !reg_error;
-  assign alert_en_shadowed_8_we = addr_hit[77] & reg_we & !reg_error;
+  assign alert_en_shadowed_8_re = addr_hit[79] & reg_re & !reg_error;
+  assign alert_en_shadowed_8_we = addr_hit[79] & reg_we & !reg_error;
 
   assign alert_en_shadowed_8_wd = reg_wdata[0];
-  assign alert_en_shadowed_9_re = addr_hit[78] & reg_re & !reg_error;
-  assign alert_en_shadowed_9_we = addr_hit[78] & reg_we & !reg_error;
+  assign alert_en_shadowed_9_re = addr_hit[80] & reg_re & !reg_error;
+  assign alert_en_shadowed_9_we = addr_hit[80] & reg_we & !reg_error;
 
   assign alert_en_shadowed_9_wd = reg_wdata[0];
-  assign alert_en_shadowed_10_re = addr_hit[79] & reg_re & !reg_error;
-  assign alert_en_shadowed_10_we = addr_hit[79] & reg_we & !reg_error;
+  assign alert_en_shadowed_10_re = addr_hit[81] & reg_re & !reg_error;
+  assign alert_en_shadowed_10_we = addr_hit[81] & reg_we & !reg_error;
 
   assign alert_en_shadowed_10_wd = reg_wdata[0];
-  assign alert_en_shadowed_11_re = addr_hit[80] & reg_re & !reg_error;
-  assign alert_en_shadowed_11_we = addr_hit[80] & reg_we & !reg_error;
+  assign alert_en_shadowed_11_re = addr_hit[82] & reg_re & !reg_error;
+  assign alert_en_shadowed_11_we = addr_hit[82] & reg_we & !reg_error;
 
   assign alert_en_shadowed_11_wd = reg_wdata[0];
-  assign alert_en_shadowed_12_re = addr_hit[81] & reg_re & !reg_error;
-  assign alert_en_shadowed_12_we = addr_hit[81] & reg_we & !reg_error;
+  assign alert_en_shadowed_12_re = addr_hit[83] & reg_re & !reg_error;
+  assign alert_en_shadowed_12_we = addr_hit[83] & reg_we & !reg_error;
 
   assign alert_en_shadowed_12_wd = reg_wdata[0];
-  assign alert_en_shadowed_13_re = addr_hit[82] & reg_re & !reg_error;
-  assign alert_en_shadowed_13_we = addr_hit[82] & reg_we & !reg_error;
+  assign alert_en_shadowed_13_re = addr_hit[84] & reg_re & !reg_error;
+  assign alert_en_shadowed_13_we = addr_hit[84] & reg_we & !reg_error;
 
   assign alert_en_shadowed_13_wd = reg_wdata[0];
-  assign alert_en_shadowed_14_re = addr_hit[83] & reg_re & !reg_error;
-  assign alert_en_shadowed_14_we = addr_hit[83] & reg_we & !reg_error;
+  assign alert_en_shadowed_14_re = addr_hit[85] & reg_re & !reg_error;
+  assign alert_en_shadowed_14_we = addr_hit[85] & reg_we & !reg_error;
 
   assign alert_en_shadowed_14_wd = reg_wdata[0];
-  assign alert_en_shadowed_15_re = addr_hit[84] & reg_re & !reg_error;
-  assign alert_en_shadowed_15_we = addr_hit[84] & reg_we & !reg_error;
+  assign alert_en_shadowed_15_re = addr_hit[86] & reg_re & !reg_error;
+  assign alert_en_shadowed_15_we = addr_hit[86] & reg_we & !reg_error;
 
   assign alert_en_shadowed_15_wd = reg_wdata[0];
-  assign alert_en_shadowed_16_re = addr_hit[85] & reg_re & !reg_error;
-  assign alert_en_shadowed_16_we = addr_hit[85] & reg_we & !reg_error;
+  assign alert_en_shadowed_16_re = addr_hit[87] & reg_re & !reg_error;
+  assign alert_en_shadowed_16_we = addr_hit[87] & reg_we & !reg_error;
 
   assign alert_en_shadowed_16_wd = reg_wdata[0];
-  assign alert_en_shadowed_17_re = addr_hit[86] & reg_re & !reg_error;
-  assign alert_en_shadowed_17_we = addr_hit[86] & reg_we & !reg_error;
+  assign alert_en_shadowed_17_re = addr_hit[88] & reg_re & !reg_error;
+  assign alert_en_shadowed_17_we = addr_hit[88] & reg_we & !reg_error;
 
   assign alert_en_shadowed_17_wd = reg_wdata[0];
-  assign alert_en_shadowed_18_re = addr_hit[87] & reg_re & !reg_error;
-  assign alert_en_shadowed_18_we = addr_hit[87] & reg_we & !reg_error;
+  assign alert_en_shadowed_18_re = addr_hit[89] & reg_re & !reg_error;
+  assign alert_en_shadowed_18_we = addr_hit[89] & reg_we & !reg_error;
 
   assign alert_en_shadowed_18_wd = reg_wdata[0];
-  assign alert_en_shadowed_19_re = addr_hit[88] & reg_re & !reg_error;
-  assign alert_en_shadowed_19_we = addr_hit[88] & reg_we & !reg_error;
+  assign alert_en_shadowed_19_re = addr_hit[90] & reg_re & !reg_error;
+  assign alert_en_shadowed_19_we = addr_hit[90] & reg_we & !reg_error;
 
   assign alert_en_shadowed_19_wd = reg_wdata[0];
-  assign alert_en_shadowed_20_re = addr_hit[89] & reg_re & !reg_error;
-  assign alert_en_shadowed_20_we = addr_hit[89] & reg_we & !reg_error;
+  assign alert_en_shadowed_20_re = addr_hit[91] & reg_re & !reg_error;
+  assign alert_en_shadowed_20_we = addr_hit[91] & reg_we & !reg_error;
 
   assign alert_en_shadowed_20_wd = reg_wdata[0];
-  assign alert_en_shadowed_21_re = addr_hit[90] & reg_re & !reg_error;
-  assign alert_en_shadowed_21_we = addr_hit[90] & reg_we & !reg_error;
+  assign alert_en_shadowed_21_re = addr_hit[92] & reg_re & !reg_error;
+  assign alert_en_shadowed_21_we = addr_hit[92] & reg_we & !reg_error;
 
   assign alert_en_shadowed_21_wd = reg_wdata[0];
-  assign alert_en_shadowed_22_re = addr_hit[91] & reg_re & !reg_error;
-  assign alert_en_shadowed_22_we = addr_hit[91] & reg_we & !reg_error;
+  assign alert_en_shadowed_22_re = addr_hit[93] & reg_re & !reg_error;
+  assign alert_en_shadowed_22_we = addr_hit[93] & reg_we & !reg_error;
 
   assign alert_en_shadowed_22_wd = reg_wdata[0];
-  assign alert_en_shadowed_23_re = addr_hit[92] & reg_re & !reg_error;
-  assign alert_en_shadowed_23_we = addr_hit[92] & reg_we & !reg_error;
+  assign alert_en_shadowed_23_re = addr_hit[94] & reg_re & !reg_error;
+  assign alert_en_shadowed_23_we = addr_hit[94] & reg_we & !reg_error;
 
   assign alert_en_shadowed_23_wd = reg_wdata[0];
-  assign alert_en_shadowed_24_re = addr_hit[93] & reg_re & !reg_error;
-  assign alert_en_shadowed_24_we = addr_hit[93] & reg_we & !reg_error;
+  assign alert_en_shadowed_24_re = addr_hit[95] & reg_re & !reg_error;
+  assign alert_en_shadowed_24_we = addr_hit[95] & reg_we & !reg_error;
 
   assign alert_en_shadowed_24_wd = reg_wdata[0];
-  assign alert_en_shadowed_25_re = addr_hit[94] & reg_re & !reg_error;
-  assign alert_en_shadowed_25_we = addr_hit[94] & reg_we & !reg_error;
+  assign alert_en_shadowed_25_re = addr_hit[96] & reg_re & !reg_error;
+  assign alert_en_shadowed_25_we = addr_hit[96] & reg_we & !reg_error;
 
   assign alert_en_shadowed_25_wd = reg_wdata[0];
-  assign alert_en_shadowed_26_re = addr_hit[95] & reg_re & !reg_error;
-  assign alert_en_shadowed_26_we = addr_hit[95] & reg_we & !reg_error;
+  assign alert_en_shadowed_26_re = addr_hit[97] & reg_re & !reg_error;
+  assign alert_en_shadowed_26_we = addr_hit[97] & reg_we & !reg_error;
 
   assign alert_en_shadowed_26_wd = reg_wdata[0];
-  assign alert_en_shadowed_27_re = addr_hit[96] & reg_re & !reg_error;
-  assign alert_en_shadowed_27_we = addr_hit[96] & reg_we & !reg_error;
+  assign alert_en_shadowed_27_re = addr_hit[98] & reg_re & !reg_error;
+  assign alert_en_shadowed_27_we = addr_hit[98] & reg_we & !reg_error;
 
   assign alert_en_shadowed_27_wd = reg_wdata[0];
-  assign alert_en_shadowed_28_re = addr_hit[97] & reg_re & !reg_error;
-  assign alert_en_shadowed_28_we = addr_hit[97] & reg_we & !reg_error;
+  assign alert_en_shadowed_28_re = addr_hit[99] & reg_re & !reg_error;
+  assign alert_en_shadowed_28_we = addr_hit[99] & reg_we & !reg_error;
 
   assign alert_en_shadowed_28_wd = reg_wdata[0];
-  assign alert_en_shadowed_29_re = addr_hit[98] & reg_re & !reg_error;
-  assign alert_en_shadowed_29_we = addr_hit[98] & reg_we & !reg_error;
+  assign alert_en_shadowed_29_re = addr_hit[100] & reg_re & !reg_error;
+  assign alert_en_shadowed_29_we = addr_hit[100] & reg_we & !reg_error;
 
   assign alert_en_shadowed_29_wd = reg_wdata[0];
-  assign alert_en_shadowed_30_re = addr_hit[99] & reg_re & !reg_error;
-  assign alert_en_shadowed_30_we = addr_hit[99] & reg_we & !reg_error;
+  assign alert_en_shadowed_30_re = addr_hit[101] & reg_re & !reg_error;
+  assign alert_en_shadowed_30_we = addr_hit[101] & reg_we & !reg_error;
 
   assign alert_en_shadowed_30_wd = reg_wdata[0];
-  assign alert_en_shadowed_31_re = addr_hit[100] & reg_re & !reg_error;
-  assign alert_en_shadowed_31_we = addr_hit[100] & reg_we & !reg_error;
+  assign alert_en_shadowed_31_re = addr_hit[102] & reg_re & !reg_error;
+  assign alert_en_shadowed_31_we = addr_hit[102] & reg_we & !reg_error;
 
   assign alert_en_shadowed_31_wd = reg_wdata[0];
-  assign alert_en_shadowed_32_re = addr_hit[101] & reg_re & !reg_error;
-  assign alert_en_shadowed_32_we = addr_hit[101] & reg_we & !reg_error;
+  assign alert_en_shadowed_32_re = addr_hit[103] & reg_re & !reg_error;
+  assign alert_en_shadowed_32_we = addr_hit[103] & reg_we & !reg_error;
 
   assign alert_en_shadowed_32_wd = reg_wdata[0];
-  assign alert_en_shadowed_33_re = addr_hit[102] & reg_re & !reg_error;
-  assign alert_en_shadowed_33_we = addr_hit[102] & reg_we & !reg_error;
+  assign alert_en_shadowed_33_re = addr_hit[104] & reg_re & !reg_error;
+  assign alert_en_shadowed_33_we = addr_hit[104] & reg_we & !reg_error;
 
   assign alert_en_shadowed_33_wd = reg_wdata[0];
-  assign alert_en_shadowed_34_re = addr_hit[103] & reg_re & !reg_error;
-  assign alert_en_shadowed_34_we = addr_hit[103] & reg_we & !reg_error;
+  assign alert_en_shadowed_34_re = addr_hit[105] & reg_re & !reg_error;
+  assign alert_en_shadowed_34_we = addr_hit[105] & reg_we & !reg_error;
 
   assign alert_en_shadowed_34_wd = reg_wdata[0];
-  assign alert_en_shadowed_35_re = addr_hit[104] & reg_re & !reg_error;
-  assign alert_en_shadowed_35_we = addr_hit[104] & reg_we & !reg_error;
+  assign alert_en_shadowed_35_re = addr_hit[106] & reg_re & !reg_error;
+  assign alert_en_shadowed_35_we = addr_hit[106] & reg_we & !reg_error;
 
   assign alert_en_shadowed_35_wd = reg_wdata[0];
-  assign alert_en_shadowed_36_re = addr_hit[105] & reg_re & !reg_error;
-  assign alert_en_shadowed_36_we = addr_hit[105] & reg_we & !reg_error;
+  assign alert_en_shadowed_36_re = addr_hit[107] & reg_re & !reg_error;
+  assign alert_en_shadowed_36_we = addr_hit[107] & reg_we & !reg_error;
 
   assign alert_en_shadowed_36_wd = reg_wdata[0];
-  assign alert_en_shadowed_37_re = addr_hit[106] & reg_re & !reg_error;
-  assign alert_en_shadowed_37_we = addr_hit[106] & reg_we & !reg_error;
+  assign alert_en_shadowed_37_re = addr_hit[108] & reg_re & !reg_error;
+  assign alert_en_shadowed_37_we = addr_hit[108] & reg_we & !reg_error;
 
   assign alert_en_shadowed_37_wd = reg_wdata[0];
-  assign alert_en_shadowed_38_re = addr_hit[107] & reg_re & !reg_error;
-  assign alert_en_shadowed_38_we = addr_hit[107] & reg_we & !reg_error;
+  assign alert_en_shadowed_38_re = addr_hit[109] & reg_re & !reg_error;
+  assign alert_en_shadowed_38_we = addr_hit[109] & reg_we & !reg_error;
 
   assign alert_en_shadowed_38_wd = reg_wdata[0];
-  assign alert_en_shadowed_39_re = addr_hit[108] & reg_re & !reg_error;
-  assign alert_en_shadowed_39_we = addr_hit[108] & reg_we & !reg_error;
+  assign alert_en_shadowed_39_re = addr_hit[110] & reg_re & !reg_error;
+  assign alert_en_shadowed_39_we = addr_hit[110] & reg_we & !reg_error;
 
   assign alert_en_shadowed_39_wd = reg_wdata[0];
-  assign alert_en_shadowed_40_re = addr_hit[109] & reg_re & !reg_error;
-  assign alert_en_shadowed_40_we = addr_hit[109] & reg_we & !reg_error;
+  assign alert_en_shadowed_40_re = addr_hit[111] & reg_re & !reg_error;
+  assign alert_en_shadowed_40_we = addr_hit[111] & reg_we & !reg_error;
 
   assign alert_en_shadowed_40_wd = reg_wdata[0];
-  assign alert_en_shadowed_41_re = addr_hit[110] & reg_re & !reg_error;
-  assign alert_en_shadowed_41_we = addr_hit[110] & reg_we & !reg_error;
+  assign alert_en_shadowed_41_re = addr_hit[112] & reg_re & !reg_error;
+  assign alert_en_shadowed_41_we = addr_hit[112] & reg_we & !reg_error;
 
   assign alert_en_shadowed_41_wd = reg_wdata[0];
-  assign alert_en_shadowed_42_re = addr_hit[111] & reg_re & !reg_error;
-  assign alert_en_shadowed_42_we = addr_hit[111] & reg_we & !reg_error;
+  assign alert_en_shadowed_42_re = addr_hit[113] & reg_re & !reg_error;
+  assign alert_en_shadowed_42_we = addr_hit[113] & reg_we & !reg_error;
 
   assign alert_en_shadowed_42_wd = reg_wdata[0];
-  assign alert_en_shadowed_43_re = addr_hit[112] & reg_re & !reg_error;
-  assign alert_en_shadowed_43_we = addr_hit[112] & reg_we & !reg_error;
+  assign alert_en_shadowed_43_re = addr_hit[114] & reg_re & !reg_error;
+  assign alert_en_shadowed_43_we = addr_hit[114] & reg_we & !reg_error;
 
   assign alert_en_shadowed_43_wd = reg_wdata[0];
-  assign alert_en_shadowed_44_re = addr_hit[113] & reg_re & !reg_error;
-  assign alert_en_shadowed_44_we = addr_hit[113] & reg_we & !reg_error;
+  assign alert_en_shadowed_44_re = addr_hit[115] & reg_re & !reg_error;
+  assign alert_en_shadowed_44_we = addr_hit[115] & reg_we & !reg_error;
 
   assign alert_en_shadowed_44_wd = reg_wdata[0];
-  assign alert_en_shadowed_45_re = addr_hit[114] & reg_re & !reg_error;
-  assign alert_en_shadowed_45_we = addr_hit[114] & reg_we & !reg_error;
+  assign alert_en_shadowed_45_re = addr_hit[116] & reg_re & !reg_error;
+  assign alert_en_shadowed_45_we = addr_hit[116] & reg_we & !reg_error;
 
   assign alert_en_shadowed_45_wd = reg_wdata[0];
-  assign alert_en_shadowed_46_re = addr_hit[115] & reg_re & !reg_error;
-  assign alert_en_shadowed_46_we = addr_hit[115] & reg_we & !reg_error;
+  assign alert_en_shadowed_46_re = addr_hit[117] & reg_re & !reg_error;
+  assign alert_en_shadowed_46_we = addr_hit[117] & reg_we & !reg_error;
 
   assign alert_en_shadowed_46_wd = reg_wdata[0];
-  assign alert_en_shadowed_47_re = addr_hit[116] & reg_re & !reg_error;
-  assign alert_en_shadowed_47_we = addr_hit[116] & reg_we & !reg_error;
+  assign alert_en_shadowed_47_re = addr_hit[118] & reg_re & !reg_error;
+  assign alert_en_shadowed_47_we = addr_hit[118] & reg_we & !reg_error;
 
   assign alert_en_shadowed_47_wd = reg_wdata[0];
-  assign alert_en_shadowed_48_re = addr_hit[117] & reg_re & !reg_error;
-  assign alert_en_shadowed_48_we = addr_hit[117] & reg_we & !reg_error;
+  assign alert_en_shadowed_48_re = addr_hit[119] & reg_re & !reg_error;
+  assign alert_en_shadowed_48_we = addr_hit[119] & reg_we & !reg_error;
 
   assign alert_en_shadowed_48_wd = reg_wdata[0];
-  assign alert_en_shadowed_49_re = addr_hit[118] & reg_re & !reg_error;
-  assign alert_en_shadowed_49_we = addr_hit[118] & reg_we & !reg_error;
+  assign alert_en_shadowed_49_re = addr_hit[120] & reg_re & !reg_error;
+  assign alert_en_shadowed_49_we = addr_hit[120] & reg_we & !reg_error;
 
   assign alert_en_shadowed_49_wd = reg_wdata[0];
-  assign alert_en_shadowed_50_re = addr_hit[119] & reg_re & !reg_error;
-  assign alert_en_shadowed_50_we = addr_hit[119] & reg_we & !reg_error;
+  assign alert_en_shadowed_50_re = addr_hit[121] & reg_re & !reg_error;
+  assign alert_en_shadowed_50_we = addr_hit[121] & reg_we & !reg_error;
 
   assign alert_en_shadowed_50_wd = reg_wdata[0];
-  assign alert_en_shadowed_51_re = addr_hit[120] & reg_re & !reg_error;
-  assign alert_en_shadowed_51_we = addr_hit[120] & reg_we & !reg_error;
+  assign alert_en_shadowed_51_re = addr_hit[122] & reg_re & !reg_error;
+  assign alert_en_shadowed_51_we = addr_hit[122] & reg_we & !reg_error;
 
   assign alert_en_shadowed_51_wd = reg_wdata[0];
-  assign alert_en_shadowed_52_re = addr_hit[121] & reg_re & !reg_error;
-  assign alert_en_shadowed_52_we = addr_hit[121] & reg_we & !reg_error;
+  assign alert_en_shadowed_52_re = addr_hit[123] & reg_re & !reg_error;
+  assign alert_en_shadowed_52_we = addr_hit[123] & reg_we & !reg_error;
 
   assign alert_en_shadowed_52_wd = reg_wdata[0];
-  assign alert_en_shadowed_53_re = addr_hit[122] & reg_re & !reg_error;
-  assign alert_en_shadowed_53_we = addr_hit[122] & reg_we & !reg_error;
+  assign alert_en_shadowed_53_re = addr_hit[124] & reg_re & !reg_error;
+  assign alert_en_shadowed_53_we = addr_hit[124] & reg_we & !reg_error;
 
   assign alert_en_shadowed_53_wd = reg_wdata[0];
-  assign alert_en_shadowed_54_re = addr_hit[123] & reg_re & !reg_error;
-  assign alert_en_shadowed_54_we = addr_hit[123] & reg_we & !reg_error;
+  assign alert_en_shadowed_54_re = addr_hit[125] & reg_re & !reg_error;
+  assign alert_en_shadowed_54_we = addr_hit[125] & reg_we & !reg_error;
 
   assign alert_en_shadowed_54_wd = reg_wdata[0];
-  assign alert_en_shadowed_55_re = addr_hit[124] & reg_re & !reg_error;
-  assign alert_en_shadowed_55_we = addr_hit[124] & reg_we & !reg_error;
+  assign alert_en_shadowed_55_re = addr_hit[126] & reg_re & !reg_error;
+  assign alert_en_shadowed_55_we = addr_hit[126] & reg_we & !reg_error;
 
   assign alert_en_shadowed_55_wd = reg_wdata[0];
-  assign alert_en_shadowed_56_re = addr_hit[125] & reg_re & !reg_error;
-  assign alert_en_shadowed_56_we = addr_hit[125] & reg_we & !reg_error;
+  assign alert_en_shadowed_56_re = addr_hit[127] & reg_re & !reg_error;
+  assign alert_en_shadowed_56_we = addr_hit[127] & reg_we & !reg_error;
 
   assign alert_en_shadowed_56_wd = reg_wdata[0];
-  assign alert_en_shadowed_57_re = addr_hit[126] & reg_re & !reg_error;
-  assign alert_en_shadowed_57_we = addr_hit[126] & reg_we & !reg_error;
+  assign alert_en_shadowed_57_re = addr_hit[128] & reg_re & !reg_error;
+  assign alert_en_shadowed_57_we = addr_hit[128] & reg_we & !reg_error;
 
   assign alert_en_shadowed_57_wd = reg_wdata[0];
-  assign alert_en_shadowed_58_re = addr_hit[127] & reg_re & !reg_error;
-  assign alert_en_shadowed_58_we = addr_hit[127] & reg_we & !reg_error;
+  assign alert_en_shadowed_58_re = addr_hit[129] & reg_re & !reg_error;
+  assign alert_en_shadowed_58_we = addr_hit[129] & reg_we & !reg_error;
 
   assign alert_en_shadowed_58_wd = reg_wdata[0];
-  assign alert_en_shadowed_59_re = addr_hit[128] & reg_re & !reg_error;
-  assign alert_en_shadowed_59_we = addr_hit[128] & reg_we & !reg_error;
+  assign alert_en_shadowed_59_re = addr_hit[130] & reg_re & !reg_error;
+  assign alert_en_shadowed_59_we = addr_hit[130] & reg_we & !reg_error;
 
   assign alert_en_shadowed_59_wd = reg_wdata[0];
-  assign alert_en_shadowed_60_re = addr_hit[129] & reg_re & !reg_error;
-  assign alert_en_shadowed_60_we = addr_hit[129] & reg_we & !reg_error;
+  assign alert_en_shadowed_60_re = addr_hit[131] & reg_re & !reg_error;
+  assign alert_en_shadowed_60_we = addr_hit[131] & reg_we & !reg_error;
 
   assign alert_en_shadowed_60_wd = reg_wdata[0];
-  assign alert_en_shadowed_61_re = addr_hit[130] & reg_re & !reg_error;
-  assign alert_en_shadowed_61_we = addr_hit[130] & reg_we & !reg_error;
+  assign alert_en_shadowed_61_re = addr_hit[132] & reg_re & !reg_error;
+  assign alert_en_shadowed_61_we = addr_hit[132] & reg_we & !reg_error;
 
   assign alert_en_shadowed_61_wd = reg_wdata[0];
-  assign alert_en_shadowed_62_re = addr_hit[131] & reg_re & !reg_error;
-  assign alert_en_shadowed_62_we = addr_hit[131] & reg_we & !reg_error;
+  assign alert_en_shadowed_62_re = addr_hit[133] & reg_re & !reg_error;
+  assign alert_en_shadowed_62_we = addr_hit[133] & reg_we & !reg_error;
 
   assign alert_en_shadowed_62_wd = reg_wdata[0];
-  assign alert_class_shadowed_0_re = addr_hit[132] & reg_re & !reg_error;
-  assign alert_class_shadowed_0_we = addr_hit[132] & reg_we & !reg_error;
+  assign alert_en_shadowed_63_re = addr_hit[134] & reg_re & !reg_error;
+  assign alert_en_shadowed_63_we = addr_hit[134] & reg_we & !reg_error;
+
+  assign alert_en_shadowed_63_wd = reg_wdata[0];
+  assign alert_en_shadowed_64_re = addr_hit[135] & reg_re & !reg_error;
+  assign alert_en_shadowed_64_we = addr_hit[135] & reg_we & !reg_error;
+
+  assign alert_en_shadowed_64_wd = reg_wdata[0];
+  assign alert_class_shadowed_0_re = addr_hit[136] & reg_re & !reg_error;
+  assign alert_class_shadowed_0_we = addr_hit[136] & reg_we & !reg_error;
 
   assign alert_class_shadowed_0_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_1_re = addr_hit[133] & reg_re & !reg_error;
-  assign alert_class_shadowed_1_we = addr_hit[133] & reg_we & !reg_error;
+  assign alert_class_shadowed_1_re = addr_hit[137] & reg_re & !reg_error;
+  assign alert_class_shadowed_1_we = addr_hit[137] & reg_we & !reg_error;
 
   assign alert_class_shadowed_1_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_2_re = addr_hit[134] & reg_re & !reg_error;
-  assign alert_class_shadowed_2_we = addr_hit[134] & reg_we & !reg_error;
+  assign alert_class_shadowed_2_re = addr_hit[138] & reg_re & !reg_error;
+  assign alert_class_shadowed_2_we = addr_hit[138] & reg_we & !reg_error;
 
   assign alert_class_shadowed_2_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_3_re = addr_hit[135] & reg_re & !reg_error;
-  assign alert_class_shadowed_3_we = addr_hit[135] & reg_we & !reg_error;
+  assign alert_class_shadowed_3_re = addr_hit[139] & reg_re & !reg_error;
+  assign alert_class_shadowed_3_we = addr_hit[139] & reg_we & !reg_error;
 
   assign alert_class_shadowed_3_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_4_re = addr_hit[136] & reg_re & !reg_error;
-  assign alert_class_shadowed_4_we = addr_hit[136] & reg_we & !reg_error;
+  assign alert_class_shadowed_4_re = addr_hit[140] & reg_re & !reg_error;
+  assign alert_class_shadowed_4_we = addr_hit[140] & reg_we & !reg_error;
 
   assign alert_class_shadowed_4_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_5_re = addr_hit[137] & reg_re & !reg_error;
-  assign alert_class_shadowed_5_we = addr_hit[137] & reg_we & !reg_error;
+  assign alert_class_shadowed_5_re = addr_hit[141] & reg_re & !reg_error;
+  assign alert_class_shadowed_5_we = addr_hit[141] & reg_we & !reg_error;
 
   assign alert_class_shadowed_5_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_6_re = addr_hit[138] & reg_re & !reg_error;
-  assign alert_class_shadowed_6_we = addr_hit[138] & reg_we & !reg_error;
+  assign alert_class_shadowed_6_re = addr_hit[142] & reg_re & !reg_error;
+  assign alert_class_shadowed_6_we = addr_hit[142] & reg_we & !reg_error;
 
   assign alert_class_shadowed_6_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_7_re = addr_hit[139] & reg_re & !reg_error;
-  assign alert_class_shadowed_7_we = addr_hit[139] & reg_we & !reg_error;
+  assign alert_class_shadowed_7_re = addr_hit[143] & reg_re & !reg_error;
+  assign alert_class_shadowed_7_we = addr_hit[143] & reg_we & !reg_error;
 
   assign alert_class_shadowed_7_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_8_re = addr_hit[140] & reg_re & !reg_error;
-  assign alert_class_shadowed_8_we = addr_hit[140] & reg_we & !reg_error;
+  assign alert_class_shadowed_8_re = addr_hit[144] & reg_re & !reg_error;
+  assign alert_class_shadowed_8_we = addr_hit[144] & reg_we & !reg_error;
 
   assign alert_class_shadowed_8_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_9_re = addr_hit[141] & reg_re & !reg_error;
-  assign alert_class_shadowed_9_we = addr_hit[141] & reg_we & !reg_error;
+  assign alert_class_shadowed_9_re = addr_hit[145] & reg_re & !reg_error;
+  assign alert_class_shadowed_9_we = addr_hit[145] & reg_we & !reg_error;
 
   assign alert_class_shadowed_9_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_10_re = addr_hit[142] & reg_re & !reg_error;
-  assign alert_class_shadowed_10_we = addr_hit[142] & reg_we & !reg_error;
+  assign alert_class_shadowed_10_re = addr_hit[146] & reg_re & !reg_error;
+  assign alert_class_shadowed_10_we = addr_hit[146] & reg_we & !reg_error;
 
   assign alert_class_shadowed_10_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_11_re = addr_hit[143] & reg_re & !reg_error;
-  assign alert_class_shadowed_11_we = addr_hit[143] & reg_we & !reg_error;
+  assign alert_class_shadowed_11_re = addr_hit[147] & reg_re & !reg_error;
+  assign alert_class_shadowed_11_we = addr_hit[147] & reg_we & !reg_error;
 
   assign alert_class_shadowed_11_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_12_re = addr_hit[144] & reg_re & !reg_error;
-  assign alert_class_shadowed_12_we = addr_hit[144] & reg_we & !reg_error;
+  assign alert_class_shadowed_12_re = addr_hit[148] & reg_re & !reg_error;
+  assign alert_class_shadowed_12_we = addr_hit[148] & reg_we & !reg_error;
 
   assign alert_class_shadowed_12_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_13_re = addr_hit[145] & reg_re & !reg_error;
-  assign alert_class_shadowed_13_we = addr_hit[145] & reg_we & !reg_error;
+  assign alert_class_shadowed_13_re = addr_hit[149] & reg_re & !reg_error;
+  assign alert_class_shadowed_13_we = addr_hit[149] & reg_we & !reg_error;
 
   assign alert_class_shadowed_13_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_14_re = addr_hit[146] & reg_re & !reg_error;
-  assign alert_class_shadowed_14_we = addr_hit[146] & reg_we & !reg_error;
+  assign alert_class_shadowed_14_re = addr_hit[150] & reg_re & !reg_error;
+  assign alert_class_shadowed_14_we = addr_hit[150] & reg_we & !reg_error;
 
   assign alert_class_shadowed_14_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_15_re = addr_hit[147] & reg_re & !reg_error;
-  assign alert_class_shadowed_15_we = addr_hit[147] & reg_we & !reg_error;
+  assign alert_class_shadowed_15_re = addr_hit[151] & reg_re & !reg_error;
+  assign alert_class_shadowed_15_we = addr_hit[151] & reg_we & !reg_error;
 
   assign alert_class_shadowed_15_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_16_re = addr_hit[148] & reg_re & !reg_error;
-  assign alert_class_shadowed_16_we = addr_hit[148] & reg_we & !reg_error;
+  assign alert_class_shadowed_16_re = addr_hit[152] & reg_re & !reg_error;
+  assign alert_class_shadowed_16_we = addr_hit[152] & reg_we & !reg_error;
 
   assign alert_class_shadowed_16_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_17_re = addr_hit[149] & reg_re & !reg_error;
-  assign alert_class_shadowed_17_we = addr_hit[149] & reg_we & !reg_error;
+  assign alert_class_shadowed_17_re = addr_hit[153] & reg_re & !reg_error;
+  assign alert_class_shadowed_17_we = addr_hit[153] & reg_we & !reg_error;
 
   assign alert_class_shadowed_17_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_18_re = addr_hit[150] & reg_re & !reg_error;
-  assign alert_class_shadowed_18_we = addr_hit[150] & reg_we & !reg_error;
+  assign alert_class_shadowed_18_re = addr_hit[154] & reg_re & !reg_error;
+  assign alert_class_shadowed_18_we = addr_hit[154] & reg_we & !reg_error;
 
   assign alert_class_shadowed_18_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_19_re = addr_hit[151] & reg_re & !reg_error;
-  assign alert_class_shadowed_19_we = addr_hit[151] & reg_we & !reg_error;
+  assign alert_class_shadowed_19_re = addr_hit[155] & reg_re & !reg_error;
+  assign alert_class_shadowed_19_we = addr_hit[155] & reg_we & !reg_error;
 
   assign alert_class_shadowed_19_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_20_re = addr_hit[152] & reg_re & !reg_error;
-  assign alert_class_shadowed_20_we = addr_hit[152] & reg_we & !reg_error;
+  assign alert_class_shadowed_20_re = addr_hit[156] & reg_re & !reg_error;
+  assign alert_class_shadowed_20_we = addr_hit[156] & reg_we & !reg_error;
 
   assign alert_class_shadowed_20_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_21_re = addr_hit[153] & reg_re & !reg_error;
-  assign alert_class_shadowed_21_we = addr_hit[153] & reg_we & !reg_error;
+  assign alert_class_shadowed_21_re = addr_hit[157] & reg_re & !reg_error;
+  assign alert_class_shadowed_21_we = addr_hit[157] & reg_we & !reg_error;
 
   assign alert_class_shadowed_21_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_22_re = addr_hit[154] & reg_re & !reg_error;
-  assign alert_class_shadowed_22_we = addr_hit[154] & reg_we & !reg_error;
+  assign alert_class_shadowed_22_re = addr_hit[158] & reg_re & !reg_error;
+  assign alert_class_shadowed_22_we = addr_hit[158] & reg_we & !reg_error;
 
   assign alert_class_shadowed_22_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_23_re = addr_hit[155] & reg_re & !reg_error;
-  assign alert_class_shadowed_23_we = addr_hit[155] & reg_we & !reg_error;
+  assign alert_class_shadowed_23_re = addr_hit[159] & reg_re & !reg_error;
+  assign alert_class_shadowed_23_we = addr_hit[159] & reg_we & !reg_error;
 
   assign alert_class_shadowed_23_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_24_re = addr_hit[156] & reg_re & !reg_error;
-  assign alert_class_shadowed_24_we = addr_hit[156] & reg_we & !reg_error;
+  assign alert_class_shadowed_24_re = addr_hit[160] & reg_re & !reg_error;
+  assign alert_class_shadowed_24_we = addr_hit[160] & reg_we & !reg_error;
 
   assign alert_class_shadowed_24_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_25_re = addr_hit[157] & reg_re & !reg_error;
-  assign alert_class_shadowed_25_we = addr_hit[157] & reg_we & !reg_error;
+  assign alert_class_shadowed_25_re = addr_hit[161] & reg_re & !reg_error;
+  assign alert_class_shadowed_25_we = addr_hit[161] & reg_we & !reg_error;
 
   assign alert_class_shadowed_25_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_26_re = addr_hit[158] & reg_re & !reg_error;
-  assign alert_class_shadowed_26_we = addr_hit[158] & reg_we & !reg_error;
+  assign alert_class_shadowed_26_re = addr_hit[162] & reg_re & !reg_error;
+  assign alert_class_shadowed_26_we = addr_hit[162] & reg_we & !reg_error;
 
   assign alert_class_shadowed_26_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_27_re = addr_hit[159] & reg_re & !reg_error;
-  assign alert_class_shadowed_27_we = addr_hit[159] & reg_we & !reg_error;
+  assign alert_class_shadowed_27_re = addr_hit[163] & reg_re & !reg_error;
+  assign alert_class_shadowed_27_we = addr_hit[163] & reg_we & !reg_error;
 
   assign alert_class_shadowed_27_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_28_re = addr_hit[160] & reg_re & !reg_error;
-  assign alert_class_shadowed_28_we = addr_hit[160] & reg_we & !reg_error;
+  assign alert_class_shadowed_28_re = addr_hit[164] & reg_re & !reg_error;
+  assign alert_class_shadowed_28_we = addr_hit[164] & reg_we & !reg_error;
 
   assign alert_class_shadowed_28_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_29_re = addr_hit[161] & reg_re & !reg_error;
-  assign alert_class_shadowed_29_we = addr_hit[161] & reg_we & !reg_error;
+  assign alert_class_shadowed_29_re = addr_hit[165] & reg_re & !reg_error;
+  assign alert_class_shadowed_29_we = addr_hit[165] & reg_we & !reg_error;
 
   assign alert_class_shadowed_29_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_30_re = addr_hit[162] & reg_re & !reg_error;
-  assign alert_class_shadowed_30_we = addr_hit[162] & reg_we & !reg_error;
+  assign alert_class_shadowed_30_re = addr_hit[166] & reg_re & !reg_error;
+  assign alert_class_shadowed_30_we = addr_hit[166] & reg_we & !reg_error;
 
   assign alert_class_shadowed_30_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_31_re = addr_hit[163] & reg_re & !reg_error;
-  assign alert_class_shadowed_31_we = addr_hit[163] & reg_we & !reg_error;
+  assign alert_class_shadowed_31_re = addr_hit[167] & reg_re & !reg_error;
+  assign alert_class_shadowed_31_we = addr_hit[167] & reg_we & !reg_error;
 
   assign alert_class_shadowed_31_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_32_re = addr_hit[164] & reg_re & !reg_error;
-  assign alert_class_shadowed_32_we = addr_hit[164] & reg_we & !reg_error;
+  assign alert_class_shadowed_32_re = addr_hit[168] & reg_re & !reg_error;
+  assign alert_class_shadowed_32_we = addr_hit[168] & reg_we & !reg_error;
 
   assign alert_class_shadowed_32_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_33_re = addr_hit[165] & reg_re & !reg_error;
-  assign alert_class_shadowed_33_we = addr_hit[165] & reg_we & !reg_error;
+  assign alert_class_shadowed_33_re = addr_hit[169] & reg_re & !reg_error;
+  assign alert_class_shadowed_33_we = addr_hit[169] & reg_we & !reg_error;
 
   assign alert_class_shadowed_33_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_34_re = addr_hit[166] & reg_re & !reg_error;
-  assign alert_class_shadowed_34_we = addr_hit[166] & reg_we & !reg_error;
+  assign alert_class_shadowed_34_re = addr_hit[170] & reg_re & !reg_error;
+  assign alert_class_shadowed_34_we = addr_hit[170] & reg_we & !reg_error;
 
   assign alert_class_shadowed_34_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_35_re = addr_hit[167] & reg_re & !reg_error;
-  assign alert_class_shadowed_35_we = addr_hit[167] & reg_we & !reg_error;
+  assign alert_class_shadowed_35_re = addr_hit[171] & reg_re & !reg_error;
+  assign alert_class_shadowed_35_we = addr_hit[171] & reg_we & !reg_error;
 
   assign alert_class_shadowed_35_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_36_re = addr_hit[168] & reg_re & !reg_error;
-  assign alert_class_shadowed_36_we = addr_hit[168] & reg_we & !reg_error;
+  assign alert_class_shadowed_36_re = addr_hit[172] & reg_re & !reg_error;
+  assign alert_class_shadowed_36_we = addr_hit[172] & reg_we & !reg_error;
 
   assign alert_class_shadowed_36_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_37_re = addr_hit[169] & reg_re & !reg_error;
-  assign alert_class_shadowed_37_we = addr_hit[169] & reg_we & !reg_error;
+  assign alert_class_shadowed_37_re = addr_hit[173] & reg_re & !reg_error;
+  assign alert_class_shadowed_37_we = addr_hit[173] & reg_we & !reg_error;
 
   assign alert_class_shadowed_37_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_38_re = addr_hit[170] & reg_re & !reg_error;
-  assign alert_class_shadowed_38_we = addr_hit[170] & reg_we & !reg_error;
+  assign alert_class_shadowed_38_re = addr_hit[174] & reg_re & !reg_error;
+  assign alert_class_shadowed_38_we = addr_hit[174] & reg_we & !reg_error;
 
   assign alert_class_shadowed_38_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_39_re = addr_hit[171] & reg_re & !reg_error;
-  assign alert_class_shadowed_39_we = addr_hit[171] & reg_we & !reg_error;
+  assign alert_class_shadowed_39_re = addr_hit[175] & reg_re & !reg_error;
+  assign alert_class_shadowed_39_we = addr_hit[175] & reg_we & !reg_error;
 
   assign alert_class_shadowed_39_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_40_re = addr_hit[172] & reg_re & !reg_error;
-  assign alert_class_shadowed_40_we = addr_hit[172] & reg_we & !reg_error;
+  assign alert_class_shadowed_40_re = addr_hit[176] & reg_re & !reg_error;
+  assign alert_class_shadowed_40_we = addr_hit[176] & reg_we & !reg_error;
 
   assign alert_class_shadowed_40_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_41_re = addr_hit[173] & reg_re & !reg_error;
-  assign alert_class_shadowed_41_we = addr_hit[173] & reg_we & !reg_error;
+  assign alert_class_shadowed_41_re = addr_hit[177] & reg_re & !reg_error;
+  assign alert_class_shadowed_41_we = addr_hit[177] & reg_we & !reg_error;
 
   assign alert_class_shadowed_41_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_42_re = addr_hit[174] & reg_re & !reg_error;
-  assign alert_class_shadowed_42_we = addr_hit[174] & reg_we & !reg_error;
+  assign alert_class_shadowed_42_re = addr_hit[178] & reg_re & !reg_error;
+  assign alert_class_shadowed_42_we = addr_hit[178] & reg_we & !reg_error;
 
   assign alert_class_shadowed_42_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_43_re = addr_hit[175] & reg_re & !reg_error;
-  assign alert_class_shadowed_43_we = addr_hit[175] & reg_we & !reg_error;
+  assign alert_class_shadowed_43_re = addr_hit[179] & reg_re & !reg_error;
+  assign alert_class_shadowed_43_we = addr_hit[179] & reg_we & !reg_error;
 
   assign alert_class_shadowed_43_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_44_re = addr_hit[176] & reg_re & !reg_error;
-  assign alert_class_shadowed_44_we = addr_hit[176] & reg_we & !reg_error;
+  assign alert_class_shadowed_44_re = addr_hit[180] & reg_re & !reg_error;
+  assign alert_class_shadowed_44_we = addr_hit[180] & reg_we & !reg_error;
 
   assign alert_class_shadowed_44_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_45_re = addr_hit[177] & reg_re & !reg_error;
-  assign alert_class_shadowed_45_we = addr_hit[177] & reg_we & !reg_error;
+  assign alert_class_shadowed_45_re = addr_hit[181] & reg_re & !reg_error;
+  assign alert_class_shadowed_45_we = addr_hit[181] & reg_we & !reg_error;
 
   assign alert_class_shadowed_45_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_46_re = addr_hit[178] & reg_re & !reg_error;
-  assign alert_class_shadowed_46_we = addr_hit[178] & reg_we & !reg_error;
+  assign alert_class_shadowed_46_re = addr_hit[182] & reg_re & !reg_error;
+  assign alert_class_shadowed_46_we = addr_hit[182] & reg_we & !reg_error;
 
   assign alert_class_shadowed_46_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_47_re = addr_hit[179] & reg_re & !reg_error;
-  assign alert_class_shadowed_47_we = addr_hit[179] & reg_we & !reg_error;
+  assign alert_class_shadowed_47_re = addr_hit[183] & reg_re & !reg_error;
+  assign alert_class_shadowed_47_we = addr_hit[183] & reg_we & !reg_error;
 
   assign alert_class_shadowed_47_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_48_re = addr_hit[180] & reg_re & !reg_error;
-  assign alert_class_shadowed_48_we = addr_hit[180] & reg_we & !reg_error;
+  assign alert_class_shadowed_48_re = addr_hit[184] & reg_re & !reg_error;
+  assign alert_class_shadowed_48_we = addr_hit[184] & reg_we & !reg_error;
 
   assign alert_class_shadowed_48_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_49_re = addr_hit[181] & reg_re & !reg_error;
-  assign alert_class_shadowed_49_we = addr_hit[181] & reg_we & !reg_error;
+  assign alert_class_shadowed_49_re = addr_hit[185] & reg_re & !reg_error;
+  assign alert_class_shadowed_49_we = addr_hit[185] & reg_we & !reg_error;
 
   assign alert_class_shadowed_49_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_50_re = addr_hit[182] & reg_re & !reg_error;
-  assign alert_class_shadowed_50_we = addr_hit[182] & reg_we & !reg_error;
+  assign alert_class_shadowed_50_re = addr_hit[186] & reg_re & !reg_error;
+  assign alert_class_shadowed_50_we = addr_hit[186] & reg_we & !reg_error;
 
   assign alert_class_shadowed_50_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_51_re = addr_hit[183] & reg_re & !reg_error;
-  assign alert_class_shadowed_51_we = addr_hit[183] & reg_we & !reg_error;
+  assign alert_class_shadowed_51_re = addr_hit[187] & reg_re & !reg_error;
+  assign alert_class_shadowed_51_we = addr_hit[187] & reg_we & !reg_error;
 
   assign alert_class_shadowed_51_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_52_re = addr_hit[184] & reg_re & !reg_error;
-  assign alert_class_shadowed_52_we = addr_hit[184] & reg_we & !reg_error;
+  assign alert_class_shadowed_52_re = addr_hit[188] & reg_re & !reg_error;
+  assign alert_class_shadowed_52_we = addr_hit[188] & reg_we & !reg_error;
 
   assign alert_class_shadowed_52_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_53_re = addr_hit[185] & reg_re & !reg_error;
-  assign alert_class_shadowed_53_we = addr_hit[185] & reg_we & !reg_error;
+  assign alert_class_shadowed_53_re = addr_hit[189] & reg_re & !reg_error;
+  assign alert_class_shadowed_53_we = addr_hit[189] & reg_we & !reg_error;
 
   assign alert_class_shadowed_53_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_54_re = addr_hit[186] & reg_re & !reg_error;
-  assign alert_class_shadowed_54_we = addr_hit[186] & reg_we & !reg_error;
+  assign alert_class_shadowed_54_re = addr_hit[190] & reg_re & !reg_error;
+  assign alert_class_shadowed_54_we = addr_hit[190] & reg_we & !reg_error;
 
   assign alert_class_shadowed_54_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_55_re = addr_hit[187] & reg_re & !reg_error;
-  assign alert_class_shadowed_55_we = addr_hit[187] & reg_we & !reg_error;
+  assign alert_class_shadowed_55_re = addr_hit[191] & reg_re & !reg_error;
+  assign alert_class_shadowed_55_we = addr_hit[191] & reg_we & !reg_error;
 
   assign alert_class_shadowed_55_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_56_re = addr_hit[188] & reg_re & !reg_error;
-  assign alert_class_shadowed_56_we = addr_hit[188] & reg_we & !reg_error;
+  assign alert_class_shadowed_56_re = addr_hit[192] & reg_re & !reg_error;
+  assign alert_class_shadowed_56_we = addr_hit[192] & reg_we & !reg_error;
 
   assign alert_class_shadowed_56_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_57_re = addr_hit[189] & reg_re & !reg_error;
-  assign alert_class_shadowed_57_we = addr_hit[189] & reg_we & !reg_error;
+  assign alert_class_shadowed_57_re = addr_hit[193] & reg_re & !reg_error;
+  assign alert_class_shadowed_57_we = addr_hit[193] & reg_we & !reg_error;
 
   assign alert_class_shadowed_57_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_58_re = addr_hit[190] & reg_re & !reg_error;
-  assign alert_class_shadowed_58_we = addr_hit[190] & reg_we & !reg_error;
+  assign alert_class_shadowed_58_re = addr_hit[194] & reg_re & !reg_error;
+  assign alert_class_shadowed_58_we = addr_hit[194] & reg_we & !reg_error;
 
   assign alert_class_shadowed_58_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_59_re = addr_hit[191] & reg_re & !reg_error;
-  assign alert_class_shadowed_59_we = addr_hit[191] & reg_we & !reg_error;
+  assign alert_class_shadowed_59_re = addr_hit[195] & reg_re & !reg_error;
+  assign alert_class_shadowed_59_we = addr_hit[195] & reg_we & !reg_error;
 
   assign alert_class_shadowed_59_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_60_re = addr_hit[192] & reg_re & !reg_error;
-  assign alert_class_shadowed_60_we = addr_hit[192] & reg_we & !reg_error;
+  assign alert_class_shadowed_60_re = addr_hit[196] & reg_re & !reg_error;
+  assign alert_class_shadowed_60_we = addr_hit[196] & reg_we & !reg_error;
 
   assign alert_class_shadowed_60_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_61_re = addr_hit[193] & reg_re & !reg_error;
-  assign alert_class_shadowed_61_we = addr_hit[193] & reg_we & !reg_error;
+  assign alert_class_shadowed_61_re = addr_hit[197] & reg_re & !reg_error;
+  assign alert_class_shadowed_61_we = addr_hit[197] & reg_we & !reg_error;
 
   assign alert_class_shadowed_61_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_62_re = addr_hit[194] & reg_re & !reg_error;
-  assign alert_class_shadowed_62_we = addr_hit[194] & reg_we & !reg_error;
+  assign alert_class_shadowed_62_re = addr_hit[198] & reg_re & !reg_error;
+  assign alert_class_shadowed_62_we = addr_hit[198] & reg_we & !reg_error;
 
   assign alert_class_shadowed_62_wd = reg_wdata[1:0];
-  assign alert_cause_0_we = addr_hit[195] & reg_we & !reg_error;
+  assign alert_class_shadowed_63_re = addr_hit[199] & reg_re & !reg_error;
+  assign alert_class_shadowed_63_we = addr_hit[199] & reg_we & !reg_error;
+
+  assign alert_class_shadowed_63_wd = reg_wdata[1:0];
+  assign alert_class_shadowed_64_re = addr_hit[200] & reg_re & !reg_error;
+  assign alert_class_shadowed_64_we = addr_hit[200] & reg_we & !reg_error;
+
+  assign alert_class_shadowed_64_wd = reg_wdata[1:0];
+  assign alert_cause_0_we = addr_hit[201] & reg_we & !reg_error;
 
   assign alert_cause_0_wd = reg_wdata[0];
-  assign alert_cause_1_we = addr_hit[196] & reg_we & !reg_error;
+  assign alert_cause_1_we = addr_hit[202] & reg_we & !reg_error;
 
   assign alert_cause_1_wd = reg_wdata[0];
-  assign alert_cause_2_we = addr_hit[197] & reg_we & !reg_error;
+  assign alert_cause_2_we = addr_hit[203] & reg_we & !reg_error;
 
   assign alert_cause_2_wd = reg_wdata[0];
-  assign alert_cause_3_we = addr_hit[198] & reg_we & !reg_error;
+  assign alert_cause_3_we = addr_hit[204] & reg_we & !reg_error;
 
   assign alert_cause_3_wd = reg_wdata[0];
-  assign alert_cause_4_we = addr_hit[199] & reg_we & !reg_error;
+  assign alert_cause_4_we = addr_hit[205] & reg_we & !reg_error;
 
   assign alert_cause_4_wd = reg_wdata[0];
-  assign alert_cause_5_we = addr_hit[200] & reg_we & !reg_error;
+  assign alert_cause_5_we = addr_hit[206] & reg_we & !reg_error;
 
   assign alert_cause_5_wd = reg_wdata[0];
-  assign alert_cause_6_we = addr_hit[201] & reg_we & !reg_error;
+  assign alert_cause_6_we = addr_hit[207] & reg_we & !reg_error;
 
   assign alert_cause_6_wd = reg_wdata[0];
-  assign alert_cause_7_we = addr_hit[202] & reg_we & !reg_error;
+  assign alert_cause_7_we = addr_hit[208] & reg_we & !reg_error;
 
   assign alert_cause_7_wd = reg_wdata[0];
-  assign alert_cause_8_we = addr_hit[203] & reg_we & !reg_error;
+  assign alert_cause_8_we = addr_hit[209] & reg_we & !reg_error;
 
   assign alert_cause_8_wd = reg_wdata[0];
-  assign alert_cause_9_we = addr_hit[204] & reg_we & !reg_error;
+  assign alert_cause_9_we = addr_hit[210] & reg_we & !reg_error;
 
   assign alert_cause_9_wd = reg_wdata[0];
-  assign alert_cause_10_we = addr_hit[205] & reg_we & !reg_error;
+  assign alert_cause_10_we = addr_hit[211] & reg_we & !reg_error;
 
   assign alert_cause_10_wd = reg_wdata[0];
-  assign alert_cause_11_we = addr_hit[206] & reg_we & !reg_error;
+  assign alert_cause_11_we = addr_hit[212] & reg_we & !reg_error;
 
   assign alert_cause_11_wd = reg_wdata[0];
-  assign alert_cause_12_we = addr_hit[207] & reg_we & !reg_error;
+  assign alert_cause_12_we = addr_hit[213] & reg_we & !reg_error;
 
   assign alert_cause_12_wd = reg_wdata[0];
-  assign alert_cause_13_we = addr_hit[208] & reg_we & !reg_error;
+  assign alert_cause_13_we = addr_hit[214] & reg_we & !reg_error;
 
   assign alert_cause_13_wd = reg_wdata[0];
-  assign alert_cause_14_we = addr_hit[209] & reg_we & !reg_error;
+  assign alert_cause_14_we = addr_hit[215] & reg_we & !reg_error;
 
   assign alert_cause_14_wd = reg_wdata[0];
-  assign alert_cause_15_we = addr_hit[210] & reg_we & !reg_error;
+  assign alert_cause_15_we = addr_hit[216] & reg_we & !reg_error;
 
   assign alert_cause_15_wd = reg_wdata[0];
-  assign alert_cause_16_we = addr_hit[211] & reg_we & !reg_error;
+  assign alert_cause_16_we = addr_hit[217] & reg_we & !reg_error;
 
   assign alert_cause_16_wd = reg_wdata[0];
-  assign alert_cause_17_we = addr_hit[212] & reg_we & !reg_error;
+  assign alert_cause_17_we = addr_hit[218] & reg_we & !reg_error;
 
   assign alert_cause_17_wd = reg_wdata[0];
-  assign alert_cause_18_we = addr_hit[213] & reg_we & !reg_error;
+  assign alert_cause_18_we = addr_hit[219] & reg_we & !reg_error;
 
   assign alert_cause_18_wd = reg_wdata[0];
-  assign alert_cause_19_we = addr_hit[214] & reg_we & !reg_error;
+  assign alert_cause_19_we = addr_hit[220] & reg_we & !reg_error;
 
   assign alert_cause_19_wd = reg_wdata[0];
-  assign alert_cause_20_we = addr_hit[215] & reg_we & !reg_error;
+  assign alert_cause_20_we = addr_hit[221] & reg_we & !reg_error;
 
   assign alert_cause_20_wd = reg_wdata[0];
-  assign alert_cause_21_we = addr_hit[216] & reg_we & !reg_error;
+  assign alert_cause_21_we = addr_hit[222] & reg_we & !reg_error;
 
   assign alert_cause_21_wd = reg_wdata[0];
-  assign alert_cause_22_we = addr_hit[217] & reg_we & !reg_error;
+  assign alert_cause_22_we = addr_hit[223] & reg_we & !reg_error;
 
   assign alert_cause_22_wd = reg_wdata[0];
-  assign alert_cause_23_we = addr_hit[218] & reg_we & !reg_error;
+  assign alert_cause_23_we = addr_hit[224] & reg_we & !reg_error;
 
   assign alert_cause_23_wd = reg_wdata[0];
-  assign alert_cause_24_we = addr_hit[219] & reg_we & !reg_error;
+  assign alert_cause_24_we = addr_hit[225] & reg_we & !reg_error;
 
   assign alert_cause_24_wd = reg_wdata[0];
-  assign alert_cause_25_we = addr_hit[220] & reg_we & !reg_error;
+  assign alert_cause_25_we = addr_hit[226] & reg_we & !reg_error;
 
   assign alert_cause_25_wd = reg_wdata[0];
-  assign alert_cause_26_we = addr_hit[221] & reg_we & !reg_error;
+  assign alert_cause_26_we = addr_hit[227] & reg_we & !reg_error;
 
   assign alert_cause_26_wd = reg_wdata[0];
-  assign alert_cause_27_we = addr_hit[222] & reg_we & !reg_error;
+  assign alert_cause_27_we = addr_hit[228] & reg_we & !reg_error;
 
   assign alert_cause_27_wd = reg_wdata[0];
-  assign alert_cause_28_we = addr_hit[223] & reg_we & !reg_error;
+  assign alert_cause_28_we = addr_hit[229] & reg_we & !reg_error;
 
   assign alert_cause_28_wd = reg_wdata[0];
-  assign alert_cause_29_we = addr_hit[224] & reg_we & !reg_error;
+  assign alert_cause_29_we = addr_hit[230] & reg_we & !reg_error;
 
   assign alert_cause_29_wd = reg_wdata[0];
-  assign alert_cause_30_we = addr_hit[225] & reg_we & !reg_error;
+  assign alert_cause_30_we = addr_hit[231] & reg_we & !reg_error;
 
   assign alert_cause_30_wd = reg_wdata[0];
-  assign alert_cause_31_we = addr_hit[226] & reg_we & !reg_error;
+  assign alert_cause_31_we = addr_hit[232] & reg_we & !reg_error;
 
   assign alert_cause_31_wd = reg_wdata[0];
-  assign alert_cause_32_we = addr_hit[227] & reg_we & !reg_error;
+  assign alert_cause_32_we = addr_hit[233] & reg_we & !reg_error;
 
   assign alert_cause_32_wd = reg_wdata[0];
-  assign alert_cause_33_we = addr_hit[228] & reg_we & !reg_error;
+  assign alert_cause_33_we = addr_hit[234] & reg_we & !reg_error;
 
   assign alert_cause_33_wd = reg_wdata[0];
-  assign alert_cause_34_we = addr_hit[229] & reg_we & !reg_error;
+  assign alert_cause_34_we = addr_hit[235] & reg_we & !reg_error;
 
   assign alert_cause_34_wd = reg_wdata[0];
-  assign alert_cause_35_we = addr_hit[230] & reg_we & !reg_error;
+  assign alert_cause_35_we = addr_hit[236] & reg_we & !reg_error;
 
   assign alert_cause_35_wd = reg_wdata[0];
-  assign alert_cause_36_we = addr_hit[231] & reg_we & !reg_error;
+  assign alert_cause_36_we = addr_hit[237] & reg_we & !reg_error;
 
   assign alert_cause_36_wd = reg_wdata[0];
-  assign alert_cause_37_we = addr_hit[232] & reg_we & !reg_error;
+  assign alert_cause_37_we = addr_hit[238] & reg_we & !reg_error;
 
   assign alert_cause_37_wd = reg_wdata[0];
-  assign alert_cause_38_we = addr_hit[233] & reg_we & !reg_error;
+  assign alert_cause_38_we = addr_hit[239] & reg_we & !reg_error;
 
   assign alert_cause_38_wd = reg_wdata[0];
-  assign alert_cause_39_we = addr_hit[234] & reg_we & !reg_error;
+  assign alert_cause_39_we = addr_hit[240] & reg_we & !reg_error;
 
   assign alert_cause_39_wd = reg_wdata[0];
-  assign alert_cause_40_we = addr_hit[235] & reg_we & !reg_error;
+  assign alert_cause_40_we = addr_hit[241] & reg_we & !reg_error;
 
   assign alert_cause_40_wd = reg_wdata[0];
-  assign alert_cause_41_we = addr_hit[236] & reg_we & !reg_error;
+  assign alert_cause_41_we = addr_hit[242] & reg_we & !reg_error;
 
   assign alert_cause_41_wd = reg_wdata[0];
-  assign alert_cause_42_we = addr_hit[237] & reg_we & !reg_error;
+  assign alert_cause_42_we = addr_hit[243] & reg_we & !reg_error;
 
   assign alert_cause_42_wd = reg_wdata[0];
-  assign alert_cause_43_we = addr_hit[238] & reg_we & !reg_error;
+  assign alert_cause_43_we = addr_hit[244] & reg_we & !reg_error;
 
   assign alert_cause_43_wd = reg_wdata[0];
-  assign alert_cause_44_we = addr_hit[239] & reg_we & !reg_error;
+  assign alert_cause_44_we = addr_hit[245] & reg_we & !reg_error;
 
   assign alert_cause_44_wd = reg_wdata[0];
-  assign alert_cause_45_we = addr_hit[240] & reg_we & !reg_error;
+  assign alert_cause_45_we = addr_hit[246] & reg_we & !reg_error;
 
   assign alert_cause_45_wd = reg_wdata[0];
-  assign alert_cause_46_we = addr_hit[241] & reg_we & !reg_error;
+  assign alert_cause_46_we = addr_hit[247] & reg_we & !reg_error;
 
   assign alert_cause_46_wd = reg_wdata[0];
-  assign alert_cause_47_we = addr_hit[242] & reg_we & !reg_error;
+  assign alert_cause_47_we = addr_hit[248] & reg_we & !reg_error;
 
   assign alert_cause_47_wd = reg_wdata[0];
-  assign alert_cause_48_we = addr_hit[243] & reg_we & !reg_error;
+  assign alert_cause_48_we = addr_hit[249] & reg_we & !reg_error;
 
   assign alert_cause_48_wd = reg_wdata[0];
-  assign alert_cause_49_we = addr_hit[244] & reg_we & !reg_error;
+  assign alert_cause_49_we = addr_hit[250] & reg_we & !reg_error;
 
   assign alert_cause_49_wd = reg_wdata[0];
-  assign alert_cause_50_we = addr_hit[245] & reg_we & !reg_error;
+  assign alert_cause_50_we = addr_hit[251] & reg_we & !reg_error;
 
   assign alert_cause_50_wd = reg_wdata[0];
-  assign alert_cause_51_we = addr_hit[246] & reg_we & !reg_error;
+  assign alert_cause_51_we = addr_hit[252] & reg_we & !reg_error;
 
   assign alert_cause_51_wd = reg_wdata[0];
-  assign alert_cause_52_we = addr_hit[247] & reg_we & !reg_error;
+  assign alert_cause_52_we = addr_hit[253] & reg_we & !reg_error;
 
   assign alert_cause_52_wd = reg_wdata[0];
-  assign alert_cause_53_we = addr_hit[248] & reg_we & !reg_error;
+  assign alert_cause_53_we = addr_hit[254] & reg_we & !reg_error;
 
   assign alert_cause_53_wd = reg_wdata[0];
-  assign alert_cause_54_we = addr_hit[249] & reg_we & !reg_error;
+  assign alert_cause_54_we = addr_hit[255] & reg_we & !reg_error;
 
   assign alert_cause_54_wd = reg_wdata[0];
-  assign alert_cause_55_we = addr_hit[250] & reg_we & !reg_error;
+  assign alert_cause_55_we = addr_hit[256] & reg_we & !reg_error;
 
   assign alert_cause_55_wd = reg_wdata[0];
-  assign alert_cause_56_we = addr_hit[251] & reg_we & !reg_error;
+  assign alert_cause_56_we = addr_hit[257] & reg_we & !reg_error;
 
   assign alert_cause_56_wd = reg_wdata[0];
-  assign alert_cause_57_we = addr_hit[252] & reg_we & !reg_error;
+  assign alert_cause_57_we = addr_hit[258] & reg_we & !reg_error;
 
   assign alert_cause_57_wd = reg_wdata[0];
-  assign alert_cause_58_we = addr_hit[253] & reg_we & !reg_error;
+  assign alert_cause_58_we = addr_hit[259] & reg_we & !reg_error;
 
   assign alert_cause_58_wd = reg_wdata[0];
-  assign alert_cause_59_we = addr_hit[254] & reg_we & !reg_error;
+  assign alert_cause_59_we = addr_hit[260] & reg_we & !reg_error;
 
   assign alert_cause_59_wd = reg_wdata[0];
-  assign alert_cause_60_we = addr_hit[255] & reg_we & !reg_error;
+  assign alert_cause_60_we = addr_hit[261] & reg_we & !reg_error;
 
   assign alert_cause_60_wd = reg_wdata[0];
-  assign alert_cause_61_we = addr_hit[256] & reg_we & !reg_error;
+  assign alert_cause_61_we = addr_hit[262] & reg_we & !reg_error;
 
   assign alert_cause_61_wd = reg_wdata[0];
-  assign alert_cause_62_we = addr_hit[257] & reg_we & !reg_error;
+  assign alert_cause_62_we = addr_hit[263] & reg_we & !reg_error;
 
   assign alert_cause_62_wd = reg_wdata[0];
-  assign loc_alert_regwen_0_we = addr_hit[258] & reg_we & !reg_error;
+  assign alert_cause_63_we = addr_hit[264] & reg_we & !reg_error;
+
+  assign alert_cause_63_wd = reg_wdata[0];
+  assign alert_cause_64_we = addr_hit[265] & reg_we & !reg_error;
+
+  assign alert_cause_64_wd = reg_wdata[0];
+  assign loc_alert_regwen_0_we = addr_hit[266] & reg_we & !reg_error;
 
   assign loc_alert_regwen_0_wd = reg_wdata[0];
-  assign loc_alert_regwen_1_we = addr_hit[259] & reg_we & !reg_error;
+  assign loc_alert_regwen_1_we = addr_hit[267] & reg_we & !reg_error;
 
   assign loc_alert_regwen_1_wd = reg_wdata[0];
-  assign loc_alert_regwen_2_we = addr_hit[260] & reg_we & !reg_error;
+  assign loc_alert_regwen_2_we = addr_hit[268] & reg_we & !reg_error;
 
   assign loc_alert_regwen_2_wd = reg_wdata[0];
-  assign loc_alert_regwen_3_we = addr_hit[261] & reg_we & !reg_error;
+  assign loc_alert_regwen_3_we = addr_hit[269] & reg_we & !reg_error;
 
   assign loc_alert_regwen_3_wd = reg_wdata[0];
-  assign loc_alert_regwen_4_we = addr_hit[262] & reg_we & !reg_error;
+  assign loc_alert_regwen_4_we = addr_hit[270] & reg_we & !reg_error;
 
   assign loc_alert_regwen_4_wd = reg_wdata[0];
-  assign loc_alert_regwen_5_we = addr_hit[263] & reg_we & !reg_error;
+  assign loc_alert_regwen_5_we = addr_hit[271] & reg_we & !reg_error;
 
   assign loc_alert_regwen_5_wd = reg_wdata[0];
-  assign loc_alert_regwen_6_we = addr_hit[264] & reg_we & !reg_error;
+  assign loc_alert_regwen_6_we = addr_hit[272] & reg_we & !reg_error;
 
   assign loc_alert_regwen_6_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_0_re = addr_hit[265] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_0_we = addr_hit[265] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_0_re = addr_hit[273] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_0_we = addr_hit[273] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_0_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_1_re = addr_hit[266] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_1_we = addr_hit[266] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_1_re = addr_hit[274] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_1_we = addr_hit[274] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_1_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_2_re = addr_hit[267] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_2_we = addr_hit[267] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_2_re = addr_hit[275] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_2_we = addr_hit[275] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_2_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_3_re = addr_hit[268] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_3_we = addr_hit[268] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_3_re = addr_hit[276] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_3_we = addr_hit[276] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_3_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_4_re = addr_hit[269] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_4_we = addr_hit[269] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_4_re = addr_hit[277] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_4_we = addr_hit[277] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_4_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_5_re = addr_hit[270] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_5_we = addr_hit[270] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_5_re = addr_hit[278] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_5_we = addr_hit[278] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_5_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_6_re = addr_hit[271] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_6_we = addr_hit[271] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_6_re = addr_hit[279] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_6_we = addr_hit[279] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_6_wd = reg_wdata[0];
-  assign loc_alert_class_shadowed_0_re = addr_hit[272] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_0_we = addr_hit[272] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_0_re = addr_hit[280] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_0_we = addr_hit[280] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_1_re = addr_hit[273] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_1_we = addr_hit[273] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_1_re = addr_hit[281] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_1_we = addr_hit[281] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_2_re = addr_hit[274] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_2_we = addr_hit[274] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_2_re = addr_hit[282] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_2_we = addr_hit[282] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_3_re = addr_hit[275] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_3_we = addr_hit[275] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_3_re = addr_hit[283] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_3_we = addr_hit[283] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_4_re = addr_hit[276] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_4_we = addr_hit[276] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_4_re = addr_hit[284] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_4_we = addr_hit[284] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_5_re = addr_hit[277] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_5_we = addr_hit[277] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_5_re = addr_hit[285] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_5_we = addr_hit[285] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_6_re = addr_hit[278] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_6_we = addr_hit[278] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_6_re = addr_hit[286] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_6_we = addr_hit[286] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0];
-  assign loc_alert_cause_0_we = addr_hit[279] & reg_we & !reg_error;
+  assign loc_alert_cause_0_we = addr_hit[287] & reg_we & !reg_error;
 
   assign loc_alert_cause_0_wd = reg_wdata[0];
-  assign loc_alert_cause_1_we = addr_hit[280] & reg_we & !reg_error;
+  assign loc_alert_cause_1_we = addr_hit[288] & reg_we & !reg_error;
 
   assign loc_alert_cause_1_wd = reg_wdata[0];
-  assign loc_alert_cause_2_we = addr_hit[281] & reg_we & !reg_error;
+  assign loc_alert_cause_2_we = addr_hit[289] & reg_we & !reg_error;
 
   assign loc_alert_cause_2_wd = reg_wdata[0];
-  assign loc_alert_cause_3_we = addr_hit[282] & reg_we & !reg_error;
+  assign loc_alert_cause_3_we = addr_hit[290] & reg_we & !reg_error;
 
   assign loc_alert_cause_3_wd = reg_wdata[0];
-  assign loc_alert_cause_4_we = addr_hit[283] & reg_we & !reg_error;
+  assign loc_alert_cause_4_we = addr_hit[291] & reg_we & !reg_error;
 
   assign loc_alert_cause_4_wd = reg_wdata[0];
-  assign loc_alert_cause_5_we = addr_hit[284] & reg_we & !reg_error;
+  assign loc_alert_cause_5_we = addr_hit[292] & reg_we & !reg_error;
 
   assign loc_alert_cause_5_wd = reg_wdata[0];
-  assign loc_alert_cause_6_we = addr_hit[285] & reg_we & !reg_error;
+  assign loc_alert_cause_6_we = addr_hit[293] & reg_we & !reg_error;
 
   assign loc_alert_cause_6_wd = reg_wdata[0];
-  assign classa_regwen_we = addr_hit[286] & reg_we & !reg_error;
+  assign classa_regwen_we = addr_hit[294] & reg_we & !reg_error;
 
   assign classa_regwen_wd = reg_wdata[0];
-  assign classa_ctrl_shadowed_re = addr_hit[287] & reg_re & !reg_error;
-  assign classa_ctrl_shadowed_we = addr_hit[287] & reg_we & !reg_error;
+  assign classa_ctrl_shadowed_re = addr_hit[295] & reg_re & !reg_error;
+  assign classa_ctrl_shadowed_we = addr_hit[295] & reg_we & !reg_error;
 
   assign classa_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -16615,49 +16967,49 @@
   assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classa_clr_regwen_we = addr_hit[288] & reg_we & !reg_error;
+  assign classa_clr_regwen_we = addr_hit[296] & reg_we & !reg_error;
 
   assign classa_clr_regwen_wd = reg_wdata[0];
-  assign classa_clr_shadowed_re = addr_hit[289] & reg_re & !reg_error;
-  assign classa_clr_shadowed_we = addr_hit[289] & reg_we & !reg_error;
+  assign classa_clr_shadowed_re = addr_hit[297] & reg_re & !reg_error;
+  assign classa_clr_shadowed_we = addr_hit[297] & reg_we & !reg_error;
 
   assign classa_clr_shadowed_wd = reg_wdata[0];
-  assign classa_accum_cnt_re = addr_hit[290] & reg_re & !reg_error;
-  assign classa_accum_thresh_shadowed_re = addr_hit[291] & reg_re & !reg_error;
-  assign classa_accum_thresh_shadowed_we = addr_hit[291] & reg_we & !reg_error;
+  assign classa_accum_cnt_re = addr_hit[298] & reg_re & !reg_error;
+  assign classa_accum_thresh_shadowed_re = addr_hit[299] & reg_re & !reg_error;
+  assign classa_accum_thresh_shadowed_we = addr_hit[299] & reg_we & !reg_error;
 
   assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classa_timeout_cyc_shadowed_re = addr_hit[292] & reg_re & !reg_error;
-  assign classa_timeout_cyc_shadowed_we = addr_hit[292] & reg_we & !reg_error;
+  assign classa_timeout_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error;
+  assign classa_timeout_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error;
 
   assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_crashdump_trigger_shadowed_re = addr_hit[293] & reg_re & !reg_error;
-  assign classa_crashdump_trigger_shadowed_we = addr_hit[293] & reg_we & !reg_error;
+  assign classa_crashdump_trigger_shadowed_re = addr_hit[301] & reg_re & !reg_error;
+  assign classa_crashdump_trigger_shadowed_we = addr_hit[301] & reg_we & !reg_error;
 
   assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classa_phase0_cyc_shadowed_re = addr_hit[294] & reg_re & !reg_error;
-  assign classa_phase0_cyc_shadowed_we = addr_hit[294] & reg_we & !reg_error;
+  assign classa_phase0_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error;
+  assign classa_phase0_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error;
 
   assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_phase1_cyc_shadowed_re = addr_hit[295] & reg_re & !reg_error;
-  assign classa_phase1_cyc_shadowed_we = addr_hit[295] & reg_we & !reg_error;
+  assign classa_phase1_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error;
+  assign classa_phase1_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error;
 
   assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_phase2_cyc_shadowed_re = addr_hit[296] & reg_re & !reg_error;
-  assign classa_phase2_cyc_shadowed_we = addr_hit[296] & reg_we & !reg_error;
+  assign classa_phase2_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error;
+  assign classa_phase2_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error;
 
   assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_phase3_cyc_shadowed_re = addr_hit[297] & reg_re & !reg_error;
-  assign classa_phase3_cyc_shadowed_we = addr_hit[297] & reg_we & !reg_error;
+  assign classa_phase3_cyc_shadowed_re = addr_hit[305] & reg_re & !reg_error;
+  assign classa_phase3_cyc_shadowed_we = addr_hit[305] & reg_we & !reg_error;
 
   assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_esc_cnt_re = addr_hit[298] & reg_re & !reg_error;
-  assign classa_state_re = addr_hit[299] & reg_re & !reg_error;
-  assign classb_regwen_we = addr_hit[300] & reg_we & !reg_error;
+  assign classa_esc_cnt_re = addr_hit[306] & reg_re & !reg_error;
+  assign classa_state_re = addr_hit[307] & reg_re & !reg_error;
+  assign classb_regwen_we = addr_hit[308] & reg_we & !reg_error;
 
   assign classb_regwen_wd = reg_wdata[0];
-  assign classb_ctrl_shadowed_re = addr_hit[301] & reg_re & !reg_error;
-  assign classb_ctrl_shadowed_we = addr_hit[301] & reg_we & !reg_error;
+  assign classb_ctrl_shadowed_re = addr_hit[309] & reg_re & !reg_error;
+  assign classb_ctrl_shadowed_we = addr_hit[309] & reg_we & !reg_error;
 
   assign classb_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -16678,49 +17030,49 @@
   assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classb_clr_regwen_we = addr_hit[302] & reg_we & !reg_error;
+  assign classb_clr_regwen_we = addr_hit[310] & reg_we & !reg_error;
 
   assign classb_clr_regwen_wd = reg_wdata[0];
-  assign classb_clr_shadowed_re = addr_hit[303] & reg_re & !reg_error;
-  assign classb_clr_shadowed_we = addr_hit[303] & reg_we & !reg_error;
+  assign classb_clr_shadowed_re = addr_hit[311] & reg_re & !reg_error;
+  assign classb_clr_shadowed_we = addr_hit[311] & reg_we & !reg_error;
 
   assign classb_clr_shadowed_wd = reg_wdata[0];
-  assign classb_accum_cnt_re = addr_hit[304] & reg_re & !reg_error;
-  assign classb_accum_thresh_shadowed_re = addr_hit[305] & reg_re & !reg_error;
-  assign classb_accum_thresh_shadowed_we = addr_hit[305] & reg_we & !reg_error;
+  assign classb_accum_cnt_re = addr_hit[312] & reg_re & !reg_error;
+  assign classb_accum_thresh_shadowed_re = addr_hit[313] & reg_re & !reg_error;
+  assign classb_accum_thresh_shadowed_we = addr_hit[313] & reg_we & !reg_error;
 
   assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classb_timeout_cyc_shadowed_re = addr_hit[306] & reg_re & !reg_error;
-  assign classb_timeout_cyc_shadowed_we = addr_hit[306] & reg_we & !reg_error;
+  assign classb_timeout_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error;
+  assign classb_timeout_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error;
 
   assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_crashdump_trigger_shadowed_re = addr_hit[307] & reg_re & !reg_error;
-  assign classb_crashdump_trigger_shadowed_we = addr_hit[307] & reg_we & !reg_error;
+  assign classb_crashdump_trigger_shadowed_re = addr_hit[315] & reg_re & !reg_error;
+  assign classb_crashdump_trigger_shadowed_we = addr_hit[315] & reg_we & !reg_error;
 
   assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classb_phase0_cyc_shadowed_re = addr_hit[308] & reg_re & !reg_error;
-  assign classb_phase0_cyc_shadowed_we = addr_hit[308] & reg_we & !reg_error;
+  assign classb_phase0_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error;
+  assign classb_phase0_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error;
 
   assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_phase1_cyc_shadowed_re = addr_hit[309] & reg_re & !reg_error;
-  assign classb_phase1_cyc_shadowed_we = addr_hit[309] & reg_we & !reg_error;
+  assign classb_phase1_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error;
+  assign classb_phase1_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error;
 
   assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_phase2_cyc_shadowed_re = addr_hit[310] & reg_re & !reg_error;
-  assign classb_phase2_cyc_shadowed_we = addr_hit[310] & reg_we & !reg_error;
+  assign classb_phase2_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error;
+  assign classb_phase2_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error;
 
   assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_phase3_cyc_shadowed_re = addr_hit[311] & reg_re & !reg_error;
-  assign classb_phase3_cyc_shadowed_we = addr_hit[311] & reg_we & !reg_error;
+  assign classb_phase3_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error;
+  assign classb_phase3_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error;
 
   assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_esc_cnt_re = addr_hit[312] & reg_re & !reg_error;
-  assign classb_state_re = addr_hit[313] & reg_re & !reg_error;
-  assign classc_regwen_we = addr_hit[314] & reg_we & !reg_error;
+  assign classb_esc_cnt_re = addr_hit[320] & reg_re & !reg_error;
+  assign classb_state_re = addr_hit[321] & reg_re & !reg_error;
+  assign classc_regwen_we = addr_hit[322] & reg_we & !reg_error;
 
   assign classc_regwen_wd = reg_wdata[0];
-  assign classc_ctrl_shadowed_re = addr_hit[315] & reg_re & !reg_error;
-  assign classc_ctrl_shadowed_we = addr_hit[315] & reg_we & !reg_error;
+  assign classc_ctrl_shadowed_re = addr_hit[323] & reg_re & !reg_error;
+  assign classc_ctrl_shadowed_we = addr_hit[323] & reg_we & !reg_error;
 
   assign classc_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -16741,49 +17093,49 @@
   assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classc_clr_regwen_we = addr_hit[316] & reg_we & !reg_error;
+  assign classc_clr_regwen_we = addr_hit[324] & reg_we & !reg_error;
 
   assign classc_clr_regwen_wd = reg_wdata[0];
-  assign classc_clr_shadowed_re = addr_hit[317] & reg_re & !reg_error;
-  assign classc_clr_shadowed_we = addr_hit[317] & reg_we & !reg_error;
+  assign classc_clr_shadowed_re = addr_hit[325] & reg_re & !reg_error;
+  assign classc_clr_shadowed_we = addr_hit[325] & reg_we & !reg_error;
 
   assign classc_clr_shadowed_wd = reg_wdata[0];
-  assign classc_accum_cnt_re = addr_hit[318] & reg_re & !reg_error;
-  assign classc_accum_thresh_shadowed_re = addr_hit[319] & reg_re & !reg_error;
-  assign classc_accum_thresh_shadowed_we = addr_hit[319] & reg_we & !reg_error;
+  assign classc_accum_cnt_re = addr_hit[326] & reg_re & !reg_error;
+  assign classc_accum_thresh_shadowed_re = addr_hit[327] & reg_re & !reg_error;
+  assign classc_accum_thresh_shadowed_we = addr_hit[327] & reg_we & !reg_error;
 
   assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classc_timeout_cyc_shadowed_re = addr_hit[320] & reg_re & !reg_error;
-  assign classc_timeout_cyc_shadowed_we = addr_hit[320] & reg_we & !reg_error;
+  assign classc_timeout_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error;
+  assign classc_timeout_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error;
 
   assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_crashdump_trigger_shadowed_re = addr_hit[321] & reg_re & !reg_error;
-  assign classc_crashdump_trigger_shadowed_we = addr_hit[321] & reg_we & !reg_error;
+  assign classc_crashdump_trigger_shadowed_re = addr_hit[329] & reg_re & !reg_error;
+  assign classc_crashdump_trigger_shadowed_we = addr_hit[329] & reg_we & !reg_error;
 
   assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classc_phase0_cyc_shadowed_re = addr_hit[322] & reg_re & !reg_error;
-  assign classc_phase0_cyc_shadowed_we = addr_hit[322] & reg_we & !reg_error;
+  assign classc_phase0_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error;
+  assign classc_phase0_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error;
 
   assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_phase1_cyc_shadowed_re = addr_hit[323] & reg_re & !reg_error;
-  assign classc_phase1_cyc_shadowed_we = addr_hit[323] & reg_we & !reg_error;
+  assign classc_phase1_cyc_shadowed_re = addr_hit[331] & reg_re & !reg_error;
+  assign classc_phase1_cyc_shadowed_we = addr_hit[331] & reg_we & !reg_error;
 
   assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_phase2_cyc_shadowed_re = addr_hit[324] & reg_re & !reg_error;
-  assign classc_phase2_cyc_shadowed_we = addr_hit[324] & reg_we & !reg_error;
+  assign classc_phase2_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error;
+  assign classc_phase2_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error;
 
   assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_phase3_cyc_shadowed_re = addr_hit[325] & reg_re & !reg_error;
-  assign classc_phase3_cyc_shadowed_we = addr_hit[325] & reg_we & !reg_error;
+  assign classc_phase3_cyc_shadowed_re = addr_hit[333] & reg_re & !reg_error;
+  assign classc_phase3_cyc_shadowed_we = addr_hit[333] & reg_we & !reg_error;
 
   assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_esc_cnt_re = addr_hit[326] & reg_re & !reg_error;
-  assign classc_state_re = addr_hit[327] & reg_re & !reg_error;
-  assign classd_regwen_we = addr_hit[328] & reg_we & !reg_error;
+  assign classc_esc_cnt_re = addr_hit[334] & reg_re & !reg_error;
+  assign classc_state_re = addr_hit[335] & reg_re & !reg_error;
+  assign classd_regwen_we = addr_hit[336] & reg_we & !reg_error;
 
   assign classd_regwen_wd = reg_wdata[0];
-  assign classd_ctrl_shadowed_re = addr_hit[329] & reg_re & !reg_error;
-  assign classd_ctrl_shadowed_we = addr_hit[329] & reg_we & !reg_error;
+  assign classd_ctrl_shadowed_re = addr_hit[337] & reg_re & !reg_error;
+  assign classd_ctrl_shadowed_we = addr_hit[337] & reg_we & !reg_error;
 
   assign classd_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -16804,44 +17156,44 @@
   assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classd_clr_regwen_we = addr_hit[330] & reg_we & !reg_error;
+  assign classd_clr_regwen_we = addr_hit[338] & reg_we & !reg_error;
 
   assign classd_clr_regwen_wd = reg_wdata[0];
-  assign classd_clr_shadowed_re = addr_hit[331] & reg_re & !reg_error;
-  assign classd_clr_shadowed_we = addr_hit[331] & reg_we & !reg_error;
+  assign classd_clr_shadowed_re = addr_hit[339] & reg_re & !reg_error;
+  assign classd_clr_shadowed_we = addr_hit[339] & reg_we & !reg_error;
 
   assign classd_clr_shadowed_wd = reg_wdata[0];
-  assign classd_accum_cnt_re = addr_hit[332] & reg_re & !reg_error;
-  assign classd_accum_thresh_shadowed_re = addr_hit[333] & reg_re & !reg_error;
-  assign classd_accum_thresh_shadowed_we = addr_hit[333] & reg_we & !reg_error;
+  assign classd_accum_cnt_re = addr_hit[340] & reg_re & !reg_error;
+  assign classd_accum_thresh_shadowed_re = addr_hit[341] & reg_re & !reg_error;
+  assign classd_accum_thresh_shadowed_we = addr_hit[341] & reg_we & !reg_error;
 
   assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classd_timeout_cyc_shadowed_re = addr_hit[334] & reg_re & !reg_error;
-  assign classd_timeout_cyc_shadowed_we = addr_hit[334] & reg_we & !reg_error;
+  assign classd_timeout_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error;
+  assign classd_timeout_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error;
 
   assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_crashdump_trigger_shadowed_re = addr_hit[335] & reg_re & !reg_error;
-  assign classd_crashdump_trigger_shadowed_we = addr_hit[335] & reg_we & !reg_error;
+  assign classd_crashdump_trigger_shadowed_re = addr_hit[343] & reg_re & !reg_error;
+  assign classd_crashdump_trigger_shadowed_we = addr_hit[343] & reg_we & !reg_error;
 
   assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classd_phase0_cyc_shadowed_re = addr_hit[336] & reg_re & !reg_error;
-  assign classd_phase0_cyc_shadowed_we = addr_hit[336] & reg_we & !reg_error;
+  assign classd_phase0_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error;
+  assign classd_phase0_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error;
 
   assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_phase1_cyc_shadowed_re = addr_hit[337] & reg_re & !reg_error;
-  assign classd_phase1_cyc_shadowed_we = addr_hit[337] & reg_we & !reg_error;
+  assign classd_phase1_cyc_shadowed_re = addr_hit[345] & reg_re & !reg_error;
+  assign classd_phase1_cyc_shadowed_we = addr_hit[345] & reg_we & !reg_error;
 
   assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_phase2_cyc_shadowed_re = addr_hit[338] & reg_re & !reg_error;
-  assign classd_phase2_cyc_shadowed_we = addr_hit[338] & reg_we & !reg_error;
+  assign classd_phase2_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error;
+  assign classd_phase2_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error;
 
   assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_phase3_cyc_shadowed_re = addr_hit[339] & reg_re & !reg_error;
-  assign classd_phase3_cyc_shadowed_we = addr_hit[339] & reg_we & !reg_error;
+  assign classd_phase3_cyc_shadowed_re = addr_hit[347] & reg_re & !reg_error;
+  assign classd_phase3_cyc_shadowed_we = addr_hit[347] & reg_we & !reg_error;
 
   assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_esc_cnt_re = addr_hit[340] & reg_re & !reg_error;
-  assign classd_state_re = addr_hit[341] & reg_re & !reg_error;
+  assign classd_esc_cnt_re = addr_hit[348] & reg_re & !reg_error;
+  assign classd_state_re = addr_hit[349] & reg_re & !reg_error;
 
   // Assign write-enables to checker logic vector.
   always_comb begin
@@ -16915,279 +17267,287 @@
     reg_we_check[66] = alert_regwen_60_we;
     reg_we_check[67] = alert_regwen_61_we;
     reg_we_check[68] = alert_regwen_62_we;
-    reg_we_check[69] = alert_en_shadowed_0_gated_we;
-    reg_we_check[70] = alert_en_shadowed_1_gated_we;
-    reg_we_check[71] = alert_en_shadowed_2_gated_we;
-    reg_we_check[72] = alert_en_shadowed_3_gated_we;
-    reg_we_check[73] = alert_en_shadowed_4_gated_we;
-    reg_we_check[74] = alert_en_shadowed_5_gated_we;
-    reg_we_check[75] = alert_en_shadowed_6_gated_we;
-    reg_we_check[76] = alert_en_shadowed_7_gated_we;
-    reg_we_check[77] = alert_en_shadowed_8_gated_we;
-    reg_we_check[78] = alert_en_shadowed_9_gated_we;
-    reg_we_check[79] = alert_en_shadowed_10_gated_we;
-    reg_we_check[80] = alert_en_shadowed_11_gated_we;
-    reg_we_check[81] = alert_en_shadowed_12_gated_we;
-    reg_we_check[82] = alert_en_shadowed_13_gated_we;
-    reg_we_check[83] = alert_en_shadowed_14_gated_we;
-    reg_we_check[84] = alert_en_shadowed_15_gated_we;
-    reg_we_check[85] = alert_en_shadowed_16_gated_we;
-    reg_we_check[86] = alert_en_shadowed_17_gated_we;
-    reg_we_check[87] = alert_en_shadowed_18_gated_we;
-    reg_we_check[88] = alert_en_shadowed_19_gated_we;
-    reg_we_check[89] = alert_en_shadowed_20_gated_we;
-    reg_we_check[90] = alert_en_shadowed_21_gated_we;
-    reg_we_check[91] = alert_en_shadowed_22_gated_we;
-    reg_we_check[92] = alert_en_shadowed_23_gated_we;
-    reg_we_check[93] = alert_en_shadowed_24_gated_we;
-    reg_we_check[94] = alert_en_shadowed_25_gated_we;
-    reg_we_check[95] = alert_en_shadowed_26_gated_we;
-    reg_we_check[96] = alert_en_shadowed_27_gated_we;
-    reg_we_check[97] = alert_en_shadowed_28_gated_we;
-    reg_we_check[98] = alert_en_shadowed_29_gated_we;
-    reg_we_check[99] = alert_en_shadowed_30_gated_we;
-    reg_we_check[100] = alert_en_shadowed_31_gated_we;
-    reg_we_check[101] = alert_en_shadowed_32_gated_we;
-    reg_we_check[102] = alert_en_shadowed_33_gated_we;
-    reg_we_check[103] = alert_en_shadowed_34_gated_we;
-    reg_we_check[104] = alert_en_shadowed_35_gated_we;
-    reg_we_check[105] = alert_en_shadowed_36_gated_we;
-    reg_we_check[106] = alert_en_shadowed_37_gated_we;
-    reg_we_check[107] = alert_en_shadowed_38_gated_we;
-    reg_we_check[108] = alert_en_shadowed_39_gated_we;
-    reg_we_check[109] = alert_en_shadowed_40_gated_we;
-    reg_we_check[110] = alert_en_shadowed_41_gated_we;
-    reg_we_check[111] = alert_en_shadowed_42_gated_we;
-    reg_we_check[112] = alert_en_shadowed_43_gated_we;
-    reg_we_check[113] = alert_en_shadowed_44_gated_we;
-    reg_we_check[114] = alert_en_shadowed_45_gated_we;
-    reg_we_check[115] = alert_en_shadowed_46_gated_we;
-    reg_we_check[116] = alert_en_shadowed_47_gated_we;
-    reg_we_check[117] = alert_en_shadowed_48_gated_we;
-    reg_we_check[118] = alert_en_shadowed_49_gated_we;
-    reg_we_check[119] = alert_en_shadowed_50_gated_we;
-    reg_we_check[120] = alert_en_shadowed_51_gated_we;
-    reg_we_check[121] = alert_en_shadowed_52_gated_we;
-    reg_we_check[122] = alert_en_shadowed_53_gated_we;
-    reg_we_check[123] = alert_en_shadowed_54_gated_we;
-    reg_we_check[124] = alert_en_shadowed_55_gated_we;
-    reg_we_check[125] = alert_en_shadowed_56_gated_we;
-    reg_we_check[126] = alert_en_shadowed_57_gated_we;
-    reg_we_check[127] = alert_en_shadowed_58_gated_we;
-    reg_we_check[128] = alert_en_shadowed_59_gated_we;
-    reg_we_check[129] = alert_en_shadowed_60_gated_we;
-    reg_we_check[130] = alert_en_shadowed_61_gated_we;
-    reg_we_check[131] = alert_en_shadowed_62_gated_we;
-    reg_we_check[132] = alert_class_shadowed_0_gated_we;
-    reg_we_check[133] = alert_class_shadowed_1_gated_we;
-    reg_we_check[134] = alert_class_shadowed_2_gated_we;
-    reg_we_check[135] = alert_class_shadowed_3_gated_we;
-    reg_we_check[136] = alert_class_shadowed_4_gated_we;
-    reg_we_check[137] = alert_class_shadowed_5_gated_we;
-    reg_we_check[138] = alert_class_shadowed_6_gated_we;
-    reg_we_check[139] = alert_class_shadowed_7_gated_we;
-    reg_we_check[140] = alert_class_shadowed_8_gated_we;
-    reg_we_check[141] = alert_class_shadowed_9_gated_we;
-    reg_we_check[142] = alert_class_shadowed_10_gated_we;
-    reg_we_check[143] = alert_class_shadowed_11_gated_we;
-    reg_we_check[144] = alert_class_shadowed_12_gated_we;
-    reg_we_check[145] = alert_class_shadowed_13_gated_we;
-    reg_we_check[146] = alert_class_shadowed_14_gated_we;
-    reg_we_check[147] = alert_class_shadowed_15_gated_we;
-    reg_we_check[148] = alert_class_shadowed_16_gated_we;
-    reg_we_check[149] = alert_class_shadowed_17_gated_we;
-    reg_we_check[150] = alert_class_shadowed_18_gated_we;
-    reg_we_check[151] = alert_class_shadowed_19_gated_we;
-    reg_we_check[152] = alert_class_shadowed_20_gated_we;
-    reg_we_check[153] = alert_class_shadowed_21_gated_we;
-    reg_we_check[154] = alert_class_shadowed_22_gated_we;
-    reg_we_check[155] = alert_class_shadowed_23_gated_we;
-    reg_we_check[156] = alert_class_shadowed_24_gated_we;
-    reg_we_check[157] = alert_class_shadowed_25_gated_we;
-    reg_we_check[158] = alert_class_shadowed_26_gated_we;
-    reg_we_check[159] = alert_class_shadowed_27_gated_we;
-    reg_we_check[160] = alert_class_shadowed_28_gated_we;
-    reg_we_check[161] = alert_class_shadowed_29_gated_we;
-    reg_we_check[162] = alert_class_shadowed_30_gated_we;
-    reg_we_check[163] = alert_class_shadowed_31_gated_we;
-    reg_we_check[164] = alert_class_shadowed_32_gated_we;
-    reg_we_check[165] = alert_class_shadowed_33_gated_we;
-    reg_we_check[166] = alert_class_shadowed_34_gated_we;
-    reg_we_check[167] = alert_class_shadowed_35_gated_we;
-    reg_we_check[168] = alert_class_shadowed_36_gated_we;
-    reg_we_check[169] = alert_class_shadowed_37_gated_we;
-    reg_we_check[170] = alert_class_shadowed_38_gated_we;
-    reg_we_check[171] = alert_class_shadowed_39_gated_we;
-    reg_we_check[172] = alert_class_shadowed_40_gated_we;
-    reg_we_check[173] = alert_class_shadowed_41_gated_we;
-    reg_we_check[174] = alert_class_shadowed_42_gated_we;
-    reg_we_check[175] = alert_class_shadowed_43_gated_we;
-    reg_we_check[176] = alert_class_shadowed_44_gated_we;
-    reg_we_check[177] = alert_class_shadowed_45_gated_we;
-    reg_we_check[178] = alert_class_shadowed_46_gated_we;
-    reg_we_check[179] = alert_class_shadowed_47_gated_we;
-    reg_we_check[180] = alert_class_shadowed_48_gated_we;
-    reg_we_check[181] = alert_class_shadowed_49_gated_we;
-    reg_we_check[182] = alert_class_shadowed_50_gated_we;
-    reg_we_check[183] = alert_class_shadowed_51_gated_we;
-    reg_we_check[184] = alert_class_shadowed_52_gated_we;
-    reg_we_check[185] = alert_class_shadowed_53_gated_we;
-    reg_we_check[186] = alert_class_shadowed_54_gated_we;
-    reg_we_check[187] = alert_class_shadowed_55_gated_we;
-    reg_we_check[188] = alert_class_shadowed_56_gated_we;
-    reg_we_check[189] = alert_class_shadowed_57_gated_we;
-    reg_we_check[190] = alert_class_shadowed_58_gated_we;
-    reg_we_check[191] = alert_class_shadowed_59_gated_we;
-    reg_we_check[192] = alert_class_shadowed_60_gated_we;
-    reg_we_check[193] = alert_class_shadowed_61_gated_we;
-    reg_we_check[194] = alert_class_shadowed_62_gated_we;
-    reg_we_check[195] = alert_cause_0_we;
-    reg_we_check[196] = alert_cause_1_we;
-    reg_we_check[197] = alert_cause_2_we;
-    reg_we_check[198] = alert_cause_3_we;
-    reg_we_check[199] = alert_cause_4_we;
-    reg_we_check[200] = alert_cause_5_we;
-    reg_we_check[201] = alert_cause_6_we;
-    reg_we_check[202] = alert_cause_7_we;
-    reg_we_check[203] = alert_cause_8_we;
-    reg_we_check[204] = alert_cause_9_we;
-    reg_we_check[205] = alert_cause_10_we;
-    reg_we_check[206] = alert_cause_11_we;
-    reg_we_check[207] = alert_cause_12_we;
-    reg_we_check[208] = alert_cause_13_we;
-    reg_we_check[209] = alert_cause_14_we;
-    reg_we_check[210] = alert_cause_15_we;
-    reg_we_check[211] = alert_cause_16_we;
-    reg_we_check[212] = alert_cause_17_we;
-    reg_we_check[213] = alert_cause_18_we;
-    reg_we_check[214] = alert_cause_19_we;
-    reg_we_check[215] = alert_cause_20_we;
-    reg_we_check[216] = alert_cause_21_we;
-    reg_we_check[217] = alert_cause_22_we;
-    reg_we_check[218] = alert_cause_23_we;
-    reg_we_check[219] = alert_cause_24_we;
-    reg_we_check[220] = alert_cause_25_we;
-    reg_we_check[221] = alert_cause_26_we;
-    reg_we_check[222] = alert_cause_27_we;
-    reg_we_check[223] = alert_cause_28_we;
-    reg_we_check[224] = alert_cause_29_we;
-    reg_we_check[225] = alert_cause_30_we;
-    reg_we_check[226] = alert_cause_31_we;
-    reg_we_check[227] = alert_cause_32_we;
-    reg_we_check[228] = alert_cause_33_we;
-    reg_we_check[229] = alert_cause_34_we;
-    reg_we_check[230] = alert_cause_35_we;
-    reg_we_check[231] = alert_cause_36_we;
-    reg_we_check[232] = alert_cause_37_we;
-    reg_we_check[233] = alert_cause_38_we;
-    reg_we_check[234] = alert_cause_39_we;
-    reg_we_check[235] = alert_cause_40_we;
-    reg_we_check[236] = alert_cause_41_we;
-    reg_we_check[237] = alert_cause_42_we;
-    reg_we_check[238] = alert_cause_43_we;
-    reg_we_check[239] = alert_cause_44_we;
-    reg_we_check[240] = alert_cause_45_we;
-    reg_we_check[241] = alert_cause_46_we;
-    reg_we_check[242] = alert_cause_47_we;
-    reg_we_check[243] = alert_cause_48_we;
-    reg_we_check[244] = alert_cause_49_we;
-    reg_we_check[245] = alert_cause_50_we;
-    reg_we_check[246] = alert_cause_51_we;
-    reg_we_check[247] = alert_cause_52_we;
-    reg_we_check[248] = alert_cause_53_we;
-    reg_we_check[249] = alert_cause_54_we;
-    reg_we_check[250] = alert_cause_55_we;
-    reg_we_check[251] = alert_cause_56_we;
-    reg_we_check[252] = alert_cause_57_we;
-    reg_we_check[253] = alert_cause_58_we;
-    reg_we_check[254] = alert_cause_59_we;
-    reg_we_check[255] = alert_cause_60_we;
-    reg_we_check[256] = alert_cause_61_we;
-    reg_we_check[257] = alert_cause_62_we;
-    reg_we_check[258] = loc_alert_regwen_0_we;
-    reg_we_check[259] = loc_alert_regwen_1_we;
-    reg_we_check[260] = loc_alert_regwen_2_we;
-    reg_we_check[261] = loc_alert_regwen_3_we;
-    reg_we_check[262] = loc_alert_regwen_4_we;
-    reg_we_check[263] = loc_alert_regwen_5_we;
-    reg_we_check[264] = loc_alert_regwen_6_we;
-    reg_we_check[265] = loc_alert_en_shadowed_0_gated_we;
-    reg_we_check[266] = loc_alert_en_shadowed_1_gated_we;
-    reg_we_check[267] = loc_alert_en_shadowed_2_gated_we;
-    reg_we_check[268] = loc_alert_en_shadowed_3_gated_we;
-    reg_we_check[269] = loc_alert_en_shadowed_4_gated_we;
-    reg_we_check[270] = loc_alert_en_shadowed_5_gated_we;
-    reg_we_check[271] = loc_alert_en_shadowed_6_gated_we;
-    reg_we_check[272] = loc_alert_class_shadowed_0_gated_we;
-    reg_we_check[273] = loc_alert_class_shadowed_1_gated_we;
-    reg_we_check[274] = loc_alert_class_shadowed_2_gated_we;
-    reg_we_check[275] = loc_alert_class_shadowed_3_gated_we;
-    reg_we_check[276] = loc_alert_class_shadowed_4_gated_we;
-    reg_we_check[277] = loc_alert_class_shadowed_5_gated_we;
-    reg_we_check[278] = loc_alert_class_shadowed_6_gated_we;
-    reg_we_check[279] = loc_alert_cause_0_we;
-    reg_we_check[280] = loc_alert_cause_1_we;
-    reg_we_check[281] = loc_alert_cause_2_we;
-    reg_we_check[282] = loc_alert_cause_3_we;
-    reg_we_check[283] = loc_alert_cause_4_we;
-    reg_we_check[284] = loc_alert_cause_5_we;
-    reg_we_check[285] = loc_alert_cause_6_we;
-    reg_we_check[286] = classa_regwen_we;
-    reg_we_check[287] = classa_ctrl_shadowed_gated_we;
-    reg_we_check[288] = classa_clr_regwen_we;
-    reg_we_check[289] = classa_clr_shadowed_gated_we;
-    reg_we_check[290] = 1'b0;
-    reg_we_check[291] = classa_accum_thresh_shadowed_gated_we;
-    reg_we_check[292] = classa_timeout_cyc_shadowed_gated_we;
-    reg_we_check[293] = classa_crashdump_trigger_shadowed_gated_we;
-    reg_we_check[294] = classa_phase0_cyc_shadowed_gated_we;
-    reg_we_check[295] = classa_phase1_cyc_shadowed_gated_we;
-    reg_we_check[296] = classa_phase2_cyc_shadowed_gated_we;
-    reg_we_check[297] = classa_phase3_cyc_shadowed_gated_we;
+    reg_we_check[69] = alert_regwen_63_we;
+    reg_we_check[70] = alert_regwen_64_we;
+    reg_we_check[71] = alert_en_shadowed_0_gated_we;
+    reg_we_check[72] = alert_en_shadowed_1_gated_we;
+    reg_we_check[73] = alert_en_shadowed_2_gated_we;
+    reg_we_check[74] = alert_en_shadowed_3_gated_we;
+    reg_we_check[75] = alert_en_shadowed_4_gated_we;
+    reg_we_check[76] = alert_en_shadowed_5_gated_we;
+    reg_we_check[77] = alert_en_shadowed_6_gated_we;
+    reg_we_check[78] = alert_en_shadowed_7_gated_we;
+    reg_we_check[79] = alert_en_shadowed_8_gated_we;
+    reg_we_check[80] = alert_en_shadowed_9_gated_we;
+    reg_we_check[81] = alert_en_shadowed_10_gated_we;
+    reg_we_check[82] = alert_en_shadowed_11_gated_we;
+    reg_we_check[83] = alert_en_shadowed_12_gated_we;
+    reg_we_check[84] = alert_en_shadowed_13_gated_we;
+    reg_we_check[85] = alert_en_shadowed_14_gated_we;
+    reg_we_check[86] = alert_en_shadowed_15_gated_we;
+    reg_we_check[87] = alert_en_shadowed_16_gated_we;
+    reg_we_check[88] = alert_en_shadowed_17_gated_we;
+    reg_we_check[89] = alert_en_shadowed_18_gated_we;
+    reg_we_check[90] = alert_en_shadowed_19_gated_we;
+    reg_we_check[91] = alert_en_shadowed_20_gated_we;
+    reg_we_check[92] = alert_en_shadowed_21_gated_we;
+    reg_we_check[93] = alert_en_shadowed_22_gated_we;
+    reg_we_check[94] = alert_en_shadowed_23_gated_we;
+    reg_we_check[95] = alert_en_shadowed_24_gated_we;
+    reg_we_check[96] = alert_en_shadowed_25_gated_we;
+    reg_we_check[97] = alert_en_shadowed_26_gated_we;
+    reg_we_check[98] = alert_en_shadowed_27_gated_we;
+    reg_we_check[99] = alert_en_shadowed_28_gated_we;
+    reg_we_check[100] = alert_en_shadowed_29_gated_we;
+    reg_we_check[101] = alert_en_shadowed_30_gated_we;
+    reg_we_check[102] = alert_en_shadowed_31_gated_we;
+    reg_we_check[103] = alert_en_shadowed_32_gated_we;
+    reg_we_check[104] = alert_en_shadowed_33_gated_we;
+    reg_we_check[105] = alert_en_shadowed_34_gated_we;
+    reg_we_check[106] = alert_en_shadowed_35_gated_we;
+    reg_we_check[107] = alert_en_shadowed_36_gated_we;
+    reg_we_check[108] = alert_en_shadowed_37_gated_we;
+    reg_we_check[109] = alert_en_shadowed_38_gated_we;
+    reg_we_check[110] = alert_en_shadowed_39_gated_we;
+    reg_we_check[111] = alert_en_shadowed_40_gated_we;
+    reg_we_check[112] = alert_en_shadowed_41_gated_we;
+    reg_we_check[113] = alert_en_shadowed_42_gated_we;
+    reg_we_check[114] = alert_en_shadowed_43_gated_we;
+    reg_we_check[115] = alert_en_shadowed_44_gated_we;
+    reg_we_check[116] = alert_en_shadowed_45_gated_we;
+    reg_we_check[117] = alert_en_shadowed_46_gated_we;
+    reg_we_check[118] = alert_en_shadowed_47_gated_we;
+    reg_we_check[119] = alert_en_shadowed_48_gated_we;
+    reg_we_check[120] = alert_en_shadowed_49_gated_we;
+    reg_we_check[121] = alert_en_shadowed_50_gated_we;
+    reg_we_check[122] = alert_en_shadowed_51_gated_we;
+    reg_we_check[123] = alert_en_shadowed_52_gated_we;
+    reg_we_check[124] = alert_en_shadowed_53_gated_we;
+    reg_we_check[125] = alert_en_shadowed_54_gated_we;
+    reg_we_check[126] = alert_en_shadowed_55_gated_we;
+    reg_we_check[127] = alert_en_shadowed_56_gated_we;
+    reg_we_check[128] = alert_en_shadowed_57_gated_we;
+    reg_we_check[129] = alert_en_shadowed_58_gated_we;
+    reg_we_check[130] = alert_en_shadowed_59_gated_we;
+    reg_we_check[131] = alert_en_shadowed_60_gated_we;
+    reg_we_check[132] = alert_en_shadowed_61_gated_we;
+    reg_we_check[133] = alert_en_shadowed_62_gated_we;
+    reg_we_check[134] = alert_en_shadowed_63_gated_we;
+    reg_we_check[135] = alert_en_shadowed_64_gated_we;
+    reg_we_check[136] = alert_class_shadowed_0_gated_we;
+    reg_we_check[137] = alert_class_shadowed_1_gated_we;
+    reg_we_check[138] = alert_class_shadowed_2_gated_we;
+    reg_we_check[139] = alert_class_shadowed_3_gated_we;
+    reg_we_check[140] = alert_class_shadowed_4_gated_we;
+    reg_we_check[141] = alert_class_shadowed_5_gated_we;
+    reg_we_check[142] = alert_class_shadowed_6_gated_we;
+    reg_we_check[143] = alert_class_shadowed_7_gated_we;
+    reg_we_check[144] = alert_class_shadowed_8_gated_we;
+    reg_we_check[145] = alert_class_shadowed_9_gated_we;
+    reg_we_check[146] = alert_class_shadowed_10_gated_we;
+    reg_we_check[147] = alert_class_shadowed_11_gated_we;
+    reg_we_check[148] = alert_class_shadowed_12_gated_we;
+    reg_we_check[149] = alert_class_shadowed_13_gated_we;
+    reg_we_check[150] = alert_class_shadowed_14_gated_we;
+    reg_we_check[151] = alert_class_shadowed_15_gated_we;
+    reg_we_check[152] = alert_class_shadowed_16_gated_we;
+    reg_we_check[153] = alert_class_shadowed_17_gated_we;
+    reg_we_check[154] = alert_class_shadowed_18_gated_we;
+    reg_we_check[155] = alert_class_shadowed_19_gated_we;
+    reg_we_check[156] = alert_class_shadowed_20_gated_we;
+    reg_we_check[157] = alert_class_shadowed_21_gated_we;
+    reg_we_check[158] = alert_class_shadowed_22_gated_we;
+    reg_we_check[159] = alert_class_shadowed_23_gated_we;
+    reg_we_check[160] = alert_class_shadowed_24_gated_we;
+    reg_we_check[161] = alert_class_shadowed_25_gated_we;
+    reg_we_check[162] = alert_class_shadowed_26_gated_we;
+    reg_we_check[163] = alert_class_shadowed_27_gated_we;
+    reg_we_check[164] = alert_class_shadowed_28_gated_we;
+    reg_we_check[165] = alert_class_shadowed_29_gated_we;
+    reg_we_check[166] = alert_class_shadowed_30_gated_we;
+    reg_we_check[167] = alert_class_shadowed_31_gated_we;
+    reg_we_check[168] = alert_class_shadowed_32_gated_we;
+    reg_we_check[169] = alert_class_shadowed_33_gated_we;
+    reg_we_check[170] = alert_class_shadowed_34_gated_we;
+    reg_we_check[171] = alert_class_shadowed_35_gated_we;
+    reg_we_check[172] = alert_class_shadowed_36_gated_we;
+    reg_we_check[173] = alert_class_shadowed_37_gated_we;
+    reg_we_check[174] = alert_class_shadowed_38_gated_we;
+    reg_we_check[175] = alert_class_shadowed_39_gated_we;
+    reg_we_check[176] = alert_class_shadowed_40_gated_we;
+    reg_we_check[177] = alert_class_shadowed_41_gated_we;
+    reg_we_check[178] = alert_class_shadowed_42_gated_we;
+    reg_we_check[179] = alert_class_shadowed_43_gated_we;
+    reg_we_check[180] = alert_class_shadowed_44_gated_we;
+    reg_we_check[181] = alert_class_shadowed_45_gated_we;
+    reg_we_check[182] = alert_class_shadowed_46_gated_we;
+    reg_we_check[183] = alert_class_shadowed_47_gated_we;
+    reg_we_check[184] = alert_class_shadowed_48_gated_we;
+    reg_we_check[185] = alert_class_shadowed_49_gated_we;
+    reg_we_check[186] = alert_class_shadowed_50_gated_we;
+    reg_we_check[187] = alert_class_shadowed_51_gated_we;
+    reg_we_check[188] = alert_class_shadowed_52_gated_we;
+    reg_we_check[189] = alert_class_shadowed_53_gated_we;
+    reg_we_check[190] = alert_class_shadowed_54_gated_we;
+    reg_we_check[191] = alert_class_shadowed_55_gated_we;
+    reg_we_check[192] = alert_class_shadowed_56_gated_we;
+    reg_we_check[193] = alert_class_shadowed_57_gated_we;
+    reg_we_check[194] = alert_class_shadowed_58_gated_we;
+    reg_we_check[195] = alert_class_shadowed_59_gated_we;
+    reg_we_check[196] = alert_class_shadowed_60_gated_we;
+    reg_we_check[197] = alert_class_shadowed_61_gated_we;
+    reg_we_check[198] = alert_class_shadowed_62_gated_we;
+    reg_we_check[199] = alert_class_shadowed_63_gated_we;
+    reg_we_check[200] = alert_class_shadowed_64_gated_we;
+    reg_we_check[201] = alert_cause_0_we;
+    reg_we_check[202] = alert_cause_1_we;
+    reg_we_check[203] = alert_cause_2_we;
+    reg_we_check[204] = alert_cause_3_we;
+    reg_we_check[205] = alert_cause_4_we;
+    reg_we_check[206] = alert_cause_5_we;
+    reg_we_check[207] = alert_cause_6_we;
+    reg_we_check[208] = alert_cause_7_we;
+    reg_we_check[209] = alert_cause_8_we;
+    reg_we_check[210] = alert_cause_9_we;
+    reg_we_check[211] = alert_cause_10_we;
+    reg_we_check[212] = alert_cause_11_we;
+    reg_we_check[213] = alert_cause_12_we;
+    reg_we_check[214] = alert_cause_13_we;
+    reg_we_check[215] = alert_cause_14_we;
+    reg_we_check[216] = alert_cause_15_we;
+    reg_we_check[217] = alert_cause_16_we;
+    reg_we_check[218] = alert_cause_17_we;
+    reg_we_check[219] = alert_cause_18_we;
+    reg_we_check[220] = alert_cause_19_we;
+    reg_we_check[221] = alert_cause_20_we;
+    reg_we_check[222] = alert_cause_21_we;
+    reg_we_check[223] = alert_cause_22_we;
+    reg_we_check[224] = alert_cause_23_we;
+    reg_we_check[225] = alert_cause_24_we;
+    reg_we_check[226] = alert_cause_25_we;
+    reg_we_check[227] = alert_cause_26_we;
+    reg_we_check[228] = alert_cause_27_we;
+    reg_we_check[229] = alert_cause_28_we;
+    reg_we_check[230] = alert_cause_29_we;
+    reg_we_check[231] = alert_cause_30_we;
+    reg_we_check[232] = alert_cause_31_we;
+    reg_we_check[233] = alert_cause_32_we;
+    reg_we_check[234] = alert_cause_33_we;
+    reg_we_check[235] = alert_cause_34_we;
+    reg_we_check[236] = alert_cause_35_we;
+    reg_we_check[237] = alert_cause_36_we;
+    reg_we_check[238] = alert_cause_37_we;
+    reg_we_check[239] = alert_cause_38_we;
+    reg_we_check[240] = alert_cause_39_we;
+    reg_we_check[241] = alert_cause_40_we;
+    reg_we_check[242] = alert_cause_41_we;
+    reg_we_check[243] = alert_cause_42_we;
+    reg_we_check[244] = alert_cause_43_we;
+    reg_we_check[245] = alert_cause_44_we;
+    reg_we_check[246] = alert_cause_45_we;
+    reg_we_check[247] = alert_cause_46_we;
+    reg_we_check[248] = alert_cause_47_we;
+    reg_we_check[249] = alert_cause_48_we;
+    reg_we_check[250] = alert_cause_49_we;
+    reg_we_check[251] = alert_cause_50_we;
+    reg_we_check[252] = alert_cause_51_we;
+    reg_we_check[253] = alert_cause_52_we;
+    reg_we_check[254] = alert_cause_53_we;
+    reg_we_check[255] = alert_cause_54_we;
+    reg_we_check[256] = alert_cause_55_we;
+    reg_we_check[257] = alert_cause_56_we;
+    reg_we_check[258] = alert_cause_57_we;
+    reg_we_check[259] = alert_cause_58_we;
+    reg_we_check[260] = alert_cause_59_we;
+    reg_we_check[261] = alert_cause_60_we;
+    reg_we_check[262] = alert_cause_61_we;
+    reg_we_check[263] = alert_cause_62_we;
+    reg_we_check[264] = alert_cause_63_we;
+    reg_we_check[265] = alert_cause_64_we;
+    reg_we_check[266] = loc_alert_regwen_0_we;
+    reg_we_check[267] = loc_alert_regwen_1_we;
+    reg_we_check[268] = loc_alert_regwen_2_we;
+    reg_we_check[269] = loc_alert_regwen_3_we;
+    reg_we_check[270] = loc_alert_regwen_4_we;
+    reg_we_check[271] = loc_alert_regwen_5_we;
+    reg_we_check[272] = loc_alert_regwen_6_we;
+    reg_we_check[273] = loc_alert_en_shadowed_0_gated_we;
+    reg_we_check[274] = loc_alert_en_shadowed_1_gated_we;
+    reg_we_check[275] = loc_alert_en_shadowed_2_gated_we;
+    reg_we_check[276] = loc_alert_en_shadowed_3_gated_we;
+    reg_we_check[277] = loc_alert_en_shadowed_4_gated_we;
+    reg_we_check[278] = loc_alert_en_shadowed_5_gated_we;
+    reg_we_check[279] = loc_alert_en_shadowed_6_gated_we;
+    reg_we_check[280] = loc_alert_class_shadowed_0_gated_we;
+    reg_we_check[281] = loc_alert_class_shadowed_1_gated_we;
+    reg_we_check[282] = loc_alert_class_shadowed_2_gated_we;
+    reg_we_check[283] = loc_alert_class_shadowed_3_gated_we;
+    reg_we_check[284] = loc_alert_class_shadowed_4_gated_we;
+    reg_we_check[285] = loc_alert_class_shadowed_5_gated_we;
+    reg_we_check[286] = loc_alert_class_shadowed_6_gated_we;
+    reg_we_check[287] = loc_alert_cause_0_we;
+    reg_we_check[288] = loc_alert_cause_1_we;
+    reg_we_check[289] = loc_alert_cause_2_we;
+    reg_we_check[290] = loc_alert_cause_3_we;
+    reg_we_check[291] = loc_alert_cause_4_we;
+    reg_we_check[292] = loc_alert_cause_5_we;
+    reg_we_check[293] = loc_alert_cause_6_we;
+    reg_we_check[294] = classa_regwen_we;
+    reg_we_check[295] = classa_ctrl_shadowed_gated_we;
+    reg_we_check[296] = classa_clr_regwen_we;
+    reg_we_check[297] = classa_clr_shadowed_gated_we;
     reg_we_check[298] = 1'b0;
-    reg_we_check[299] = 1'b0;
-    reg_we_check[300] = classb_regwen_we;
-    reg_we_check[301] = classb_ctrl_shadowed_gated_we;
-    reg_we_check[302] = classb_clr_regwen_we;
-    reg_we_check[303] = classb_clr_shadowed_gated_we;
-    reg_we_check[304] = 1'b0;
-    reg_we_check[305] = classb_accum_thresh_shadowed_gated_we;
-    reg_we_check[306] = classb_timeout_cyc_shadowed_gated_we;
-    reg_we_check[307] = classb_crashdump_trigger_shadowed_gated_we;
-    reg_we_check[308] = classb_phase0_cyc_shadowed_gated_we;
-    reg_we_check[309] = classb_phase1_cyc_shadowed_gated_we;
-    reg_we_check[310] = classb_phase2_cyc_shadowed_gated_we;
-    reg_we_check[311] = classb_phase3_cyc_shadowed_gated_we;
+    reg_we_check[299] = classa_accum_thresh_shadowed_gated_we;
+    reg_we_check[300] = classa_timeout_cyc_shadowed_gated_we;
+    reg_we_check[301] = classa_crashdump_trigger_shadowed_gated_we;
+    reg_we_check[302] = classa_phase0_cyc_shadowed_gated_we;
+    reg_we_check[303] = classa_phase1_cyc_shadowed_gated_we;
+    reg_we_check[304] = classa_phase2_cyc_shadowed_gated_we;
+    reg_we_check[305] = classa_phase3_cyc_shadowed_gated_we;
+    reg_we_check[306] = 1'b0;
+    reg_we_check[307] = 1'b0;
+    reg_we_check[308] = classb_regwen_we;
+    reg_we_check[309] = classb_ctrl_shadowed_gated_we;
+    reg_we_check[310] = classb_clr_regwen_we;
+    reg_we_check[311] = classb_clr_shadowed_gated_we;
     reg_we_check[312] = 1'b0;
-    reg_we_check[313] = 1'b0;
-    reg_we_check[314] = classc_regwen_we;
-    reg_we_check[315] = classc_ctrl_shadowed_gated_we;
-    reg_we_check[316] = classc_clr_regwen_we;
-    reg_we_check[317] = classc_clr_shadowed_gated_we;
-    reg_we_check[318] = 1'b0;
-    reg_we_check[319] = classc_accum_thresh_shadowed_gated_we;
-    reg_we_check[320] = classc_timeout_cyc_shadowed_gated_we;
-    reg_we_check[321] = classc_crashdump_trigger_shadowed_gated_we;
-    reg_we_check[322] = classc_phase0_cyc_shadowed_gated_we;
-    reg_we_check[323] = classc_phase1_cyc_shadowed_gated_we;
-    reg_we_check[324] = classc_phase2_cyc_shadowed_gated_we;
-    reg_we_check[325] = classc_phase3_cyc_shadowed_gated_we;
+    reg_we_check[313] = classb_accum_thresh_shadowed_gated_we;
+    reg_we_check[314] = classb_timeout_cyc_shadowed_gated_we;
+    reg_we_check[315] = classb_crashdump_trigger_shadowed_gated_we;
+    reg_we_check[316] = classb_phase0_cyc_shadowed_gated_we;
+    reg_we_check[317] = classb_phase1_cyc_shadowed_gated_we;
+    reg_we_check[318] = classb_phase2_cyc_shadowed_gated_we;
+    reg_we_check[319] = classb_phase3_cyc_shadowed_gated_we;
+    reg_we_check[320] = 1'b0;
+    reg_we_check[321] = 1'b0;
+    reg_we_check[322] = classc_regwen_we;
+    reg_we_check[323] = classc_ctrl_shadowed_gated_we;
+    reg_we_check[324] = classc_clr_regwen_we;
+    reg_we_check[325] = classc_clr_shadowed_gated_we;
     reg_we_check[326] = 1'b0;
-    reg_we_check[327] = 1'b0;
-    reg_we_check[328] = classd_regwen_we;
-    reg_we_check[329] = classd_ctrl_shadowed_gated_we;
-    reg_we_check[330] = classd_clr_regwen_we;
-    reg_we_check[331] = classd_clr_shadowed_gated_we;
-    reg_we_check[332] = 1'b0;
-    reg_we_check[333] = classd_accum_thresh_shadowed_gated_we;
-    reg_we_check[334] = classd_timeout_cyc_shadowed_gated_we;
-    reg_we_check[335] = classd_crashdump_trigger_shadowed_gated_we;
-    reg_we_check[336] = classd_phase0_cyc_shadowed_gated_we;
-    reg_we_check[337] = classd_phase1_cyc_shadowed_gated_we;
-    reg_we_check[338] = classd_phase2_cyc_shadowed_gated_we;
-    reg_we_check[339] = classd_phase3_cyc_shadowed_gated_we;
+    reg_we_check[327] = classc_accum_thresh_shadowed_gated_we;
+    reg_we_check[328] = classc_timeout_cyc_shadowed_gated_we;
+    reg_we_check[329] = classc_crashdump_trigger_shadowed_gated_we;
+    reg_we_check[330] = classc_phase0_cyc_shadowed_gated_we;
+    reg_we_check[331] = classc_phase1_cyc_shadowed_gated_we;
+    reg_we_check[332] = classc_phase2_cyc_shadowed_gated_we;
+    reg_we_check[333] = classc_phase3_cyc_shadowed_gated_we;
+    reg_we_check[334] = 1'b0;
+    reg_we_check[335] = 1'b0;
+    reg_we_check[336] = classd_regwen_we;
+    reg_we_check[337] = classd_ctrl_shadowed_gated_we;
+    reg_we_check[338] = classd_clr_regwen_we;
+    reg_we_check[339] = classd_clr_shadowed_gated_we;
     reg_we_check[340] = 1'b0;
-    reg_we_check[341] = 1'b0;
+    reg_we_check[341] = classd_accum_thresh_shadowed_gated_we;
+    reg_we_check[342] = classd_timeout_cyc_shadowed_gated_we;
+    reg_we_check[343] = classd_crashdump_trigger_shadowed_gated_we;
+    reg_we_check[344] = classd_phase0_cyc_shadowed_gated_we;
+    reg_we_check[345] = classd_phase1_cyc_shadowed_gated_we;
+    reg_we_check[346] = classd_phase2_cyc_shadowed_gated_we;
+    reg_we_check[347] = classd_phase3_cyc_shadowed_gated_we;
+    reg_we_check[348] = 1'b0;
+    reg_we_check[349] = 1'b0;
   end
 
   // Read data return
@@ -17480,878 +17840,910 @@
       end
 
       addr_hit[69]: begin
-        reg_rdata_next[0] = alert_en_shadowed_0_qs;
+        reg_rdata_next[0] = alert_regwen_63_qs;
       end
 
       addr_hit[70]: begin
-        reg_rdata_next[0] = alert_en_shadowed_1_qs;
+        reg_rdata_next[0] = alert_regwen_64_qs;
       end
 
       addr_hit[71]: begin
-        reg_rdata_next[0] = alert_en_shadowed_2_qs;
+        reg_rdata_next[0] = alert_en_shadowed_0_qs;
       end
 
       addr_hit[72]: begin
-        reg_rdata_next[0] = alert_en_shadowed_3_qs;
+        reg_rdata_next[0] = alert_en_shadowed_1_qs;
       end
 
       addr_hit[73]: begin
-        reg_rdata_next[0] = alert_en_shadowed_4_qs;
+        reg_rdata_next[0] = alert_en_shadowed_2_qs;
       end
 
       addr_hit[74]: begin
-        reg_rdata_next[0] = alert_en_shadowed_5_qs;
+        reg_rdata_next[0] = alert_en_shadowed_3_qs;
       end
 
       addr_hit[75]: begin
-        reg_rdata_next[0] = alert_en_shadowed_6_qs;
+        reg_rdata_next[0] = alert_en_shadowed_4_qs;
       end
 
       addr_hit[76]: begin
-        reg_rdata_next[0] = alert_en_shadowed_7_qs;
+        reg_rdata_next[0] = alert_en_shadowed_5_qs;
       end
 
       addr_hit[77]: begin
-        reg_rdata_next[0] = alert_en_shadowed_8_qs;
+        reg_rdata_next[0] = alert_en_shadowed_6_qs;
       end
 
       addr_hit[78]: begin
-        reg_rdata_next[0] = alert_en_shadowed_9_qs;
+        reg_rdata_next[0] = alert_en_shadowed_7_qs;
       end
 
       addr_hit[79]: begin
-        reg_rdata_next[0] = alert_en_shadowed_10_qs;
+        reg_rdata_next[0] = alert_en_shadowed_8_qs;
       end
 
       addr_hit[80]: begin
-        reg_rdata_next[0] = alert_en_shadowed_11_qs;
+        reg_rdata_next[0] = alert_en_shadowed_9_qs;
       end
 
       addr_hit[81]: begin
-        reg_rdata_next[0] = alert_en_shadowed_12_qs;
+        reg_rdata_next[0] = alert_en_shadowed_10_qs;
       end
 
       addr_hit[82]: begin
-        reg_rdata_next[0] = alert_en_shadowed_13_qs;
+        reg_rdata_next[0] = alert_en_shadowed_11_qs;
       end
 
       addr_hit[83]: begin
-        reg_rdata_next[0] = alert_en_shadowed_14_qs;
+        reg_rdata_next[0] = alert_en_shadowed_12_qs;
       end
 
       addr_hit[84]: begin
-        reg_rdata_next[0] = alert_en_shadowed_15_qs;
+        reg_rdata_next[0] = alert_en_shadowed_13_qs;
       end
 
       addr_hit[85]: begin
-        reg_rdata_next[0] = alert_en_shadowed_16_qs;
+        reg_rdata_next[0] = alert_en_shadowed_14_qs;
       end
 
       addr_hit[86]: begin
-        reg_rdata_next[0] = alert_en_shadowed_17_qs;
+        reg_rdata_next[0] = alert_en_shadowed_15_qs;
       end
 
       addr_hit[87]: begin
-        reg_rdata_next[0] = alert_en_shadowed_18_qs;
+        reg_rdata_next[0] = alert_en_shadowed_16_qs;
       end
 
       addr_hit[88]: begin
-        reg_rdata_next[0] = alert_en_shadowed_19_qs;
+        reg_rdata_next[0] = alert_en_shadowed_17_qs;
       end
 
       addr_hit[89]: begin
-        reg_rdata_next[0] = alert_en_shadowed_20_qs;
+        reg_rdata_next[0] = alert_en_shadowed_18_qs;
       end
 
       addr_hit[90]: begin
-        reg_rdata_next[0] = alert_en_shadowed_21_qs;
+        reg_rdata_next[0] = alert_en_shadowed_19_qs;
       end
 
       addr_hit[91]: begin
-        reg_rdata_next[0] = alert_en_shadowed_22_qs;
+        reg_rdata_next[0] = alert_en_shadowed_20_qs;
       end
 
       addr_hit[92]: begin
-        reg_rdata_next[0] = alert_en_shadowed_23_qs;
+        reg_rdata_next[0] = alert_en_shadowed_21_qs;
       end
 
       addr_hit[93]: begin
-        reg_rdata_next[0] = alert_en_shadowed_24_qs;
+        reg_rdata_next[0] = alert_en_shadowed_22_qs;
       end
 
       addr_hit[94]: begin
-        reg_rdata_next[0] = alert_en_shadowed_25_qs;
+        reg_rdata_next[0] = alert_en_shadowed_23_qs;
       end
 
       addr_hit[95]: begin
-        reg_rdata_next[0] = alert_en_shadowed_26_qs;
+        reg_rdata_next[0] = alert_en_shadowed_24_qs;
       end
 
       addr_hit[96]: begin
-        reg_rdata_next[0] = alert_en_shadowed_27_qs;
+        reg_rdata_next[0] = alert_en_shadowed_25_qs;
       end
 
       addr_hit[97]: begin
-        reg_rdata_next[0] = alert_en_shadowed_28_qs;
+        reg_rdata_next[0] = alert_en_shadowed_26_qs;
       end
 
       addr_hit[98]: begin
-        reg_rdata_next[0] = alert_en_shadowed_29_qs;
+        reg_rdata_next[0] = alert_en_shadowed_27_qs;
       end
 
       addr_hit[99]: begin
-        reg_rdata_next[0] = alert_en_shadowed_30_qs;
+        reg_rdata_next[0] = alert_en_shadowed_28_qs;
       end
 
       addr_hit[100]: begin
-        reg_rdata_next[0] = alert_en_shadowed_31_qs;
+        reg_rdata_next[0] = alert_en_shadowed_29_qs;
       end
 
       addr_hit[101]: begin
-        reg_rdata_next[0] = alert_en_shadowed_32_qs;
+        reg_rdata_next[0] = alert_en_shadowed_30_qs;
       end
 
       addr_hit[102]: begin
-        reg_rdata_next[0] = alert_en_shadowed_33_qs;
+        reg_rdata_next[0] = alert_en_shadowed_31_qs;
       end
 
       addr_hit[103]: begin
-        reg_rdata_next[0] = alert_en_shadowed_34_qs;
+        reg_rdata_next[0] = alert_en_shadowed_32_qs;
       end
 
       addr_hit[104]: begin
-        reg_rdata_next[0] = alert_en_shadowed_35_qs;
+        reg_rdata_next[0] = alert_en_shadowed_33_qs;
       end
 
       addr_hit[105]: begin
-        reg_rdata_next[0] = alert_en_shadowed_36_qs;
+        reg_rdata_next[0] = alert_en_shadowed_34_qs;
       end
 
       addr_hit[106]: begin
-        reg_rdata_next[0] = alert_en_shadowed_37_qs;
+        reg_rdata_next[0] = alert_en_shadowed_35_qs;
       end
 
       addr_hit[107]: begin
-        reg_rdata_next[0] = alert_en_shadowed_38_qs;
+        reg_rdata_next[0] = alert_en_shadowed_36_qs;
       end
 
       addr_hit[108]: begin
-        reg_rdata_next[0] = alert_en_shadowed_39_qs;
+        reg_rdata_next[0] = alert_en_shadowed_37_qs;
       end
 
       addr_hit[109]: begin
-        reg_rdata_next[0] = alert_en_shadowed_40_qs;
+        reg_rdata_next[0] = alert_en_shadowed_38_qs;
       end
 
       addr_hit[110]: begin
-        reg_rdata_next[0] = alert_en_shadowed_41_qs;
+        reg_rdata_next[0] = alert_en_shadowed_39_qs;
       end
 
       addr_hit[111]: begin
-        reg_rdata_next[0] = alert_en_shadowed_42_qs;
+        reg_rdata_next[0] = alert_en_shadowed_40_qs;
       end
 
       addr_hit[112]: begin
-        reg_rdata_next[0] = alert_en_shadowed_43_qs;
+        reg_rdata_next[0] = alert_en_shadowed_41_qs;
       end
 
       addr_hit[113]: begin
-        reg_rdata_next[0] = alert_en_shadowed_44_qs;
+        reg_rdata_next[0] = alert_en_shadowed_42_qs;
       end
 
       addr_hit[114]: begin
-        reg_rdata_next[0] = alert_en_shadowed_45_qs;
+        reg_rdata_next[0] = alert_en_shadowed_43_qs;
       end
 
       addr_hit[115]: begin
-        reg_rdata_next[0] = alert_en_shadowed_46_qs;
+        reg_rdata_next[0] = alert_en_shadowed_44_qs;
       end
 
       addr_hit[116]: begin
-        reg_rdata_next[0] = alert_en_shadowed_47_qs;
+        reg_rdata_next[0] = alert_en_shadowed_45_qs;
       end
 
       addr_hit[117]: begin
-        reg_rdata_next[0] = alert_en_shadowed_48_qs;
+        reg_rdata_next[0] = alert_en_shadowed_46_qs;
       end
 
       addr_hit[118]: begin
-        reg_rdata_next[0] = alert_en_shadowed_49_qs;
+        reg_rdata_next[0] = alert_en_shadowed_47_qs;
       end
 
       addr_hit[119]: begin
-        reg_rdata_next[0] = alert_en_shadowed_50_qs;
+        reg_rdata_next[0] = alert_en_shadowed_48_qs;
       end
 
       addr_hit[120]: begin
-        reg_rdata_next[0] = alert_en_shadowed_51_qs;
+        reg_rdata_next[0] = alert_en_shadowed_49_qs;
       end
 
       addr_hit[121]: begin
-        reg_rdata_next[0] = alert_en_shadowed_52_qs;
+        reg_rdata_next[0] = alert_en_shadowed_50_qs;
       end
 
       addr_hit[122]: begin
-        reg_rdata_next[0] = alert_en_shadowed_53_qs;
+        reg_rdata_next[0] = alert_en_shadowed_51_qs;
       end
 
       addr_hit[123]: begin
-        reg_rdata_next[0] = alert_en_shadowed_54_qs;
+        reg_rdata_next[0] = alert_en_shadowed_52_qs;
       end
 
       addr_hit[124]: begin
-        reg_rdata_next[0] = alert_en_shadowed_55_qs;
+        reg_rdata_next[0] = alert_en_shadowed_53_qs;
       end
 
       addr_hit[125]: begin
-        reg_rdata_next[0] = alert_en_shadowed_56_qs;
+        reg_rdata_next[0] = alert_en_shadowed_54_qs;
       end
 
       addr_hit[126]: begin
-        reg_rdata_next[0] = alert_en_shadowed_57_qs;
+        reg_rdata_next[0] = alert_en_shadowed_55_qs;
       end
 
       addr_hit[127]: begin
-        reg_rdata_next[0] = alert_en_shadowed_58_qs;
+        reg_rdata_next[0] = alert_en_shadowed_56_qs;
       end
 
       addr_hit[128]: begin
-        reg_rdata_next[0] = alert_en_shadowed_59_qs;
+        reg_rdata_next[0] = alert_en_shadowed_57_qs;
       end
 
       addr_hit[129]: begin
-        reg_rdata_next[0] = alert_en_shadowed_60_qs;
+        reg_rdata_next[0] = alert_en_shadowed_58_qs;
       end
 
       addr_hit[130]: begin
-        reg_rdata_next[0] = alert_en_shadowed_61_qs;
+        reg_rdata_next[0] = alert_en_shadowed_59_qs;
       end
 
       addr_hit[131]: begin
-        reg_rdata_next[0] = alert_en_shadowed_62_qs;
+        reg_rdata_next[0] = alert_en_shadowed_60_qs;
       end
 
       addr_hit[132]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
+        reg_rdata_next[0] = alert_en_shadowed_61_qs;
       end
 
       addr_hit[133]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
+        reg_rdata_next[0] = alert_en_shadowed_62_qs;
       end
 
       addr_hit[134]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
+        reg_rdata_next[0] = alert_en_shadowed_63_qs;
       end
 
       addr_hit[135]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
+        reg_rdata_next[0] = alert_en_shadowed_64_qs;
       end
 
       addr_hit[136]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
       end
 
       addr_hit[137]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
       end
 
       addr_hit[138]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
       end
 
       addr_hit[139]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
       end
 
       addr_hit[140]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
       end
 
       addr_hit[141]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
       end
 
       addr_hit[142]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
       end
 
       addr_hit[143]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
       end
 
       addr_hit[144]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
       end
 
       addr_hit[145]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
       end
 
       addr_hit[146]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
       end
 
       addr_hit[147]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
       end
 
       addr_hit[148]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
       end
 
       addr_hit[149]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
       end
 
       addr_hit[150]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
       end
 
       addr_hit[151]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
       end
 
       addr_hit[152]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
       end
 
       addr_hit[153]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
       end
 
       addr_hit[154]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
       end
 
       addr_hit[155]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
       end
 
       addr_hit[156]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
       end
 
       addr_hit[157]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
       end
 
       addr_hit[158]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
       end
 
       addr_hit[159]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
       end
 
       addr_hit[160]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
       end
 
       addr_hit[161]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
       end
 
       addr_hit[162]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
       end
 
       addr_hit[163]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
       end
 
       addr_hit[164]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
       end
 
       addr_hit[165]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
       end
 
       addr_hit[166]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
       end
 
       addr_hit[167]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
       end
 
       addr_hit[168]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
       end
 
       addr_hit[169]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
       end
 
       addr_hit[170]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
       end
 
       addr_hit[171]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
       end
 
       addr_hit[172]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
       end
 
       addr_hit[173]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
       end
 
       addr_hit[174]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
       end
 
       addr_hit[175]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
       end
 
       addr_hit[176]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
       end
 
       addr_hit[177]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
       end
 
       addr_hit[178]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
       end
 
       addr_hit[179]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
       end
 
       addr_hit[180]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
       end
 
       addr_hit[181]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
       end
 
       addr_hit[182]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
       end
 
       addr_hit[183]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
       end
 
       addr_hit[184]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
       end
 
       addr_hit[185]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
       end
 
       addr_hit[186]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
       end
 
       addr_hit[187]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
       end
 
       addr_hit[188]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
       end
 
       addr_hit[189]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
       end
 
       addr_hit[190]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
       end
 
       addr_hit[191]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
       end
 
       addr_hit[192]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_60_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
       end
 
       addr_hit[193]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_61_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
       end
 
       addr_hit[194]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_62_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
       end
 
       addr_hit[195]: begin
-        reg_rdata_next[0] = alert_cause_0_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
       end
 
       addr_hit[196]: begin
-        reg_rdata_next[0] = alert_cause_1_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_60_qs;
       end
 
       addr_hit[197]: begin
-        reg_rdata_next[0] = alert_cause_2_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_61_qs;
       end
 
       addr_hit[198]: begin
-        reg_rdata_next[0] = alert_cause_3_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_62_qs;
       end
 
       addr_hit[199]: begin
-        reg_rdata_next[0] = alert_cause_4_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_63_qs;
       end
 
       addr_hit[200]: begin
-        reg_rdata_next[0] = alert_cause_5_qs;
+        reg_rdata_next[1:0] = alert_class_shadowed_64_qs;
       end
 
       addr_hit[201]: begin
-        reg_rdata_next[0] = alert_cause_6_qs;
+        reg_rdata_next[0] = alert_cause_0_qs;
       end
 
       addr_hit[202]: begin
-        reg_rdata_next[0] = alert_cause_7_qs;
+        reg_rdata_next[0] = alert_cause_1_qs;
       end
 
       addr_hit[203]: begin
-        reg_rdata_next[0] = alert_cause_8_qs;
+        reg_rdata_next[0] = alert_cause_2_qs;
       end
 
       addr_hit[204]: begin
-        reg_rdata_next[0] = alert_cause_9_qs;
+        reg_rdata_next[0] = alert_cause_3_qs;
       end
 
       addr_hit[205]: begin
-        reg_rdata_next[0] = alert_cause_10_qs;
+        reg_rdata_next[0] = alert_cause_4_qs;
       end
 
       addr_hit[206]: begin
-        reg_rdata_next[0] = alert_cause_11_qs;
+        reg_rdata_next[0] = alert_cause_5_qs;
       end
 
       addr_hit[207]: begin
-        reg_rdata_next[0] = alert_cause_12_qs;
+        reg_rdata_next[0] = alert_cause_6_qs;
       end
 
       addr_hit[208]: begin
-        reg_rdata_next[0] = alert_cause_13_qs;
+        reg_rdata_next[0] = alert_cause_7_qs;
       end
 
       addr_hit[209]: begin
-        reg_rdata_next[0] = alert_cause_14_qs;
+        reg_rdata_next[0] = alert_cause_8_qs;
       end
 
       addr_hit[210]: begin
-        reg_rdata_next[0] = alert_cause_15_qs;
+        reg_rdata_next[0] = alert_cause_9_qs;
       end
 
       addr_hit[211]: begin
-        reg_rdata_next[0] = alert_cause_16_qs;
+        reg_rdata_next[0] = alert_cause_10_qs;
       end
 
       addr_hit[212]: begin
-        reg_rdata_next[0] = alert_cause_17_qs;
+        reg_rdata_next[0] = alert_cause_11_qs;
       end
 
       addr_hit[213]: begin
-        reg_rdata_next[0] = alert_cause_18_qs;
+        reg_rdata_next[0] = alert_cause_12_qs;
       end
 
       addr_hit[214]: begin
-        reg_rdata_next[0] = alert_cause_19_qs;
+        reg_rdata_next[0] = alert_cause_13_qs;
       end
 
       addr_hit[215]: begin
-        reg_rdata_next[0] = alert_cause_20_qs;
+        reg_rdata_next[0] = alert_cause_14_qs;
       end
 
       addr_hit[216]: begin
-        reg_rdata_next[0] = alert_cause_21_qs;
+        reg_rdata_next[0] = alert_cause_15_qs;
       end
 
       addr_hit[217]: begin
-        reg_rdata_next[0] = alert_cause_22_qs;
+        reg_rdata_next[0] = alert_cause_16_qs;
       end
 
       addr_hit[218]: begin
-        reg_rdata_next[0] = alert_cause_23_qs;
+        reg_rdata_next[0] = alert_cause_17_qs;
       end
 
       addr_hit[219]: begin
-        reg_rdata_next[0] = alert_cause_24_qs;
+        reg_rdata_next[0] = alert_cause_18_qs;
       end
 
       addr_hit[220]: begin
-        reg_rdata_next[0] = alert_cause_25_qs;
+        reg_rdata_next[0] = alert_cause_19_qs;
       end
 
       addr_hit[221]: begin
-        reg_rdata_next[0] = alert_cause_26_qs;
+        reg_rdata_next[0] = alert_cause_20_qs;
       end
 
       addr_hit[222]: begin
-        reg_rdata_next[0] = alert_cause_27_qs;
+        reg_rdata_next[0] = alert_cause_21_qs;
       end
 
       addr_hit[223]: begin
-        reg_rdata_next[0] = alert_cause_28_qs;
+        reg_rdata_next[0] = alert_cause_22_qs;
       end
 
       addr_hit[224]: begin
-        reg_rdata_next[0] = alert_cause_29_qs;
+        reg_rdata_next[0] = alert_cause_23_qs;
       end
 
       addr_hit[225]: begin
-        reg_rdata_next[0] = alert_cause_30_qs;
+        reg_rdata_next[0] = alert_cause_24_qs;
       end
 
       addr_hit[226]: begin
-        reg_rdata_next[0] = alert_cause_31_qs;
+        reg_rdata_next[0] = alert_cause_25_qs;
       end
 
       addr_hit[227]: begin
-        reg_rdata_next[0] = alert_cause_32_qs;
+        reg_rdata_next[0] = alert_cause_26_qs;
       end
 
       addr_hit[228]: begin
-        reg_rdata_next[0] = alert_cause_33_qs;
+        reg_rdata_next[0] = alert_cause_27_qs;
       end
 
       addr_hit[229]: begin
-        reg_rdata_next[0] = alert_cause_34_qs;
+        reg_rdata_next[0] = alert_cause_28_qs;
       end
 
       addr_hit[230]: begin
-        reg_rdata_next[0] = alert_cause_35_qs;
+        reg_rdata_next[0] = alert_cause_29_qs;
       end
 
       addr_hit[231]: begin
-        reg_rdata_next[0] = alert_cause_36_qs;
+        reg_rdata_next[0] = alert_cause_30_qs;
       end
 
       addr_hit[232]: begin
-        reg_rdata_next[0] = alert_cause_37_qs;
+        reg_rdata_next[0] = alert_cause_31_qs;
       end
 
       addr_hit[233]: begin
-        reg_rdata_next[0] = alert_cause_38_qs;
+        reg_rdata_next[0] = alert_cause_32_qs;
       end
 
       addr_hit[234]: begin
-        reg_rdata_next[0] = alert_cause_39_qs;
+        reg_rdata_next[0] = alert_cause_33_qs;
       end
 
       addr_hit[235]: begin
-        reg_rdata_next[0] = alert_cause_40_qs;
+        reg_rdata_next[0] = alert_cause_34_qs;
       end
 
       addr_hit[236]: begin
-        reg_rdata_next[0] = alert_cause_41_qs;
+        reg_rdata_next[0] = alert_cause_35_qs;
       end
 
       addr_hit[237]: begin
-        reg_rdata_next[0] = alert_cause_42_qs;
+        reg_rdata_next[0] = alert_cause_36_qs;
       end
 
       addr_hit[238]: begin
-        reg_rdata_next[0] = alert_cause_43_qs;
+        reg_rdata_next[0] = alert_cause_37_qs;
       end
 
       addr_hit[239]: begin
-        reg_rdata_next[0] = alert_cause_44_qs;
+        reg_rdata_next[0] = alert_cause_38_qs;
       end
 
       addr_hit[240]: begin
-        reg_rdata_next[0] = alert_cause_45_qs;
+        reg_rdata_next[0] = alert_cause_39_qs;
       end
 
       addr_hit[241]: begin
-        reg_rdata_next[0] = alert_cause_46_qs;
+        reg_rdata_next[0] = alert_cause_40_qs;
       end
 
       addr_hit[242]: begin
-        reg_rdata_next[0] = alert_cause_47_qs;
+        reg_rdata_next[0] = alert_cause_41_qs;
       end
 
       addr_hit[243]: begin
-        reg_rdata_next[0] = alert_cause_48_qs;
+        reg_rdata_next[0] = alert_cause_42_qs;
       end
 
       addr_hit[244]: begin
-        reg_rdata_next[0] = alert_cause_49_qs;
+        reg_rdata_next[0] = alert_cause_43_qs;
       end
 
       addr_hit[245]: begin
-        reg_rdata_next[0] = alert_cause_50_qs;
+        reg_rdata_next[0] = alert_cause_44_qs;
       end
 
       addr_hit[246]: begin
-        reg_rdata_next[0] = alert_cause_51_qs;
+        reg_rdata_next[0] = alert_cause_45_qs;
       end
 
       addr_hit[247]: begin
-        reg_rdata_next[0] = alert_cause_52_qs;
+        reg_rdata_next[0] = alert_cause_46_qs;
       end
 
       addr_hit[248]: begin
-        reg_rdata_next[0] = alert_cause_53_qs;
+        reg_rdata_next[0] = alert_cause_47_qs;
       end
 
       addr_hit[249]: begin
-        reg_rdata_next[0] = alert_cause_54_qs;
+        reg_rdata_next[0] = alert_cause_48_qs;
       end
 
       addr_hit[250]: begin
-        reg_rdata_next[0] = alert_cause_55_qs;
+        reg_rdata_next[0] = alert_cause_49_qs;
       end
 
       addr_hit[251]: begin
-        reg_rdata_next[0] = alert_cause_56_qs;
+        reg_rdata_next[0] = alert_cause_50_qs;
       end
 
       addr_hit[252]: begin
-        reg_rdata_next[0] = alert_cause_57_qs;
+        reg_rdata_next[0] = alert_cause_51_qs;
       end
 
       addr_hit[253]: begin
-        reg_rdata_next[0] = alert_cause_58_qs;
+        reg_rdata_next[0] = alert_cause_52_qs;
       end
 
       addr_hit[254]: begin
-        reg_rdata_next[0] = alert_cause_59_qs;
+        reg_rdata_next[0] = alert_cause_53_qs;
       end
 
       addr_hit[255]: begin
-        reg_rdata_next[0] = alert_cause_60_qs;
+        reg_rdata_next[0] = alert_cause_54_qs;
       end
 
       addr_hit[256]: begin
-        reg_rdata_next[0] = alert_cause_61_qs;
+        reg_rdata_next[0] = alert_cause_55_qs;
       end
 
       addr_hit[257]: begin
-        reg_rdata_next[0] = alert_cause_62_qs;
+        reg_rdata_next[0] = alert_cause_56_qs;
       end
 
       addr_hit[258]: begin
-        reg_rdata_next[0] = loc_alert_regwen_0_qs;
+        reg_rdata_next[0] = alert_cause_57_qs;
       end
 
       addr_hit[259]: begin
-        reg_rdata_next[0] = loc_alert_regwen_1_qs;
+        reg_rdata_next[0] = alert_cause_58_qs;
       end
 
       addr_hit[260]: begin
-        reg_rdata_next[0] = loc_alert_regwen_2_qs;
+        reg_rdata_next[0] = alert_cause_59_qs;
       end
 
       addr_hit[261]: begin
-        reg_rdata_next[0] = loc_alert_regwen_3_qs;
+        reg_rdata_next[0] = alert_cause_60_qs;
       end
 
       addr_hit[262]: begin
-        reg_rdata_next[0] = loc_alert_regwen_4_qs;
+        reg_rdata_next[0] = alert_cause_61_qs;
       end
 
       addr_hit[263]: begin
-        reg_rdata_next[0] = loc_alert_regwen_5_qs;
+        reg_rdata_next[0] = alert_cause_62_qs;
       end
 
       addr_hit[264]: begin
-        reg_rdata_next[0] = loc_alert_regwen_6_qs;
+        reg_rdata_next[0] = alert_cause_63_qs;
       end
 
       addr_hit[265]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
+        reg_rdata_next[0] = alert_cause_64_qs;
       end
 
       addr_hit[266]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
+        reg_rdata_next[0] = loc_alert_regwen_0_qs;
       end
 
       addr_hit[267]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
+        reg_rdata_next[0] = loc_alert_regwen_1_qs;
       end
 
       addr_hit[268]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
+        reg_rdata_next[0] = loc_alert_regwen_2_qs;
       end
 
       addr_hit[269]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
+        reg_rdata_next[0] = loc_alert_regwen_3_qs;
       end
 
       addr_hit[270]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
+        reg_rdata_next[0] = loc_alert_regwen_4_qs;
       end
 
       addr_hit[271]: begin
-        reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
+        reg_rdata_next[0] = loc_alert_regwen_5_qs;
       end
 
       addr_hit[272]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
+        reg_rdata_next[0] = loc_alert_regwen_6_qs;
       end
 
       addr_hit[273]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
       end
 
       addr_hit[274]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
       end
 
       addr_hit[275]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
       end
 
       addr_hit[276]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
       end
 
       addr_hit[277]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
       end
 
       addr_hit[278]: begin
-        reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
       end
 
       addr_hit[279]: begin
-        reg_rdata_next[0] = loc_alert_cause_0_qs;
+        reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
       end
 
       addr_hit[280]: begin
-        reg_rdata_next[0] = loc_alert_cause_1_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
       end
 
       addr_hit[281]: begin
-        reg_rdata_next[0] = loc_alert_cause_2_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
       end
 
       addr_hit[282]: begin
-        reg_rdata_next[0] = loc_alert_cause_3_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
       end
 
       addr_hit[283]: begin
-        reg_rdata_next[0] = loc_alert_cause_4_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
       end
 
       addr_hit[284]: begin
-        reg_rdata_next[0] = loc_alert_cause_5_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
       end
 
       addr_hit[285]: begin
-        reg_rdata_next[0] = loc_alert_cause_6_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
       end
 
       addr_hit[286]: begin
-        reg_rdata_next[0] = classa_regwen_qs;
+        reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
       end
 
       addr_hit[287]: begin
+        reg_rdata_next[0] = loc_alert_cause_0_qs;
+      end
+
+      addr_hit[288]: begin
+        reg_rdata_next[0] = loc_alert_cause_1_qs;
+      end
+
+      addr_hit[289]: begin
+        reg_rdata_next[0] = loc_alert_cause_2_qs;
+      end
+
+      addr_hit[290]: begin
+        reg_rdata_next[0] = loc_alert_cause_3_qs;
+      end
+
+      addr_hit[291]: begin
+        reg_rdata_next[0] = loc_alert_cause_4_qs;
+      end
+
+      addr_hit[292]: begin
+        reg_rdata_next[0] = loc_alert_cause_5_qs;
+      end
+
+      addr_hit[293]: begin
+        reg_rdata_next[0] = loc_alert_cause_6_qs;
+      end
+
+      addr_hit[294]: begin
+        reg_rdata_next[0] = classa_regwen_qs;
+      end
+
+      addr_hit[295]: begin
         reg_rdata_next[0] = classa_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs;
@@ -18364,59 +18756,59 @@
         reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[288]: begin
+      addr_hit[296]: begin
         reg_rdata_next[0] = classa_clr_regwen_qs;
       end
 
-      addr_hit[289]: begin
+      addr_hit[297]: begin
         reg_rdata_next[0] = classa_clr_shadowed_qs;
       end
 
-      addr_hit[290]: begin
+      addr_hit[298]: begin
         reg_rdata_next[15:0] = classa_accum_cnt_qs;
       end
 
-      addr_hit[291]: begin
+      addr_hit[299]: begin
         reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[292]: begin
+      addr_hit[300]: begin
         reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[293]: begin
+      addr_hit[301]: begin
         reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[294]: begin
+      addr_hit[302]: begin
         reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[295]: begin
+      addr_hit[303]: begin
         reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[296]: begin
+      addr_hit[304]: begin
         reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[297]: begin
+      addr_hit[305]: begin
         reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[298]: begin
+      addr_hit[306]: begin
         reg_rdata_next[31:0] = classa_esc_cnt_qs;
       end
 
-      addr_hit[299]: begin
+      addr_hit[307]: begin
         reg_rdata_next[2:0] = classa_state_qs;
       end
 
-      addr_hit[300]: begin
+      addr_hit[308]: begin
         reg_rdata_next[0] = classb_regwen_qs;
       end
 
-      addr_hit[301]: begin
+      addr_hit[309]: begin
         reg_rdata_next[0] = classb_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs;
@@ -18429,59 +18821,59 @@
         reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[302]: begin
+      addr_hit[310]: begin
         reg_rdata_next[0] = classb_clr_regwen_qs;
       end
 
-      addr_hit[303]: begin
+      addr_hit[311]: begin
         reg_rdata_next[0] = classb_clr_shadowed_qs;
       end
 
-      addr_hit[304]: begin
+      addr_hit[312]: begin
         reg_rdata_next[15:0] = classb_accum_cnt_qs;
       end
 
-      addr_hit[305]: begin
+      addr_hit[313]: begin
         reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[306]: begin
+      addr_hit[314]: begin
         reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[307]: begin
+      addr_hit[315]: begin
         reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[308]: begin
+      addr_hit[316]: begin
         reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[309]: begin
+      addr_hit[317]: begin
         reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[310]: begin
+      addr_hit[318]: begin
         reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[311]: begin
+      addr_hit[319]: begin
         reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[312]: begin
+      addr_hit[320]: begin
         reg_rdata_next[31:0] = classb_esc_cnt_qs;
       end
 
-      addr_hit[313]: begin
+      addr_hit[321]: begin
         reg_rdata_next[2:0] = classb_state_qs;
       end
 
-      addr_hit[314]: begin
+      addr_hit[322]: begin
         reg_rdata_next[0] = classc_regwen_qs;
       end
 
-      addr_hit[315]: begin
+      addr_hit[323]: begin
         reg_rdata_next[0] = classc_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs;
@@ -18494,59 +18886,59 @@
         reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[316]: begin
+      addr_hit[324]: begin
         reg_rdata_next[0] = classc_clr_regwen_qs;
       end
 
-      addr_hit[317]: begin
+      addr_hit[325]: begin
         reg_rdata_next[0] = classc_clr_shadowed_qs;
       end
 
-      addr_hit[318]: begin
+      addr_hit[326]: begin
         reg_rdata_next[15:0] = classc_accum_cnt_qs;
       end
 
-      addr_hit[319]: begin
+      addr_hit[327]: begin
         reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[320]: begin
+      addr_hit[328]: begin
         reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[321]: begin
+      addr_hit[329]: begin
         reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[322]: begin
+      addr_hit[330]: begin
         reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[323]: begin
+      addr_hit[331]: begin
         reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[324]: begin
+      addr_hit[332]: begin
         reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[325]: begin
+      addr_hit[333]: begin
         reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[326]: begin
+      addr_hit[334]: begin
         reg_rdata_next[31:0] = classc_esc_cnt_qs;
       end
 
-      addr_hit[327]: begin
+      addr_hit[335]: begin
         reg_rdata_next[2:0] = classc_state_qs;
       end
 
-      addr_hit[328]: begin
+      addr_hit[336]: begin
         reg_rdata_next[0] = classd_regwen_qs;
       end
 
-      addr_hit[329]: begin
+      addr_hit[337]: begin
         reg_rdata_next[0] = classd_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs;
@@ -18559,51 +18951,51 @@
         reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[330]: begin
+      addr_hit[338]: begin
         reg_rdata_next[0] = classd_clr_regwen_qs;
       end
 
-      addr_hit[331]: begin
+      addr_hit[339]: begin
         reg_rdata_next[0] = classd_clr_shadowed_qs;
       end
 
-      addr_hit[332]: begin
+      addr_hit[340]: begin
         reg_rdata_next[15:0] = classd_accum_cnt_qs;
       end
 
-      addr_hit[333]: begin
+      addr_hit[341]: begin
         reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[334]: begin
+      addr_hit[342]: begin
         reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[335]: begin
+      addr_hit[343]: begin
         reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[336]: begin
+      addr_hit[344]: begin
         reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[337]: begin
+      addr_hit[345]: begin
         reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[338]: begin
+      addr_hit[346]: begin
         reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[339]: begin
+      addr_hit[347]: begin
         reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[340]: begin
+      addr_hit[348]: begin
         reg_rdata_next[31:0] = classd_esc_cnt_qs;
       end
 
-      addr_hit[341]: begin
+      addr_hit[349]: begin
         reg_rdata_next[2:0] = classd_state_qs;
       end
 
@@ -18703,6 +19095,8 @@
     alert_en_shadowed_60_storage_err,
     alert_en_shadowed_61_storage_err,
     alert_en_shadowed_62_storage_err,
+    alert_en_shadowed_63_storage_err,
+    alert_en_shadowed_64_storage_err,
     alert_class_shadowed_0_storage_err,
     alert_class_shadowed_1_storage_err,
     alert_class_shadowed_2_storage_err,
@@ -18766,6 +19160,8 @@
     alert_class_shadowed_60_storage_err,
     alert_class_shadowed_61_storage_err,
     alert_class_shadowed_62_storage_err,
+    alert_class_shadowed_63_storage_err,
+    alert_class_shadowed_64_storage_err,
     loc_alert_en_shadowed_0_storage_err,
     loc_alert_en_shadowed_1_storage_err,
     loc_alert_en_shadowed_2_storage_err,
@@ -18919,6 +19315,8 @@
     alert_en_shadowed_60_update_err,
     alert_en_shadowed_61_update_err,
     alert_en_shadowed_62_update_err,
+    alert_en_shadowed_63_update_err,
+    alert_en_shadowed_64_update_err,
     alert_class_shadowed_0_update_err,
     alert_class_shadowed_1_update_err,
     alert_class_shadowed_2_update_err,
@@ -18982,6 +19380,8 @@
     alert_class_shadowed_60_update_err,
     alert_class_shadowed_61_update_err,
     alert_class_shadowed_62_update_err,
+    alert_class_shadowed_63_update_err,
+    alert_class_shadowed_64_update_err,
     loc_alert_en_shadowed_0_update_err,
     loc_alert_en_shadowed_1_update_err,
     loc_alert_en_shadowed_2_update_err,
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index 3204c4a..53226a2 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -740,6 +740,8 @@
   logic flash_power_down_h;
   logic flash_power_ready_h;
   ast_pkg::ast_dif_t flash_alert;
+  assign flash_alert.p = 1'b0;
+  assign flash_alert.n = 1'b1;
 
   // clock bypass req/ack
   prim_mubi_pkg::mubi4_t io_clk_byp_req;
@@ -1115,7 +1117,6 @@
     .flash_bist_enable_i          ( flash_bist_enable          ),
     .flash_power_down_h_i         ( flash_power_down_h         ),
     .flash_power_ready_h_i        ( flash_power_ready_h        ),
-    .flash_alert_o                ( flash_alert                ),
     .flash_obs_o                  ( fla_obs                    ),
     .es_rng_req_o                 ( es_rng_req                 ),
     .es_rng_rsp_i                 ( es_rng_rsp                 ),
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
index 191d500..a17d6e1 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
@@ -701,6 +701,8 @@
   logic flash_power_down_h;
   logic flash_power_ready_h;
   ast_pkg::ast_dif_t flash_alert;
+  assign flash_alert.p = 1'b0;
+  assign flash_alert.n = 1'b1;
 
   // clock bypass req/ack
   prim_mubi_pkg::mubi4_t io_clk_byp_req;
@@ -1033,7 +1035,6 @@
     .flash_power_down_h_i         ( 1'b0                  ),
     .flash_power_ready_h_i        ( 1'b1                  ),
     .flash_obs_o                  ( flash_obs             ),
-    .flash_alert_o                ( flash_alert           ),
     .io_clk_byp_req_o             ( io_clk_byp_req        ),
     .io_clk_byp_ack_i             ( io_clk_byp_ack        ),
     .all_clk_byp_req_o            ( all_clk_byp_req       ),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 76ac69c..3cc91bd 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -141,7 +141,6 @@
   output prim_mubi_pkg::mubi4_t       hi_speed_sel_o,
   input  prim_mubi_pkg::mubi4_t       div_step_down_req_i,
   input  logic       calib_rdy_i,
-  output ast_pkg::ast_dif_t       flash_alert_o,
   input  prim_mubi_pkg::mubi4_t       flash_bist_enable_i,
   input  logic       flash_power_down_h_i,
   input  logic       flash_power_ready_h_i,
@@ -2053,7 +2052,7 @@
       .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
   );
   flash_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:35]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:35]),
     .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
     .RndCnstDataKey(RndCnstFlashCtrlDataKey),
     .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds),
@@ -2083,8 +2082,10 @@
       // [35]: recov_err
       // [36]: fatal_std_err
       // [37]: fatal_err
-      .alert_tx_o  ( alert_tx[37:35] ),
-      .alert_rx_i  ( alert_rx[37:35] ),
+      // [38]: fatal_prim_flash_alert
+      // [39]: recov_prim_flash_alert
+      .alert_tx_o  ( alert_tx[39:35] ),
+      .alert_rx_i  ( alert_rx[39:35] ),
 
       // Inter-module signals
       .otp_o(flash_ctrl_otp_req),
@@ -2095,7 +2096,6 @@
       .flash_power_ready_h_i(flash_power_ready_h_i),
       .flash_test_mode_a_io(flash_test_mode_a_io),
       .flash_test_voltage_h_io(flash_test_voltage_h_io),
-      .flash_alert_o(flash_alert_o),
       .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
       .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en),
       .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en),
@@ -2127,12 +2127,12 @@
       .rst_otp_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
   );
   rv_dm #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]),
     .IdcodeValue(RvDmIdcodeValue)
   ) u_rv_dm (
-      // [38]: fatal_fault
-      .alert_tx_o  ( alert_tx[38:38] ),
-      .alert_rx_i  ( alert_rx[38:38] ),
+      // [40]: fatal_fault
+      .alert_tx_o  ( alert_tx[40:40] ),
+      .alert_rx_i  ( alert_rx[40:40] ),
 
       // Inter-module signals
       .jtag_i(pinmux_aon_rv_jtag_req),
@@ -2156,11 +2156,11 @@
       .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
   );
   rv_plic #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:39])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41])
   ) u_rv_plic (
-      // [39]: fatal_fault
-      .alert_tx_o  ( alert_tx[39:39] ),
-      .alert_rx_i  ( alert_rx[39:39] ),
+      // [41]: fatal_fault
+      .alert_tx_o  ( alert_tx[41:41] ),
+      .alert_rx_i  ( alert_rx[41:41] ),
 
       // Inter-module signals
       .irq_o(rv_plic_irq),
@@ -2175,7 +2175,7 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   aes #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
     .AES192Enable(1'b1),
     .SecMasking(SecAesMasking),
     .SecSBoxImpl(SecAesSBoxImpl),
@@ -2188,10 +2188,10 @@
     .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
     .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm)
   ) u_aes (
-      // [40]: recov_ctrl_update_err
-      // [41]: fatal_fault
-      .alert_tx_o  ( alert_tx[41:40] ),
-      .alert_rx_i  ( alert_rx[41:40] ),
+      // [42]: recov_ctrl_update_err
+      // [43]: fatal_fault
+      .alert_tx_o  ( alert_tx[43:42] ),
+      .alert_rx_i  ( alert_rx[43:42] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[0]),
@@ -2210,16 +2210,16 @@
       .rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   hmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:42])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44])
   ) u_hmac (
 
       // Interrupt
       .intr_hmac_done_o  (intr_hmac_hmac_done),
       .intr_fifo_empty_o (intr_hmac_fifo_empty),
       .intr_hmac_err_o   (intr_hmac_hmac_err),
-      // [42]: fatal_fault
-      .alert_tx_o  ( alert_tx[42:42] ),
-      .alert_rx_i  ( alert_rx[42:42] ),
+      // [44]: fatal_fault
+      .alert_tx_o  ( alert_tx[44:44] ),
+      .alert_rx_i  ( alert_rx[44:44] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[1]),
@@ -2231,7 +2231,7 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   kmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
     .EnMasking(KmacEnMasking),
     .SecCmdDelay(SecKmacCmdDelay),
     .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg),
@@ -2245,10 +2245,10 @@
       .intr_kmac_done_o  (intr_kmac_kmac_done),
       .intr_fifo_empty_o (intr_kmac_fifo_empty),
       .intr_kmac_err_o   (intr_kmac_kmac_err),
-      // [43]: recov_operation_err
-      // [44]: fatal_fault_err
-      .alert_tx_o  ( alert_tx[44:43] ),
-      .alert_rx_i  ( alert_rx[44:43] ),
+      // [45]: recov_operation_err
+      // [46]: fatal_fault_err
+      .alert_tx_o  ( alert_tx[46:45] ),
+      .alert_rx_i  ( alert_rx[46:45] ),
 
       // Inter-module signals
       .keymgr_key_i(keymgr_kmac_key),
@@ -2270,7 +2270,7 @@
       .rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   otbn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
     .Stub(OtbnStub),
     .RegFile(OtbnRegFile),
     .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed),
@@ -2280,10 +2280,10 @@
 
       // Interrupt
       .intr_done_o (intr_otbn_done),
-      // [45]: fatal
-      // [46]: recov
-      .alert_tx_o  ( alert_tx[46:45] ),
-      .alert_rx_i  ( alert_rx[46:45] ),
+      // [47]: fatal
+      // [48]: recov
+      .alert_tx_o  ( alert_tx[48:47] ),
+      .alert_rx_i  ( alert_rx[48:47] ),
 
       // Inter-module signals
       .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
@@ -2310,7 +2310,7 @@
       .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
   );
   keymgr #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]),
     .KmacEnMasking(KeymgrKmacEnMasking),
     .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
     .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
@@ -2330,10 +2330,10 @@
 
       // Interrupt
       .intr_op_done_o (intr_keymgr_op_done),
-      // [47]: recov_operation_err
-      // [48]: fatal_fault_err
-      .alert_tx_o  ( alert_tx[48:47] ),
-      .alert_rx_i  ( alert_rx[48:47] ),
+      // [49]: recov_operation_err
+      // [50]: fatal_fault_err
+      .alert_tx_o  ( alert_tx[50:49] ),
+      .alert_rx_i  ( alert_rx[50:49] ),
 
       // Inter-module signals
       .edn_o(edn0_edn_req[0]),
@@ -2361,7 +2361,7 @@
       .rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   csrng #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]),
     .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
     .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
     .SBoxImpl(CsrngSBoxImpl)
@@ -2372,10 +2372,10 @@
       .intr_cs_entropy_req_o  (intr_csrng_cs_entropy_req),
       .intr_cs_hw_inst_exc_o  (intr_csrng_cs_hw_inst_exc),
       .intr_cs_fatal_err_o    (intr_csrng_cs_fatal_err),
-      // [49]: recov_alert
-      // [50]: fatal_alert
-      .alert_tx_o  ( alert_tx[50:49] ),
-      .alert_rx_i  ( alert_rx[50:49] ),
+      // [51]: recov_alert
+      // [52]: fatal_alert
+      .alert_tx_o  ( alert_tx[52:51] ),
+      .alert_rx_i  ( alert_rx[52:51] ),
 
       // Inter-module signals
       .csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2394,7 +2394,7 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   entropy_src #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]),
     .Stub(EntropySrcStub)
   ) u_entropy_src (
 
@@ -2403,10 +2403,10 @@
       .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
       .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
       .intr_es_fatal_err_o          (intr_entropy_src_es_fatal_err),
-      // [51]: recov_alert
-      // [52]: fatal_alert
-      .alert_tx_o  ( alert_tx[52:51] ),
-      .alert_rx_i  ( alert_rx[52:51] ),
+      // [53]: recov_alert
+      // [54]: fatal_alert
+      .alert_tx_o  ( alert_tx[54:53] ),
+      .alert_rx_i  ( alert_rx[54:53] ),
 
       // Inter-module signals
       .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2428,16 +2428,16 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55])
   ) u_edn0 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn0_edn_fatal_err),
-      // [53]: recov_alert
-      // [54]: fatal_alert
-      .alert_tx_o  ( alert_tx[54:53] ),
-      .alert_rx_i  ( alert_rx[54:53] ),
+      // [55]: recov_alert
+      // [56]: fatal_alert
+      .alert_tx_o  ( alert_tx[56:55] ),
+      .alert_rx_i  ( alert_rx[56:55] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2452,16 +2452,16 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57])
   ) u_edn1 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn1_edn_fatal_err),
-      // [55]: recov_alert
-      // [56]: fatal_alert
-      .alert_tx_o  ( alert_tx[56:55] ),
-      .alert_rx_i  ( alert_rx[56:55] ),
+      // [57]: recov_alert
+      // [58]: fatal_alert
+      .alert_tx_o  ( alert_tx[58:57] ),
+      .alert_rx_i  ( alert_rx[58:57] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2476,7 +2476,7 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   sram_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:57]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:59]),
     .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
     .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
     .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
@@ -2484,9 +2484,9 @@
     .MemSizeRam(131072),
     .InstrExec(SramCtrlMainInstrExec)
   ) u_sram_ctrl_main (
-      // [57]: fatal_error
-      .alert_tx_o  ( alert_tx[57:57] ),
-      .alert_rx_i  ( alert_rx[57:57] ),
+      // [59]: fatal_error
+      .alert_tx_o  ( alert_tx[59:59] ),
+      .alert_rx_i  ( alert_rx[59:59] ),
 
       // Inter-module signals
       .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2507,15 +2507,15 @@
       .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
   );
   rom_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:58]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]),
     .BootRomInitFile(RomCtrlBootRomInitFile),
     .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
     .RndCnstScrKey(RndCnstRomCtrlScrKey),
     .SecDisableScrambling(SecRomCtrlDisableScrambling)
   ) u_rom_ctrl (
-      // [58]: fatal
-      .alert_tx_o  ( alert_tx[58:58] ),
-      .alert_rx_i  ( alert_rx[58:58] ),
+      // [60]: fatal
+      .alert_tx_o  ( alert_tx[60:60] ),
+      .alert_rx_i  ( alert_rx[60:60] ),
 
       // Inter-module signals
       .rom_cfg_i(ast_rom_cfg),
@@ -2533,7 +2533,7 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
   );
   rv_core_ibex #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[62:59]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64:61]),
     .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed),
     .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm),
     .RndCnstIbexKeyDefault(RndCnstRvCoreIbexIbexKeyDefault),
@@ -2560,12 +2560,12 @@
     .DmExceptionAddr(RvCoreIbexDmExceptionAddr),
     .PipeLine(RvCoreIbexPipeLine)
   ) u_rv_core_ibex (
-      // [59]: fatal_sw_err
-      // [60]: recov_sw_err
-      // [61]: fatal_hw_err
-      // [62]: recov_hw_err
-      .alert_tx_o  ( alert_tx[62:59] ),
-      .alert_rx_i  ( alert_rx[62:59] ),
+      // [61]: fatal_sw_err
+      // [62]: recov_sw_err
+      // [63]: fatal_hw_err
+      // [64]: recov_hw_err
+      .alert_tx_o  ( alert_tx[64:61] ),
+      .alert_rx_i  ( alert_rx[64:61] ),
 
       // Inter-module signals
       .rst_cpu_n_o(),
diff --git a/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
index b10d033..382a5bb 100644
--- a/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
@@ -250,7 +250,8 @@
   assign otp_alert.n = 1'b1;
 
   logic ast_init_done;
-
+  assign flash_alert.p = 1'b0;
+  assign flash_alert.n = 1'b1;
 
   ast #(
     .EntropyStreams(ast_pkg::EntropyStreams),
@@ -452,7 +453,6 @@
     .flash_bist_enable_i          ( flash_bist_enable          ),
     .flash_power_down_h_i         ( flash_power_down_h         ),
     .flash_power_ready_h_i        ( flash_power_ready_h        ),
-    .flash_alert_o                ( flash_alert                ),
     .es_rng_req_o                 ( es_rng_req                 ),
     .es_rng_rsp_i                 ( es_rng_rsp                 ),
     .es_rng_fips_o                ( es_rng_fips                ),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 8b2fe3d..4f8638f 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -210,7 +210,7 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[63] = {
+    top_earlgrey_alert_for_peripheral[65] = {
   [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0,
   [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1,
   [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2,
@@ -249,6 +249,8 @@
   [kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
   [kTopEarlgreyAlertIdFlashCtrlFatalStdErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
   [kTopEarlgreyAlertIdFlashCtrlFatalErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
+  [kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl,
+  [kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl,
   [kTopEarlgreyAlertIdRvDmFatalFault] = kTopEarlgreyAlertPeripheralRvDm,
   [kTopEarlgreyAlertIdRvPlicFatalFault] = kTopEarlgreyAlertPeripheralRvPlic,
   [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index ad2797c..e9b93f7 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1322,32 +1322,34 @@
   kTopEarlgreyAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
   kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
   kTopEarlgreyAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
-  kTopEarlgreyAlertIdRvDmFatalFault = 38, /**< rv_dm_fatal_fault */
-  kTopEarlgreyAlertIdRvPlicFatalFault = 39, /**< rv_plic_fatal_fault */
-  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 40, /**< aes_recov_ctrl_update_err */
-  kTopEarlgreyAlertIdAesFatalFault = 41, /**< aes_fatal_fault */
-  kTopEarlgreyAlertIdHmacFatalFault = 42, /**< hmac_fatal_fault */
-  kTopEarlgreyAlertIdKmacRecovOperationErr = 43, /**< kmac_recov_operation_err */
-  kTopEarlgreyAlertIdKmacFatalFaultErr = 44, /**< kmac_fatal_fault_err */
-  kTopEarlgreyAlertIdOtbnFatal = 45, /**< otbn_fatal */
-  kTopEarlgreyAlertIdOtbnRecov = 46, /**< otbn_recov */
-  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 47, /**< keymgr_recov_operation_err */
-  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 48, /**< keymgr_fatal_fault_err */
-  kTopEarlgreyAlertIdCsrngRecovAlert = 49, /**< csrng_recov_alert */
-  kTopEarlgreyAlertIdCsrngFatalAlert = 50, /**< csrng_fatal_alert */
-  kTopEarlgreyAlertIdEntropySrcRecovAlert = 51, /**< entropy_src_recov_alert */
-  kTopEarlgreyAlertIdEntropySrcFatalAlert = 52, /**< entropy_src_fatal_alert */
-  kTopEarlgreyAlertIdEdn0RecovAlert = 53, /**< edn0_recov_alert */
-  kTopEarlgreyAlertIdEdn0FatalAlert = 54, /**< edn0_fatal_alert */
-  kTopEarlgreyAlertIdEdn1RecovAlert = 55, /**< edn1_recov_alert */
-  kTopEarlgreyAlertIdEdn1FatalAlert = 56, /**< edn1_fatal_alert */
-  kTopEarlgreyAlertIdSramCtrlMainFatalError = 57, /**< sram_ctrl_main_fatal_error */
-  kTopEarlgreyAlertIdRomCtrlFatal = 58, /**< rom_ctrl_fatal */
-  kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 59, /**< rv_core_ibex_fatal_sw_err */
-  kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 60, /**< rv_core_ibex_recov_sw_err */
-  kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 61, /**< rv_core_ibex_fatal_hw_err */
-  kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 62, /**< rv_core_ibex_recov_hw_err */
-  kTopEarlgreyAlertIdLast = 62, /**< \internal The Last Valid Alert ID. */
+  kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
+  kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
+  kTopEarlgreyAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
+  kTopEarlgreyAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
+  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */
+  kTopEarlgreyAlertIdAesFatalFault = 43, /**< aes_fatal_fault */
+  kTopEarlgreyAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */
+  kTopEarlgreyAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */
+  kTopEarlgreyAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */
+  kTopEarlgreyAlertIdOtbnFatal = 47, /**< otbn_fatal */
+  kTopEarlgreyAlertIdOtbnRecov = 48, /**< otbn_recov */
+  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
+  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
+  kTopEarlgreyAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
+  kTopEarlgreyAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
+  kTopEarlgreyAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
+  kTopEarlgreyAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
+  kTopEarlgreyAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
+  kTopEarlgreyAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
+  kTopEarlgreyAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
+  kTopEarlgreyAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
+  kTopEarlgreyAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
+  kTopEarlgreyAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
+  kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 61, /**< rv_core_ibex_fatal_sw_err */
+  kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 62, /**< rv_core_ibex_recov_sw_err */
+  kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 63, /**< rv_core_ibex_fatal_hw_err */
+  kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 64, /**< rv_core_ibex_recov_hw_err */
+  kTopEarlgreyAlertIdLast = 64, /**< \internal The Last Valid Alert ID. */
 } top_earlgrey_alert_id_t;
 
 /**
@@ -1357,7 +1359,7 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 extern const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[63];
+    top_earlgrey_alert_for_peripheral[65];
 
 #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
 
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index a71ee44..46595b0 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -662,7 +662,6 @@
         'clkmgr_aon.all_clk_byp_ack'   : 'all_clk_byp_ack',
         'clkmgr_aon.io_clk_byp_req'    : 'io_clk_byp_req',
         'clkmgr_aon.io_clk_byp_ack'    : 'io_clk_byp_ack',
-        'flash_ctrl.flash_alert'          : 'flash_alert',
         'flash_ctrl.flash_bist_enable'    : 'flash_bist_enable',
         'flash_ctrl.flash_power_down_h'   : 'flash_power_down_h',
         'flash_ctrl.flash_power_ready_h'  : 'flash_power_ready_h',
diff --git a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c
index 02f4741..e7e58ae 100644
--- a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c
+++ b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c
@@ -40,6 +40,12 @@
     case kDifFlashCtrlAlertFatalErr:
       alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT;
       break;
+    case kDifFlashCtrlAlertFatalPrimFlashAlert:
+      alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_BIT;
+      break;
+    case kDifFlashCtrlAlertRecovPrimFlashAlert:
+      alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_BIT;
+      break;
     default:
       return kDifBadArg;
   }
diff --git a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h
index 6583633..0cef3e0 100644
--- a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h
+++ b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h
@@ -66,6 +66,15 @@
    * Flash fatal errors
    */
   kDifFlashCtrlAlertFatalErr = 2,
+  /**
+   * Fatal alert triggered inside the flash primitive, including fatal TL-UL bus
+   * integrity faults of the test interface.
+   */
+  kDifFlashCtrlAlertFatalPrimFlashAlert = 3,
+  /**
+   * Recoverable alert triggered inside the flash primitive.
+   */
+  kDifFlashCtrlAlertRecovPrimFlashAlert = 4,
 } dif_flash_ctrl_alert_t;
 
 /**
diff --git a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc
index 44df3c8..88c0a5d 100644
--- a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc
@@ -57,9 +57,9 @@
 
   // Force last alert.
   EXPECT_WRITE32(FLASH_CTRL_ALERT_TEST_REG_OFFSET,
-                 {{FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT, true}});
-  EXPECT_DIF_OK(
-      dif_flash_ctrl_alert_force(&flash_ctrl_, kDifFlashCtrlAlertFatalErr));
+                 {{FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_BIT, true}});
+  EXPECT_DIF_OK(dif_flash_ctrl_alert_force(
+      &flash_ctrl_, kDifFlashCtrlAlertRecovPrimFlashAlert));
 }
 
 class IrqGetStateTest : public FlashCtrlTest {};
diff --git a/sw/device/tests/autogen/alert_test.c b/sw/device/tests/autogen/alert_test.c
index c068bdc..20f95fd 100644
--- a/sw/device/tests/autogen/alert_test.c
+++ b/sw/device/tests/autogen/alert_test.c
@@ -401,7 +401,7 @@
   }
 
   // Write flash_ctrl's alert_test reg and check alert_cause.
-  for (int i = 0; i < 3; ++i) {
+  for (int i = 0; i < 5; ++i) {
     CHECK_DIF_OK(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovErr + i));
 
     // Verify that alert handler received it.
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 87f5643..4c1a044 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -521,6 +521,8 @@
   logic flash_power_down_h;
   logic flash_power_ready_h;
   ast_pkg::ast_dif_t flash_alert;
+  assign flash_alert.p = 1'b0;
+  assign flash_alert.n = 1'b1;
 
   // clock bypass req/ack
   prim_mubi_pkg::mubi4_t io_clk_byp_req;
@@ -956,7 +958,6 @@
     .flash_bist_enable_i          ( flash_bist_enable          ),
     .flash_power_down_h_i         ( flash_power_down_h         ),
     .flash_power_ready_h_i        ( flash_power_ready_h        ),
-    .flash_alert_o                ( flash_alert                ),
     .flash_obs_o                  ( fla_obs                    ),
     .es_rng_req_o                 ( es_rng_req                 ),
     .es_rng_rsp_i                 ( es_rng_rsp                 ),
@@ -1126,7 +1127,6 @@
     .flash_power_down_h_i         ( 1'b0                  ),
     .flash_power_ready_h_i        ( 1'b1                  ),
     .flash_obs_o                  ( flash_obs             ),
-    .flash_alert_o                ( flash_alert           ),
     .io_clk_byp_req_o             ( io_clk_byp_req        ),
     .io_clk_byp_ack_i             ( io_clk_byp_ack        ),
     .all_clk_byp_req_o            ( all_clk_byp_req       ),