commit 87be84ee07f73107f64476891120a3c47226af13
author Michael Hoang <hoangm@google.com> Mon Jul 17 22:10:31 2023 +0000
committer Michael Hoang <hoangm@google.com> Mon Jul 17 22:10:31 2023 +0000
tree 72d5acaa129dceac62759bf59f670b2af3a9d4f5
parent 1e8879224f0cbc50d6d637f8e6bd4ec2aeeeba5c

Change rv_dm port bitwidth to # of harts on matcha

Change-Id: I8026509e671ecd7d5b26f3819d6e8db215afbeee

hw/ip/rv_dm/data/rv_dm.hjson

diff --git a/hw/ip/rv_dm/data/rv_dm.hjson b/hw/ip/rv_dm/data/rv_dm.hjson
index 0c8407f..eced431 100644
--- a/hw/ip/rv_dm/data/rv_dm.hjson
+++ b/hw/ip/rv_dm/data/rv_dm.hjson
@@ -90,7 +90,7 @@
       type:    "uni"
       name:    "unavailable"
       act:     "rcv"
-      default: "1'b0"
+      default: "2'b0"
       desc:    '''
                This signal indicates to the debug module that the main processor is not available
                for debug (e.g. due to a low-power state).