UART Checklist

This checklist is for Hardware Stage transitions for the UART peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneUART Spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80N/A
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D1 Exceptions

PHYSICAL_MACROS_DEFINED_80 is waived as UART doesn't have memories inside.

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESN/A
DocumentationBLOCK_DIAGRAMN/A
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCN/A
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODone
RTLSTYLE_XDone
RTLCDC_SYNCMACRON/A
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDoneArea check done (on FPGA)
Code QualityTIMING_CHECKDoneFmax 50MHz on NexysVideo
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSN/A
SecuritySEC_CM_SHADOW_REGSN/A
SecuritySEC_CM_RTL_REVIEWEDN/A
SecuritySEC_CM_COUNCIL_REVIEWEDN/AThis block only contains the bus-integrity CM.

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3N/A
RTLTODO_COMPLETEDone
Code QualityLINT_COMPLETEDone
Code QualityCDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff
Code QualityRDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff
ReviewREVIEW_RTLDone
ReviewREVIEW_DELETED_FFWaivedNo block-level flow available - waived to top-level signoff
ReviewREVIEW_SW_CHANGEDoneby awill@
ReviewREVIEW_SW_ERRATADone
Security[SEC_NON_RESET_FLOPS][]N/A
Security[SEC_SHADOW_REGS][]N/A
ReviewReviewer(s)Doneeunchan@ jeoong@ weicai@ awill@
ReviewSignoff dateDone2022-06-16

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDoneUART DV document
DocumentationTESTPLAN_COMPLETEDDoneUART Testplan
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_CREATEDDone
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDone
TestbenchCSR_CHECK_GEN_AUTOMATEDwaivedRevisit later. Tool setup in progress.
TestbenchTB_GEN_AUTOMATEDN/A
TestsSIM_SMOKE_TEST_PASSINGDone
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDone
TestsFPV_MAIN_ASSERTIONS_PROVENN/A
Tool SetupSIM_ALT_TOOL_SETUPDone
RegressionSIM_SMOKE_REGRESSION_SETUPDoneException (implemented in local)
RegressionSIM_NIGHTLY_REGRESSION_SETUPDoneException (implemented in local)
RegressionFPV_REGRESSION_SETUPN/A
CoverageSIM_COVERAGE_MODEL_ADDEDDone
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1N/AExcept for IP module
ReviewDESIGN_SPEC_REVIEWEDDone
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDDoneException (Security, Power, Debug)
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2N/A
DocumentationDV_DOC_COMPLETEDDone
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDNot Started
TestbenchALL_INTERFACES_EXERCISEDDone
TestbenchALL_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_COMPLETEDDone
TestsSIM_ALL_TESTS_PASSINGDone
TestsFPV_ALL_ASSERTIONS_WRITTENN/A
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDN/A
TestsSIM_FW_SIMULATEDN/A
RegressionSIM_NIGHTLY_REGRESSION_V2Done
CoverageSIM_CODE_COVERAGE_V2Done
CoverageSIM_FUNCTIONAL_COVERAGE_V2Done
CoverageFPV_CODE_COVERAGE_V2N/A
CoverageFPV_COI_COVERAGE_V2N/A
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGDone
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDDone
IntegrationPRE_VERIFIED_SUB_MODULES_V2N/A
ReviewDV_DOC_TESTPLAN_REVIEWEDNot Started
ReviewV3_CHECKLIST_SCOPEDDone

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDNot Started
TestsFPV_SEC_CM_VERIFIEDNot Started
TestsSIM_SEC_CM_VERIFIEDNot Started
CoverageSIM_COVERAGE_REVIEWEDNot Started
ReviewSEC_CM_DV_REVIEWEDNot Started

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3N/A
TestsX_PROP_ANALYSIS_COMPLETEDWaivedRevisit later. Tool setup in progress
TestsFPV_ASSERTIONS_PROVEN_AT_V3N/A
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Done
CoverageSIM_CODE_COVERAGE_AT_100Donecommon_cov_excl.el, uart_cov_excl.el
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Done
CoverageFPV_CODE_COVERAGE_AT_100N/A
CoverageFPV_COI_COVERAGE_AT_100N/A
Code QualityALL_TODOS_RESOLVEDDone
Code QualityNO_TOOL_WARNINGS_THROWNDone
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3N/A
IssuesNO_ISSUES_PENDINGDone
ReviewReviewer(s)Done@eunchan @sjgitty @sriyerg
ReviewSignoff dateDone2019-11-01