SRAM_CTRL Checklist

This checklist is for Hardware Stage transitions for the SRAM_CTRL peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneSRAM_CTRL Design Spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLMEM_INSTANCED_80Done
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESDone
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCDone
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODone
RTLSTYLE_XDone
RTLCDC_SYNCMACRODone
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code QualityTIMING_CHECKDone
SecuritySEC_CM_DOCUMENTEDDone

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTDone
SecuritySEC_CM_NON_RESET_FLOPSDone
SecuritySEC_CM_SHADOW_REGSDone
SecuritySEC_CM_RTL_REVIEWEDDone
SecuritySEC_CM_COUNCIL_REVIEWEDDone

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Done
RTLTODO_COMPLETEDone
Code QualityLINT_COMPLETEDone
Code QualityCDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff.
ReviewREVIEW_RTLDone
ReviewREVIEW_DELETED_FFWaivedNo block-level flow available - waived to top-level signoff.
ReviewREVIEW_SW_CHANGEDone
ReviewREVIEW_SW_ERRATADone
ReviewReviewer(s)Donemsf@ weicai@ tjaychen@ gac@
ReviewSignoff dateDone2022-07-15

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDone
DocumentationTESTPLAN_COMPLETEDDone
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_CREATEDDone
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDone
TestbenchCSR_CHECK_GEN_AUTOMATEDDone
TestbenchTB_GEN_AUTOMATEDN/A
TestsSIM_SMOKE_TEST_PASSINGDone
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDone
TestsFPV_MAIN_ASSERTIONS_PROVENN/A
Tool SetupSIM_ALT_TOOL_SETUPDone
RegressionSIM_SMOKE_REGRESSION_SETUPDone
RegressionSIM_NIGHTLY_REGRESSION_SETUPDone
RegressionFPV_REGRESSION_SETUPDone
CoverageSIM_COVERAGE_MODEL_ADDEDDone
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1Done
ReviewDESIGN_SPEC_REVIEWEDDone
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDDoneException (Security/Power/Debug)
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Done
DocumentationDV_DOC_COMPLETEDDone
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDDone
TestbenchALL_INTERFACES_EXERCISEDDone
TestbenchALL_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_COMPLETEDDone
TestsSIM_ALL_TESTS_PASSINGDone
TestsFPV_ALL_ASSERTIONS_WRITTENN/A
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDN/A
TestsSIM_FW_SIMULATEDDone
RegressionSIM_NIGHTLY_REGRESSION_V2Done
CoverageSIM_CODE_COVERAGE_V2Done
CoverageSIM_FUNCTIONAL_COVERAGE_V2Done
CoverageFPV_CODE_COVERAGE_V2N/A
CoverageFPV_COI_COVERAGE_V2N/A
IntegrationPRE_VERIFIED_SUB_MODULES_V2Doneprim_prince and prim_lfsr are verified in separated TBs
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGDone
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDDone
ReviewDV_DOC_TESTPLAN_REVIEWEDDone
ReviewV3_CHECKLIST_SCOPEDDone

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDDone
TestsFPV_SEC_CM_VERIFIEDDoneSub-module prim_count is proven in FPV
TestsSIM_SEC_CM_VERIFIEDDone
CoverageSIM_COVERAGE_REVIEWEDDone
ReviewSEC_CM_DV_REVIEWEDDone

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started