Ibex Processor Core Checklist

This checklist is for Hardware Stage transitions for the Ibex Processor Core. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDone
DocumentationCSR_DEFINEDDonelowRISC/ibex#307
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80N/A
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDone

D1 Exceptions

PHYSICAL_MACROS_DEFINED_80 is waived as Ibex doesn't have memories inside.

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESN/A
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCN/A
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODoneMinor TODOs remain, waived
RTLSTYLE_XDonewill be reworked (#366)
RTLCDC_SYNCMACRODone
Code QualityLINT_PASSDoneLint waivers created, not finalized
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDoneArea smoke check done (on FPGA)
Code QualityTIMING_CHECKDoneFPGA timing acceptable
SecuritySEC_CM_DOCUMENTEDDone

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTDone
SecuritySEC_CM_NON_RESET_FLOPSDone
SecuritySEC_CM_SHADOW_REGSDone
SecuritySEC_CM_RTL_REVIEWEDDone
SecuritySEC_CM_COUNCIL_REVIEWEDDone

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not Started
RTLTODO_COMPLETENot Started
Code QualityLINT_COMPLETENot Started
Code QualityCDC_COMPLETENot Started
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLNot Started
ReviewREVIEW_DELETED_FFNot Started
ReviewREVIEW_SW_CHANGENot Started
ReviewREVIEW_SW_ERRATANot Started

Verification Checklist

Ibex verification is tracked in the Ibex documentation. Ibex is at V2S.

Features specific to rv_core_ibex do not have block-level verification. Top-level testing suffices for these, see the rv_core_ibex DV document for more details.

V1

The V1 checklist may be found in the Ibex documentation.

V2

The V2 checklist may be found in the Ibex documentation.

V2S

The V2S checklist may be found in the Ibex documentation.

V3

The V3 checklist may be found in the Ibex documentation.