hw/ip/otp_ctrl/data/otp_ctrl_img_creator_sw_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Use the gen-otp-img.py script to convert this configuration into
// a MEM file for preloading the OTP in FPGA synthesis or simulation.
//

{
    // The partition and item names must correspond with the OTP memory map.
    partitions: [
        {
            name:  "CREATOR_SW_CFG",
            items: [
                {
                    name:  "CREATOR_SW_CFG_DIGEST",
                    value: "0x0",
                },
                {
                    name: "CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN",
                    // Use software mod_exp implementation for signature
                    // verification. See the definition of `hardened_bool_t` in
                    // sw/device/lib/base/hardened.h.
                    value: "0x739",
                },
                {
                    name: "CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN",
                    // Mark the first three keys as valid and remaining as
                    // invalid since we currently have only three keys. See the
                    // definition of `hardened_byte_bool_t` in
                    // sw/device/lib/base/hardened.h.
                    value: "0x4b4b4b4b4ba5a5a5",
                },
                {
                    name: "CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG",
                    // Default values for flash scramble / ecc / he_en. This OTP
                    // word contains byte-aligned, packed, 4-bit mubi values.
                    // See the flash_ctrl driver bitfield definitions in
                    // sw/device/silicon_creator/lib/drivers/flash_ctrl.h.
                    value: "0x0",
                },
                {
                    name: "CREATOR_SW_CFG_RNG_EN",
                    // Enable use of entropy for countermeasures. See the
                    // definition of `hardened_bool_t` in
                    // sw/device/lib/base/hardened.h.
                    value: "0x739",
                },
                {
                    name: "CREATOR_SW_CFG_ROM_EXEC_EN",
                    // ROM execution is enabled if this item is set to a
                    // non-zero value.
                    value: "0xffffffff",
                },
                {
                    name: "CREATOR_SW_CFG_CPUCTRL",
                    // Value to write to the `cpuctrl` CSR in `rom_init()`.
                    // Note: Only bits 5:0 are written to the `cpuctrl` CSR.
                    // See: https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-register-cpuctrl
                    value: "0x1",
                },
                {
                    name:  "CREATOR_SW_CFG_JITTER_EN",
                    value: "0x9",
                },
                {
                    name: "CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT",
                    // Value of the min_security_version_rom_ext field of the
                    // default boot data.
                    value: "0x0",
                },
                {
                    name: "CREATOR_SW_CFG_MIN_SEC_VER_BL0",
                    // Value of the min_security_version_bl0 field of the
                    // default boot data.
                    value: "0x0",
                },
                {
                    name: "CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN",
                    // Enable the default boot data in PROD and PROD_END life
                    // cycle states. See the definition of `hardened_bool_t` in
                    // sw/device/lib/base/hardened.h.
                    value: "0x739",
                },
                {
                    name: "CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS",
                    value: "0xffffffff",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS",
                    value: "0xffffffff",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS",
                    value: "0xffffffff",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS",
                    value: "0x0",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS",
                    value: "0xffffffff",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS",
                    value: "0xffffffff",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS",
                    value: "0x0",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS",
                    value: "0xffffffff",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS",
                    value: "0x0",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_ALERT_THRESHOLD",
                    value: "0xfffd0002",
                }
                {
                    name: "CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST",
                    value: "0x8264cf75",
                }
                {
                    // Using the default register reset value. Two consecutive
                    // failures trigger an alert.
                    name: "CREATOR_SW_CFG_RNG_ALERT_THRESHOLD",
                    value: "0xfffd0002",
                }
            ],
        }
    ]
}