)]}'
{
  "commit": "7ffe17d951f56a2ea385c8d6488c0343cef0d302",
  "tree": "28f9499fe46dce34955da93d26c1dda15ed51e62",
  "parents": [
    "f198c7f6552c1cdc251aa35de2d38942d9a6da0b"
  ],
  "author": {
    "name": "Rupert Swarbrick",
    "email": "rswarbrick@lowrisc.org",
    "time": "Fri Sep 25 15:23:04 2020 +0100"
  },
  "committer": {
    "name": "Rupert Swarbrick",
    "email": "rswarbrick@gmail.com",
    "time": "Mon Sep 28 17:56:35 2020 +0100"
  },
  "message": "[otbn] Make registers much more explicit in the ISS\n\nThis patch defines a new class for registers (called Reg, in reg.py).\nIt\u0027s a bit simpler than the riscvmodel version, but the big difference\nis that it has no magic coercions. If you want to get the value as an\nunsigned integer, you call Reg.read_unsigned. If you want set the\nvalue as a signed integer, you call Reg.write_signed. It\u0027s all very\nexplicit, which should hopefully catch corner cases in the spec.\n\nreg.py also defines a RegFile class, to hold the registers. This is\nused as-is for the wide registers, but is subclassed for GPRs in\ngpr.py. This allows us to give x0 and x1 special behaviour (a zeros\nregister and a call stack, respectively).\n\nMost of the rest of this patch is porting the instruction definitions\nin insn.py to use the new register interface. Because there are no\nmagic coercions, the definitions get rather longer, but they are\nhopefully easier to understand.\n\nOne notable change from the previous Register class is that you get an\nassertion error if you try to assign an integer that\u0027s out of range.\nSo state.gprs.get_reg(1).write_unsigned(1 \u003c\u003c 32) will trigger an\nerror. This means that code that does arithmetic on operands generally\ngains an explicit mask \"foo \u0026 ((1 \u003c\u003c 32) - 1)\". This was an\nintentional design decision, because it means the code in\ninsn.py (which defines what the instruction does) fully specifies the\nsemantics, rather than relying on magic inside the Register class.\n\nSimilarly, the register files no longer override __getitem__ and\n__setitem__. I think the result is less magical and the syntax more\naccurately shows what\u0027s actually happening in the Python simulation.\nThe plan is that when we do automatic extraction from the ISS to the\nspec examples, we\u0027ll do some sort of transformation, turning e.g.\n\n    val1 \u003d state.gprs.get_reg(self.grs1).read_unsigned()\n    ...\n    state.gprs.get_reg(self.grd).write_unsigned(result)\n\nto something more like\n\n    val \u003d unsigned(state.gprs[self.grs1])\n    ...\n    state.gprs[self.grd] \u003d from_unsigned(result)\n\nSo the \"trace the assignments\" approach to reading the documentation\nworks again.\n\nWhen porting the instruction definitions, I made one intentional\nchange to behaviour (to match the intended semantics): If a big number\nALU instruction specifies a right shift of shift_bytes, it\u0027s now a\nlogical right shift, rather than an arithmetic one.\n\nI also got rid of most updates to variable values in the instruction\ndefinitions, so they are now in a sort of \"pseudo-SSA style\". This\ntends to be more convenient when you\u0027re looking at pseudo-code\ndocumentation, especially when debugging or trying to write formal\ndefinitions, because you can say \"foo\" rather than \"the value of foo\nat line 12\".\n\nSigned-off-by: Rupert Swarbrick \u003crswarbrick@lowrisc.org\u003e\n",
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