diff --git a/hw/ip/alert_handler/data/alert_handler.hjson b/hw/ip/alert_handler/data/alert_handler.hjson
index df261b2..1a048b4 100644
--- a/hw/ip/alert_handler/data/alert_handler.hjson
+++ b/hw/ip/alert_handler/data/alert_handler.hjson
@@ -201,6 +201,9 @@
                   hwaccess: "hro",
                   regwen:   "REGEN",
                   cname:    "alert",
+                  tags:     [// Enable `alert_en` might cause top-level escalators to trigger
+                             // unexpected reset
+                             "excl:CsrAllTests:CsrExclWrite"]
                   fields: [
                     { bits: "0",
                       name: "EN_A",
diff --git a/hw/ip/alert_handler/data/alert_handler.hjson.tpl b/hw/ip/alert_handler/data/alert_handler.hjson.tpl
index cea2831..082ffc7 100644
--- a/hw/ip/alert_handler/data/alert_handler.hjson.tpl
+++ b/hw/ip/alert_handler/data/alert_handler.hjson.tpl
@@ -195,7 +195,10 @@
                   hwaccess: "hro",
                   regwen:   "REGEN",
                   cname:    "alert",
-                  fields: [
+                  tags:     [// Enable `alert_en` might cause top-level escalators to trigger
+                             // unexpected reset
+                             "excl:CsrAllTests:CsrExclWrite"]
+                 fields: [
                     { bits: "0",
                       name: "EN_A",
                       desc: "Alert enable "
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index cfca5f5..0c189ac 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -209,7 +209,10 @@
                   hwaccess: "hro",
                   regwen:   "REGEN",
                   cname:    "alert",
-                  fields: [
+                  tags:     [// Enable `alert_en` might cause top-level escalators to trigger
+                             // unexpected reset
+                             "excl:CsrAllTests:CsrExclWrite"]
+                 fields: [
                     { bits: "0",
                       name: "EN_A",
                       desc: "Alert enable "
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 2de341b..d7da9b6 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -1344,7 +1344,7 @@
     genreg['hwqe'] = 'true' if name in testreg_names else 'false'
     genreg['hwre'] = 'false'
     # Add tags.
-    if name in testreg_names:
+    if name == 'INTR_TEST':
         # intr_test csr is WO which - it reads back 0s
         genreg['tags'] = ["excl:CsrNonInitTests:CsrExclWrite"]
     elif name == 'INTR_STATE':