tree b686d1db0bc90d09b011eb4ecb87bb8d8e00db1a
parent 58f3297109e4c51b6c68386f14323ac441287082
author Weicai Yang <weicai@google.com> 1615853180 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> 1615930274 -0700

[uart/dv] Fix regression failure

Reduce TL delay when uart clock is fast to have more margin to predict
status and interrupt correctly
Reduce num_trans for stess_all, as very a few cases may run over 3hr

Signed-off-by: Weicai Yang <weicai@google.com>