)]}'
{
  "commit": "7e4e4d21e78f8f06d551ada4a553c26bf8a53037",
  "tree": "b686d1db0bc90d09b011eb4ecb87bb8d8e00db1a",
  "parents": [
    "58f3297109e4c51b6c68386f14323ac441287082"
  ],
  "author": {
    "name": "Weicai Yang",
    "email": "weicai@google.com",
    "time": "Mon Mar 15 17:06:20 2021 -0700"
  },
  "committer": {
    "name": "weicaiyang",
    "email": "49293026+weicaiyang@users.noreply.github.com",
    "time": "Tue Mar 16 14:31:14 2021 -0700"
  },
  "message": "[uart/dv] Fix regression failure\n\nReduce TL delay when uart clock is fast to have more margin to predict\nstatus and interrupt correctly\nReduce num_trans for stess_all, as very a few cases may run over 3hr\n\nSigned-off-by: Weicai Yang \u003cweicai@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a8555a498dfeb58ebaad9751329c07982592033c",
      "old_mode": 33188,
      "old_path": "hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv",
      "new_id": "8e5dd675d5c2c5678773cd2a4e389e55fbc89bd6",
      "new_mode": 33188,
      "new_path": "hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv"
    },
    {
      "type": "modify",
      "old_id": "d002e8526f0442d4bd08fc0845cb30f99057778b",
      "old_mode": 33188,
      "old_path": "hw/ip/uart/dv/env/seq_lib/uart_stress_all_vseq.sv",
      "new_id": "52cfe0f02bd505b58de60d1dfc75ea1c3eb2a9de",
      "new_mode": 33188,
      "new_path": "hw/ip/uart/dv/env/seq_lib/uart_stress_all_vseq.sv"
    }
  ]
}