tree 0dc01361b62bf1e139444355d58d2bb700f30b74
parent 7ab48eddf9a251f2fcff78d8a38860a2476cc9c2
author Srikrishna Iyer <sriyer@google.com> 1590118087 -0700
committer sriyerg <46467186+sriyerg@users.noreply.github.com> 1590541042 -0700

[dv] Refactor watchdog_ok_to_end

- Found an issue where chip level DV sim was not exiting gracefully.
- I started debugging it and ended up refactoring it a bit to make it
more streamlined.
- watchdog timer ensures that `ok_to_end` stays asserted for 1 period
- `phase_ready_to_end` can now raise the objection again (if there are
other components that are not yet done and can trigger more activity on
`this` component.

Signed-off-by: Srikrishna Iyer <sriyer@google.com>