)]}'
{
  "commit": "7bdd9575f954017bb930cb738e52ef4d7040237b",
  "tree": "0dc01361b62bf1e139444355d58d2bb700f30b74",
  "parents": [
    "7ab48eddf9a251f2fcff78d8a38860a2476cc9c2"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Thu May 21 20:28:07 2020 -0700"
  },
  "committer": {
    "name": "sriyerg",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Tue May 26 17:57:22 2020 -0700"
  },
  "message": "[dv] Refactor watchdog_ok_to_end\n\n- Found an issue where chip level DV sim was not exiting gracefully.\n- I started debugging it and ended up refactoring it a bit to make it\nmore streamlined.\n- watchdog timer ensures that `ok_to_end` stays asserted for 1 period\n- `phase_ready_to_end` can now raise the objection again (if there are\nother components that are not yet done and can trigger more activity on\n`this` component.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "013651802d5ddcc06b826ba15955674c13002650",
      "old_mode": 33188,
      "old_path": "hw/dv/sv/dv_lib/dv_base_monitor.sv",
      "new_id": "17283cadccde413aebef1b3f7ad00cd443153b21",
      "new_mode": 33188,
      "new_path": "hw/dv/sv/dv_lib/dv_base_monitor.sv"
    }
  ]
}