diff --git a/hw/ip/aes/dv/aes_sim_cfg.hjson b/hw/ip/aes/dv/aes_sim_cfg.hjson
index 16e84b6..25e299a 100644
--- a/hw/ip/aes/dv/aes_sim_cfg.hjson
+++ b/hw/ip/aes/dv/aes_sim_cfg.hjson
@@ -46,6 +46,9 @@
   uvm_test: aes_base_test
   uvm_test_seq: aes_wake_up_vseq
 
+  // AES specific exclusions
+  xcelium_cov_refine_files: ["{proj_root}/hw/ip/aes/dv/cov/aes_cov.vRefine"]
+
   // Update all builds to add options specific to AES C model compilation.
   en_build_modes: ["{tool}_aes_model_build_opts"]
 
diff --git a/hw/ip/aes/dv/cov/aes_cov.vRefine b/hw/ip/aes/dv/cov/aes_cov.vRefine
new file mode 100644
index 0000000..6bf4ae7
--- /dev/null
+++ b/hw/ip/aes/dv/cov/aes_cov.vRefine
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="ISO-8859-1" standalone="no"?>
+<refinement-file-root>
+  <information comment-version="1" creation-time="Thu 04 Mar 2021 01:47:06 PST" creator="rasmus.madsen" csCheck="false" modified-by="rasmus.madsen" modify-time="Wed 10 Mar 2021 01:54:48 PST" save-ref-method="seq" tool-version="Cadence vManager20.09" rules-signature-c="e2743b896ba5cfea53f1e8edcd36a1">
+    <ucm-files>
+    </ucm-files>
+    <ccf-files>
+    </ccf-files>
+  </information>
+  <rules>
+    <rule ccType="inst" comment="0" domain="icc" entityName="aes/&quot;tl_i.a_param&quot;" entityType="toggle" excTime="1615370069" name="exclude" reviewer="rasmus" user="1" vscope="default"></rule>
+    <rule ccType="inst" domain="icc" entityName="aes/&quot;tl_o.d_param&quot;" entityType="toggle" excTime="1615369582" name="exclude" reviewer="unknown" user="1" vscope="default"></rule>
+    <rule ccType="inst" domain="icc" entityName="aes/&quot;tl_o.d_sink&quot;" entityType="toggle" excTime="1615369582" name="exclude" reviewer="unknown" user="1" vscope="default"></rule>
+  </rules>
+  <cache-map>
+    <cache-entry key="0" value="[NOT SUPPORTED] This is excluded from the common exclusion file
+as the port is not used in the design"></cache-entry>
+    <cache-entry key="1" value="rasmus.madsen"></cache-entry>
+  </cache-map>
+</refinement-file-root>