)]}'
{
  "commit": "7285a9896cdc7521c312f0cdddfcee9a5ea9dcf6",
  "tree": "b675c0c4086779a398490dcb2c5207e361e6499b",
  "parents": [
    "7dd3eecd746fc0c6aa415de7299948ccde861350"
  ],
  "author": {
    "name": "Cindy Chen",
    "email": "chencindy@google.com",
    "time": "Wed Oct 28 17:53:39 2020 -0700"
  },
  "committer": {
    "name": "cindychip",
    "email": "cindy.chen0316@gmail.com",
    "time": "Thu Oct 29 10:58:00 2020 -0700"
  },
  "message": "[dv/top] fix alert_monitor phase_ready_to_end timeout\n\nRandom CSR rw might trigger alert. Some alerts will conintuously be triggered until reset\napplied, which will cause alert_monitor phase_ready_to_end timeout.\nThis commit solves it by adding a reset at post_start().\n\nSigned-off-by: Cindy Chen \u003cchencindy@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "85e0d9f3445822c28bd9a1f5dea4c8f53590ca8e",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv",
      "new_id": "adddb22831db0b0cad8124d443797466436f2097",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv"
    }
  ]
}