| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| // Name of the sim cfg - typically same as the name of the DUT. |
| name: |
| otbn |
| |
| // Top level dut name (sv module). |
| dut: otbn |
| |
| // Top level testbench name (sv module). |
| tb: tb |
| |
| // Simulator used to sign off this block |
| tool: xcelium |
| |
| // Fusesoc core file used for building the file list. |
| fusesoc_core: lowrisc:dv:otbn_sim:0.1 |
| |
| otbn_dir: "{proj_root}/hw/ip/otbn" |
| |
| // Testplan hjson file. |
| testplan: "{otbn_dir}/data/otbn_testplan.hjson" |
| |
| exports: [ |
| { REPO_TOP: "{proj_root}" }, |
| ] |
| |
| // Import additional common sim cfg files. |
| // TODO: remove imported cfgs that do not apply. |
| import_cfgs: [ |
| // Project wide common sim cfg file |
| "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", |
| // Config files to get the correct flags for otbn_memutil and otbn_tracer |
| "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", |
| "{otbn_dir}/dv/memutil/otbn_memutil_sim_opts.hjson", |
| "{otbn_dir}/dv/tracer/otbn_tracer_sim_opts.hjson", |
| // Common CIP test lists |
| "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", |
| "{proj_root}/hw/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson" |
| ] |
| |
| // Add options needed to compile against otbn_memutil, otbn_tracer, and |
| // memutil_dpi_scrambled. |
| en_build_modes: ["{tool}_otbn_memutil_build_opts", |
| "{tool}_otbn_tracer_build_opts", |
| "{tool}_memutil_dpi_scrambled_build_opts"] |
| |
| // Add additional tops for simulation. |
| sim_tops: ["otbn_bind", "sec_cm_prim_sparse_fsm_flop_bind", "sec_cm_prim_onehot_check_bind", |
| "sec_cm_prim_count_bind"] |
| |
| // Default iterations for all tests - each test entry can override this. |
| reseed: 50 |
| |
| // Default UVM test and seq class name. |
| uvm_test: otbn_base_test |
| uvm_test_seq: otbn_base_vseq |
| |
| // The default place to find and build ELF binaries. If you have |
| // some pre-built binaries, you can run the simulation with them by using |
| // --run-opts to override the otbn_elf_dir plusarg in run_opts. |
| otbn_elf_dir: "{run_dir}/otbn-binaries" |
| |
| run_opts: ["+otbn_elf_dir={otbn_elf_dir}"] |
| |
| // The default build mode, used for the tests explicitly listed below does not |
| // require any pre-build steps. |
| build_modes: [ |
| { |
| name: default |
| pre_build_cmds: [] |
| } |
| ] |
| |
| // The value to pass to the --size parameter for gen-binaries.py. This |
| // controls the number of instructions that are run before ECALL or error. |
| binary_size: 2000 |
| |
| // This runs bazel to locate the RV32 toolchain, needed by gen-binaries.py. |
| setup_env: "pushd {proj_root}; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd;" |
| gen_binaries_py: "{setup_env} {otbn_dir}/dv/uvm/gen-binaries.py" |
| |
| rnd_args: "--seed {seed} --size {binary_size}" |
| gen_fixed: "{gen_binaries_py}" |
| gen_rnd: "{gen_binaries_py} {rnd_args}" |
| |
| smoke_dir: "{otbn_dir}/dv/smoke" |
| multi_err_dir: "{otbn_dir}/dv/otbnsim/test/simple/multi" |
| |
| run_modes: [ |
| // Run the random instruction generator and builds the one resulting binary |
| // in {otbn_elf_dir}. If you override the otbn_elf_dir plusarg with |
| // --run-opts, we'll still build the binary (but will ignore it). |
| { |
| name: build_otbn_rig_binary_mode |
| pre_run_cmds: [ |
| "{gen_rnd} --count 1 {otbn_elf_dir}" |
| ] |
| } |
| |
| // Run the random instruction generator several times and build the |
| // resulting binaries in {otbn_elf_dir}. |
| { |
| name: build_otbn_rig_binaries_mode |
| pre_run_cmds: [ |
| "{gen_rnd} --count 10 {otbn_elf_dir}" |
| ] |
| } |
| |
| // Build the smoke test in {otbn_elf_dir}. |
| { |
| name: build_otbn_smoke_binary_mode |
| pre_run_cmds: [ |
| "{gen_fixed} --src-dir {smoke_dir} {otbn_elf_dir}" |
| ] |
| } |
| |
| // Build the multi-error tests in {otbn_elf_dir}. |
| { |
| name: build_otbn_multi_err_binaries_mode |
| pre_run_cmds: [ |
| "{gen_fixed} --src-dir {multi_err_dir} {otbn_elf_dir}" |
| ] |
| } |
| ] |
| |
| // List of test specifications. |
| tests: [ |
| { |
| name: "otbn_smoke" |
| uvm_test_seq: "otbn_smoke_vseq" |
| en_run_modes: ["build_otbn_smoke_binary_mode"] |
| // Run just one smoke test: it's a fixed binary and there's not much |
| // interaction with the environment so there's probably not much point |
| // in running it loads of times. |
| reseed: 1 |
| } |
| |
| { |
| name: "otbn_single" |
| uvm_test_seq: "otbn_single_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 100 |
| } |
| |
| // This test runs 10 binaries each time, so we give it a reseed value |
| // that's much less than for otbn_single: these tests should equally good |
| // at catching errors within a single run, so the coverage that they give |
| // is specifically to do with improper clearing of state when starting or |
| // ending an operation. |
| { |
| name: "otbn_multi" |
| uvm_test_seq: "otbn_multi_vseq" |
| en_run_modes: ["build_otbn_rig_binaries_mode"] |
| reseed: 10 |
| } |
| |
| // This test asserts reset somewhere in the middle of an operation. It is |
| // good for flushing out testbench bugs that are triggered on a reset, but |
| // it will also catch incorrect initialisation of state and hit some |
| // FSM/toggle coverage points that need a reset. |
| { |
| name: "otbn_reset" |
| uvm_test_seq: "otbn_reset_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 10 |
| } |
| |
| // This test runs a fixed set of binaries, one after the other. Since this |
| // is essentially a directed test, there's probably no real benefit to |
| // running it more than once. |
| { |
| name: "otbn_multi_err" |
| uvm_test_seq: "otbn_sequential_vseq" |
| en_run_modes: ["build_otbn_multi_err_binaries_mode"] |
| reseed: 1 |
| } |
| |
| // This test causes a fault in the middle of an execution by triggering an |
| // IMEM error. We run it several times because (historically) some of the |
| // bugs it has found have been depended on unfortunate timing coincidences, |
| // so we want to have a chance of seeing them. |
| { |
| name: "otbn_imem_err" |
| uvm_test_seq: "otbn_imem_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 10 |
| } |
| |
| // This test causes a fault in the middle of an execution by triggering an |
| // DMEM error. As with the IMEM case, we want a reasonable number of |
| // reseeds to see awkward timing corners. Also, there's a possibility of an |
| // otbn_dmem_err test not actually generating an error (if we don't load |
| // from DMEM after invalidating it), so we bump things up slightly further |
| // to correct for that. |
| { |
| name: "otbn_dmem_err" |
| uvm_test_seq: "otbn_dmem_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 15 |
| } |
| |
| // This test sets the lc_escalate_en_i and lc_rma_req_i signals somewhere in |
| // the middle of an operation and makes sure that we see an alert. There's |
| // not much interesting that can happen here, so a small number of seeds should |
| // suffice. |
| { |
| name: "otbn_escalate" |
| uvm_test_seq: "otbn_escalate_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 60 |
| } |
| |
| { |
| name: "otbn_alu_bignum_mod_err" |
| uvm_test_seq: "otbn_alu_bignum_mod_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| |
| { |
| name: "otbn_controller_ispr_rdata_err" |
| uvm_test_seq: "otbn_controller_ispr_rdata_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| |
| { |
| name: "otbn_mac_bignum_acc_err" |
| uvm_test_seq: "otbn_mac_bignum_acc_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| |
| { |
| name: "otbn_rf_bignum_intg_err" |
| uvm_test_seq: "otbn_rf_bignum_intg_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 10 |
| } |
| |
| { |
| name: "otbn_rf_base_intg_err" |
| uvm_test_seq: "otbn_rf_base_intg_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 10 |
| } |
| |
| // This test runs several sequences back-to-back. Unlike otbn_multi, these |
| // sequences can include imem or dmem error sequences. We shouldn't need |
| // many seeds here because each test runs several operations. |
| { |
| name: "otbn_stress_all" |
| uvm_test_seq: "otbn_stress_all_vseq" |
| en_run_modes: ["build_otbn_rig_binaries_mode"] |
| reseed: 10 |
| } |
| |
| // A combination of otbn_stress_all and otbn_reset. |
| { |
| name: "otbn_stress_all_with_rand_reset" |
| en_run_modes: ["build_otbn_rig_binaries_mode"] |
| reseed: 10 |
| } |
| { |
| name: "otbn_zero_state_err_urnd" |
| uvm_test_seq: "otbn_zero_state_err_urnd_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| { |
| name: "otbn_illegal_mem_acc" |
| uvm_test_seq: "otbn_illegal_mem_acc_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| { |
| name: "otbn_sw_errs_fatal_chk" |
| uvm_test_seq: "otbn_sw_errs_fatal_chk_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 10 |
| } |
| { |
| name: "otbn_pc_ctrl_flow_redun" |
| uvm_test_seq: "otbn_pc_ctrl_flow_redun_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| { |
| name: "otbn_rnd_sec_cm" |
| uvm_test_seq: "otbn_rnd_sec_cm_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| { |
| name: "otbn_ctrl_redun" |
| uvm_test_seq: "otbn_ctrl_redun_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 12 |
| } |
| { |
| name: "otbn_sec_wipe_err" |
| uvm_test_seq: "otbn_sec_wipe_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 7 |
| } |
| { |
| name: "otbn_urnd_err" |
| uvm_test_seq: "otbn_urnd_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 2 |
| } |
| { |
| name: "otbn_sw_no_acc" |
| uvm_test_seq: "otbn_sw_no_acc_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| { |
| name: "otbn_mem_gnt_acc_err" |
| uvm_test_seq: "otbn_mem_gnt_acc_err_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 2 |
| } |
| { |
| name: "otbn_stack_addr_integ_chk" |
| uvm_test_seq: "otbn_stack_addr_integ_chk_vseq" |
| en_run_modes: ["build_otbn_rig_binary_mode"] |
| reseed: 5 |
| } |
| ] |
| |
| // List of regressions. |
| regressions: [ |
| { |
| name: smoke |
| tests: ["otbn_smoke"] |
| } |
| |
| { |
| name: "core" |
| tests: [ |
| "otbn_smoke", "otbn_single", "otbn_multi", "otbn_reset", |
| "otbn_multi_err", "otbn_imem_err", "otbn_dmem_err", |
| "otbn_stress_all", "otbn_escalate", "otbn_illegal_mem_acc", |
| "otbn_zero_state_err_urnd", "otbn_sw_errs_fatal_chk", |
| "otbn_rnd_sec_cm", "otbn_mac_bignum_acc_err", "otbn_rf_base_intg_err", |
| "otbn_controller_ispr_rdata_err", "otbn_alu_bignum_mod_err" |
| ] |
| |
| } |
| |
| { |
| name: "ci" |
| tests: [ |
| # V1 |
| "otbn_smoke", "otbn_single", "otbn_csr_hw_reset", "otbn_csr_rw", |
| "otbn_csr_bit_bash", "otbn_csr_aliasing", |
| "otbn_csr_mem_rw_with_rand_reset", |
| "otbn_mem_partial_access", |
| # V1 but known broken |
| # "otbn_mem_walk", |
| # V2 |
| "otbn_reset", "otbn_multi", "otbn_stress_all", |
| "otbn_zero_state_err_urnd", "otbn_sw_errs_fatal_chk", "otbn_alert_test", |
| "otbn_intr_test", "otbn_tl_errors", |
| "otbn_same_csr_outstanding" |
| # V2 but known broken |
| # "otbn_multi_err", "otbn_escalate", |
| # V2S |
| "otbn_imem_err", "otbn_dmem_err", "otbn_illegal_mem_acc", |
| "otbn_tl_intg_err", "otbn_sec_cm", "otbn_pc_ctrl_flow_redun", |
| "otbn_rnd_sec_cm", "otbn_alu_bignum_mod_err", |
| "otbn_controller_ispr_rdata_err", "otbn_mac_bignum_acc_err", |
| "otbn_rf_base_intg_err", |
| "otbn_sec_wipe_err", "otbn_urnd_err", |
| # V2S but known broken |
| # "otbn_passthru_mem_tl_intg_err", |
| # V3 thus not yet active |
| # "otbn_stress_all_with_rand_reset", |
| ] |
| } |
| ] |
| } |