diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 0cc1850..139ef23 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -118,9 +118,9 @@
     },
 
     { struct: "pwr_flash",
-      type: "req_rsp",
+      type: "uni",
       name: "pwrmgr",
-      act:  "rsp",
+      act:  "req",
       package: "pwrmgr_pkg"
     },
 
@@ -262,6 +262,25 @@
   regwidth: "32",
   registers: {
     core: [
+      { name: "INIT",
+        desc: "Controller init register",
+        swaccess: "rw1s",
+        hwaccess: "hro",
+        fields: [
+          { bits: "0",
+            name: "VAL",
+            desc: '''
+              Initializes the flash controller.
+              During the initialization process, the flash controller reads out the root seeds
+              before allowing other usage of the flash controller.
+              '''
+            resval: "0"
+            tags: [// Dont init flash, it has several side effects on the status bits
+                   "excl:CsrAllTests:CsrExclWrite"],
+          },
+        ]
+      },
+
       { name: "CTRL_REGWEN",
         swaccess: "ro",
         hwaccess: "hwo",
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
index a626265..2439162 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -125,9 +125,9 @@
     },
 
     { struct: "pwr_flash",
-      type: "req_rsp",
+      type: "uni",
       name: "pwrmgr",
-      act:  "rsp",
+      act:  "req",
       package: "pwrmgr_pkg"
     },
 
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index 308ddc3..44440b4 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -47,7 +47,7 @@
   input        lc_ctrl_pkg::lc_tx_t rma_req_i,
   input        lc_ctrl_pkg::lc_flash_rma_seed_t rma_seed_i,
   output       lc_ctrl_pkg::lc_tx_t rma_ack_o,
-  output       pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
+  output       pwrmgr_pkg::pwr_flash_t pwrmgr_o,
   output       keymgr_flash_t keymgr_o,
 
   // IOs
diff --git a/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv b/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv
index 17bc120..c28d129 100644
--- a/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv
+++ b/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv
@@ -32,8 +32,7 @@
   input        lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i,
   input        lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i,
   input        lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i,
-  output       pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
-  input        pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
+  output       pwrmgr_pkg::pwr_flash_t pwrmgr_o,
   input        lc_ctrl_pkg::lc_tx_t rma_req_i,
   input        lc_ctrl_pkg::lc_flash_rma_seed_t rma_seed_i,
   output       lc_ctrl_pkg::lc_tx_t rma_ack_o,
@@ -89,7 +88,6 @@
     .rma_req_i         (rma_req_i),
     .rma_seed_i        (rma_seed_i),
     .rma_ack_o         (rma_ack_o),
-    .pwrmgr_i          (pwrmgr_i),
     .pwrmgr_o          (pwrmgr_o),
 
     .clk_i             (clk_i),
diff --git a/hw/ip/flash_ctrl/dv/tb/tb.sv b/hw/ip/flash_ctrl/dv/tb/tb.sv
index 8884412..a4d0101 100644
--- a/hw/ip/flash_ctrl/dv/tb/tb.sv
+++ b/hw/ip/flash_ctrl/dv/tb/tb.sv
@@ -59,8 +59,7 @@
     .lc_iso_part_sw_wr_en_i     (lc_ctrl_pkg::On),
     .lc_seed_hw_rd_en_i         (lc_ctrl_pkg::On),
     .lc_nvm_debug_en_i          (lc_ctrl_pkg::Off),
-    .pwrmgr_o                   (pwrmgr_pkg::PWR_FLASH_RSP_DEFAULT),
-    .pwrmgr_i                   (pwrmgr_pkg::PWR_FLASH_REQ_DEFAULT),
+    .pwrmgr_o                   (pwrmgr_pkg::PWR_FLASH_DEFAULT),
     .rma_req_i                  (lc_ctrl_pkg::Off),
     .rma_seed_i                 ('0),
     .rma_ack_o                  (),
diff --git a/hw/ip/flash_ctrl/lint/flash_ctrl.vlt b/hw/ip/flash_ctrl/lint/flash_ctrl.vlt
index 1795937..f136925 100644
--- a/hw/ip/flash_ctrl/lint/flash_ctrl.vlt
+++ b/hw/ip/flash_ctrl/lint/flash_ctrl.vlt
@@ -17,3 +17,11 @@
 // the code too (which is at .../rtl/autogen/flash_ctrl.sv)
 lint_off -rule WIDTH -file "*/rtl/*flash_ctrl.sv" -match "Operator ASSIGNW expects 10 bits*MUL generates 32 bits."
 
+// The following are int parameter assignments into variables
+// While the variables themselves are technically not large enough to accommodate a 32b integer, synthsizers
+// are smart enough to do the right thing
+lint_off -rule WIDTH -file "*flash_ctrl_lcmgr.sv" -match "Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'seed_cnt_q' generates 2 bits."
+lint_off -rule WIDTH -file "*flash_ctrl_lcmgr.sv" -match "Operator ADD expects 32 bits on the LHS, but LHS's VARREF 'word_cnt' generates 10 bits."
+lint_off -rule WIDTH -file "*flash_ctrl_lcmgr.sv" -match "Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS's ADD generates 32 bits."
+lint_off -rule WIDTH -file "*flash_ctrl_lcmgr.sv" -match "Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits."
+lint_off -rule WIDTH -file "*flash_ctrl_lcmgr.sv" -match "Operator LT expects 32 bits on the LHS, but LHS's VARREF 'word_cnt' generates 10 bits."
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 2e6d474..94cbd51 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -47,8 +47,7 @@
   input        lc_ctrl_pkg::lc_tx_t rma_req_i,
   input        lc_ctrl_pkg::lc_flash_rma_seed_t rma_seed_i,
   output       lc_ctrl_pkg::lc_tx_t rma_ack_o,
-  input        pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
-  output       pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
+  output       pwrmgr_pkg::pwr_flash_t pwrmgr_o,
   output       keymgr_flash_t keymgr_o,
 
   // IOs
@@ -382,8 +381,7 @@
     .clk_otp_i,
     .rst_otp_ni,
 
-    .init_i(pwrmgr_i.flash_init),
-    .init_done_o(pwrmgr_o.flash_done),
+    .init_i(reg2hw.init),
     .provision_en_i(lc_seed_hw_rd_en == lc_ctrl_pkg::On),
 
     // interface to ctrl arb control ports
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
index 1b7eb76..6772147 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
@@ -120,10 +120,10 @@
     reg_steer = 2;       // Default set to register
 
     // TODO: Can below codes be unique case () inside ?
-    if (tl_i.a_address[AW-1:0] >= 392 && tl_i.a_address[AW-1:0] < 396) begin
+    if (tl_i.a_address[AW-1:0] >= 396 && tl_i.a_address[AW-1:0] < 400) begin
       reg_steer = 0;
     end
-    if (tl_i.a_address[AW-1:0] >= 396 && tl_i.a_address[AW-1:0] < 400) begin
+    if (tl_i.a_address[AW-1:0] >= 400 && tl_i.a_address[AW-1:0] < 404) begin
       reg_steer = 1;
     end
     if (intg_err) begin
@@ -213,6 +213,9 @@
   logic alert_test_recov_ecc_err_we;
   logic alert_test_fatal_intg_err_wd;
   logic alert_test_fatal_intg_err_we;
+  logic init_qs;
+  logic init_wd;
+  logic init_we;
   logic ctrl_regwen_qs;
   logic ctrl_regwen_re;
   logic control_start_qs;
@@ -1690,6 +1693,33 @@
   );
 
 
+  // R[init]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1S"),
+    .RESVAL  (1'h0)
+  ) u_init (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (init_we),
+    .wd     (init_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.init.q ),
+
+    // to register interface (read)
+    .qs     (init_qs)
+  );
+
+
   // R[ctrl_regwen]: V(True)
 
   prim_subreg_ext #(
@@ -10820,107 +10850,108 @@
 
 
 
-  logic [97:0] addr_hit;
+  logic [98:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
     addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
     addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
     addr_hit[ 3] = (reg_addr == FLASH_CTRL_ALERT_TEST_OFFSET);
-    addr_hit[ 4] = (reg_addr == FLASH_CTRL_CTRL_REGWEN_OFFSET);
-    addr_hit[ 5] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
-    addr_hit[ 6] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
-    addr_hit[ 7] = (reg_addr == FLASH_CTRL_PROG_TYPE_EN_OFFSET);
-    addr_hit[ 8] = (reg_addr == FLASH_CTRL_ERASE_SUSPEND_OFFSET);
-    addr_hit[ 9] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
-    addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
-    addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
-    addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
-    addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
-    addr_hit[14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
-    addr_hit[15] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
-    addr_hit[16] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
-    addr_hit[17] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
-    addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
-    addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
-    addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
-    addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
-    addr_hit[22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
-    addr_hit[23] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
-    addr_hit[24] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
-    addr_hit[25] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
-    addr_hit[26] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
-    addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
-    addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
-    addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
-    addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET);
-    addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET);
-    addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET);
-    addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET);
-    addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET);
-    addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET);
-    addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
-    addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
-    addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
-    addr_hit[39] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
-    addr_hit[40] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET);
-    addr_hit[41] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET);
-    addr_hit[42] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET);
-    addr_hit[43] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET);
-    addr_hit[44] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET);
-    addr_hit[45] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET);
-    addr_hit[46] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET);
-    addr_hit[47] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET);
-    addr_hit[48] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET);
-    addr_hit[49] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET);
-    addr_hit[50] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET);
-    addr_hit[51] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET);
-    addr_hit[52] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
-    addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
-    addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
-    addr_hit[55] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
-    addr_hit[56] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET);
-    addr_hit[57] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET);
-    addr_hit[58] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET);
-    addr_hit[59] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET);
-    addr_hit[60] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET);
-    addr_hit[61] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET);
-    addr_hit[62] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
-    addr_hit[63] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
-    addr_hit[64] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
-    addr_hit[65] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
-    addr_hit[66] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET);
-    addr_hit[67] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET);
-    addr_hit[68] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET);
-    addr_hit[69] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET);
-    addr_hit[70] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET);
-    addr_hit[71] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET);
-    addr_hit[72] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET);
-    addr_hit[73] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET);
-    addr_hit[74] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET);
-    addr_hit[75] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET);
-    addr_hit[76] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET);
-    addr_hit[77] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET);
-    addr_hit[78] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
-    addr_hit[79] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
-    addr_hit[80] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
-    addr_hit[81] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
-    addr_hit[82] = (reg_addr == FLASH_CTRL_ERR_CODE_INTR_EN_OFFSET);
-    addr_hit[83] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
-    addr_hit[84] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
-    addr_hit[85] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
-    addr_hit[86] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
-    addr_hit[87] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
-    addr_hit[88] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_CNT_OFFSET);
-    addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_ADDR_0_OFFSET);
-    addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_ADDR_1_OFFSET);
-    addr_hit[91] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET);
-    addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_OFFSET);
-    addr_hit[93] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
-    addr_hit[94] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
-    addr_hit[95] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
-    addr_hit[96] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
-    addr_hit[97] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+    addr_hit[ 4] = (reg_addr == FLASH_CTRL_INIT_OFFSET);
+    addr_hit[ 5] = (reg_addr == FLASH_CTRL_CTRL_REGWEN_OFFSET);
+    addr_hit[ 6] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
+    addr_hit[ 7] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
+    addr_hit[ 8] = (reg_addr == FLASH_CTRL_PROG_TYPE_EN_OFFSET);
+    addr_hit[ 9] = (reg_addr == FLASH_CTRL_ERASE_SUSPEND_OFFSET);
+    addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
+    addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
+    addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
+    addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
+    addr_hit[14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
+    addr_hit[15] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
+    addr_hit[16] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
+    addr_hit[17] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
+    addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
+    addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
+    addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
+    addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
+    addr_hit[22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
+    addr_hit[23] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
+    addr_hit[24] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
+    addr_hit[25] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
+    addr_hit[26] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
+    addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
+    addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
+    addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
+    addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
+    addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET);
+    addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET);
+    addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET);
+    addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET);
+    addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET);
+    addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET);
+    addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
+    addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
+    addr_hit[39] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
+    addr_hit[40] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
+    addr_hit[41] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET);
+    addr_hit[42] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET);
+    addr_hit[43] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET);
+    addr_hit[44] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET);
+    addr_hit[45] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET);
+    addr_hit[46] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET);
+    addr_hit[47] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET);
+    addr_hit[48] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET);
+    addr_hit[49] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET);
+    addr_hit[50] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET);
+    addr_hit[51] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET);
+    addr_hit[52] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET);
+    addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
+    addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
+    addr_hit[55] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
+    addr_hit[56] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
+    addr_hit[57] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET);
+    addr_hit[58] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET);
+    addr_hit[59] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET);
+    addr_hit[60] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET);
+    addr_hit[61] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET);
+    addr_hit[62] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET);
+    addr_hit[63] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
+    addr_hit[64] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
+    addr_hit[65] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
+    addr_hit[66] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
+    addr_hit[67] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET);
+    addr_hit[68] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET);
+    addr_hit[69] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET);
+    addr_hit[70] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET);
+    addr_hit[71] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET);
+    addr_hit[72] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET);
+    addr_hit[73] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET);
+    addr_hit[74] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET);
+    addr_hit[75] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET);
+    addr_hit[76] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET);
+    addr_hit[77] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET);
+    addr_hit[78] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET);
+    addr_hit[79] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
+    addr_hit[80] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
+    addr_hit[81] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
+    addr_hit[82] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
+    addr_hit[83] = (reg_addr == FLASH_CTRL_ERR_CODE_INTR_EN_OFFSET);
+    addr_hit[84] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
+    addr_hit[85] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
+    addr_hit[86] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
+    addr_hit[87] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
+    addr_hit[88] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
+    addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_CNT_OFFSET);
+    addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_ADDR_0_OFFSET);
+    addr_hit[91] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_ADDR_1_OFFSET);
+    addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET);
+    addr_hit[93] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_OFFSET);
+    addr_hit[94] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
+    addr_hit[95] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+    addr_hit[96] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+    addr_hit[97] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+    addr_hit[98] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -11026,6 +11057,7 @@
     if (addr_hit[95] && reg_we && (FLASH_CTRL_CORE_PERMIT[95] != (FLASH_CTRL_CORE_PERMIT[95] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[96] && reg_we && (FLASH_CTRL_CORE_PERMIT[96] != (FLASH_CTRL_CORE_PERMIT[96] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[97] && reg_we && (FLASH_CTRL_CORE_PERMIT[97] != (FLASH_CTRL_CORE_PERMIT[97] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[98] && reg_we && (FLASH_CTRL_CORE_PERMIT[98] != (FLASH_CTRL_CORE_PERMIT[98] & reg_be))) wr_err = 1'b1 ;
   end
 
   assign intr_state_prog_empty_we = addr_hit[0] & reg_we & !reg_error;
@@ -11094,996 +11126,999 @@
   assign alert_test_fatal_intg_err_we = addr_hit[3] & reg_we & !reg_error;
   assign alert_test_fatal_intg_err_wd = reg_wdata[3];
 
-  assign ctrl_regwen_re = addr_hit[4] & reg_re & !reg_error;
+  assign init_we = addr_hit[4] & reg_we & !reg_error;
+  assign init_wd = reg_wdata[0];
 
-  assign control_start_we = addr_hit[5] & reg_we & !reg_error;
+  assign ctrl_regwen_re = addr_hit[5] & reg_re & !reg_error;
+
+  assign control_start_we = addr_hit[6] & reg_we & !reg_error;
   assign control_start_wd = reg_wdata[0];
 
-  assign control_op_we = addr_hit[5] & reg_we & !reg_error;
+  assign control_op_we = addr_hit[6] & reg_we & !reg_error;
   assign control_op_wd = reg_wdata[5:4];
 
-  assign control_prog_sel_we = addr_hit[5] & reg_we & !reg_error;
+  assign control_prog_sel_we = addr_hit[6] & reg_we & !reg_error;
   assign control_prog_sel_wd = reg_wdata[6];
 
-  assign control_erase_sel_we = addr_hit[5] & reg_we & !reg_error;
+  assign control_erase_sel_we = addr_hit[6] & reg_we & !reg_error;
   assign control_erase_sel_wd = reg_wdata[7];
 
-  assign control_partition_sel_we = addr_hit[5] & reg_we & !reg_error;
+  assign control_partition_sel_we = addr_hit[6] & reg_we & !reg_error;
   assign control_partition_sel_wd = reg_wdata[8];
 
-  assign control_info_sel_we = addr_hit[5] & reg_we & !reg_error;
+  assign control_info_sel_we = addr_hit[6] & reg_we & !reg_error;
   assign control_info_sel_wd = reg_wdata[10:9];
 
-  assign control_num_we = addr_hit[5] & reg_we & !reg_error;
+  assign control_num_we = addr_hit[6] & reg_we & !reg_error;
   assign control_num_wd = reg_wdata[27:16];
 
-  assign addr_we = addr_hit[6] & reg_we & !reg_error;
+  assign addr_we = addr_hit[7] & reg_we & !reg_error;
   assign addr_wd = reg_wdata[31:0];
 
-  assign prog_type_en_normal_we = addr_hit[7] & reg_we & !reg_error;
+  assign prog_type_en_normal_we = addr_hit[8] & reg_we & !reg_error;
   assign prog_type_en_normal_wd = reg_wdata[0];
 
-  assign prog_type_en_repair_we = addr_hit[7] & reg_we & !reg_error;
+  assign prog_type_en_repair_we = addr_hit[8] & reg_we & !reg_error;
   assign prog_type_en_repair_wd = reg_wdata[1];
 
-  assign erase_suspend_we = addr_hit[8] & reg_we & !reg_error;
+  assign erase_suspend_we = addr_hit[9] & reg_we & !reg_error;
   assign erase_suspend_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_0_we = addr_hit[9] & reg_we & !reg_error;
+  assign region_cfg_regwen_0_we = addr_hit[10] & reg_we & !reg_error;
   assign region_cfg_regwen_0_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_1_we = addr_hit[10] & reg_we & !reg_error;
+  assign region_cfg_regwen_1_we = addr_hit[11] & reg_we & !reg_error;
   assign region_cfg_regwen_1_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_2_we = addr_hit[11] & reg_we & !reg_error;
+  assign region_cfg_regwen_2_we = addr_hit[12] & reg_we & !reg_error;
   assign region_cfg_regwen_2_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_3_we = addr_hit[12] & reg_we & !reg_error;
+  assign region_cfg_regwen_3_we = addr_hit[13] & reg_we & !reg_error;
   assign region_cfg_regwen_3_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_4_we = addr_hit[13] & reg_we & !reg_error;
+  assign region_cfg_regwen_4_we = addr_hit[14] & reg_we & !reg_error;
   assign region_cfg_regwen_4_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_5_we = addr_hit[14] & reg_we & !reg_error;
+  assign region_cfg_regwen_5_we = addr_hit[15] & reg_we & !reg_error;
   assign region_cfg_regwen_5_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_6_we = addr_hit[15] & reg_we & !reg_error;
+  assign region_cfg_regwen_6_we = addr_hit[16] & reg_we & !reg_error;
   assign region_cfg_regwen_6_wd = reg_wdata[0];
 
-  assign region_cfg_regwen_7_we = addr_hit[16] & reg_we & !reg_error;
+  assign region_cfg_regwen_7_we = addr_hit[17] & reg_we & !reg_error;
   assign region_cfg_regwen_7_wd = reg_wdata[0];
 
-  assign mp_region_cfg_0_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_en_0_wd = reg_wdata[0];
 
-  assign mp_region_cfg_0_rd_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_rd_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_rd_en_0_wd = reg_wdata[1];
 
-  assign mp_region_cfg_0_prog_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_prog_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_prog_en_0_wd = reg_wdata[2];
 
-  assign mp_region_cfg_0_erase_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_erase_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_erase_en_0_wd = reg_wdata[3];
 
-  assign mp_region_cfg_0_scramble_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_scramble_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[4];
 
-  assign mp_region_cfg_0_ecc_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_ecc_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[5];
 
-  assign mp_region_cfg_0_he_en_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_he_en_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_he_en_0_wd = reg_wdata[6];
 
-  assign mp_region_cfg_0_base_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_base_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_base_0_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_0_size_0_we = addr_hit[17] & reg_we & !reg_error;
+  assign mp_region_cfg_0_size_0_we = addr_hit[18] & reg_we & !reg_error;
   assign mp_region_cfg_0_size_0_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_1_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_en_1_wd = reg_wdata[0];
 
-  assign mp_region_cfg_1_rd_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_rd_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_rd_en_1_wd = reg_wdata[1];
 
-  assign mp_region_cfg_1_prog_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_prog_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_prog_en_1_wd = reg_wdata[2];
 
-  assign mp_region_cfg_1_erase_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_erase_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_erase_en_1_wd = reg_wdata[3];
 
-  assign mp_region_cfg_1_scramble_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_scramble_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[4];
 
-  assign mp_region_cfg_1_ecc_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_ecc_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[5];
 
-  assign mp_region_cfg_1_he_en_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_he_en_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_he_en_1_wd = reg_wdata[6];
 
-  assign mp_region_cfg_1_base_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_base_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_base_1_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_1_size_1_we = addr_hit[18] & reg_we & !reg_error;
+  assign mp_region_cfg_1_size_1_we = addr_hit[19] & reg_we & !reg_error;
   assign mp_region_cfg_1_size_1_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_2_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_en_2_wd = reg_wdata[0];
 
-  assign mp_region_cfg_2_rd_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_rd_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_rd_en_2_wd = reg_wdata[1];
 
-  assign mp_region_cfg_2_prog_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_prog_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_prog_en_2_wd = reg_wdata[2];
 
-  assign mp_region_cfg_2_erase_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_erase_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_erase_en_2_wd = reg_wdata[3];
 
-  assign mp_region_cfg_2_scramble_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_scramble_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[4];
 
-  assign mp_region_cfg_2_ecc_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_ecc_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[5];
 
-  assign mp_region_cfg_2_he_en_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_he_en_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_he_en_2_wd = reg_wdata[6];
 
-  assign mp_region_cfg_2_base_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_base_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_base_2_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_2_size_2_we = addr_hit[19] & reg_we & !reg_error;
+  assign mp_region_cfg_2_size_2_we = addr_hit[20] & reg_we & !reg_error;
   assign mp_region_cfg_2_size_2_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_3_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_en_3_wd = reg_wdata[0];
 
-  assign mp_region_cfg_3_rd_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_rd_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_rd_en_3_wd = reg_wdata[1];
 
-  assign mp_region_cfg_3_prog_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_prog_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_prog_en_3_wd = reg_wdata[2];
 
-  assign mp_region_cfg_3_erase_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_erase_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_erase_en_3_wd = reg_wdata[3];
 
-  assign mp_region_cfg_3_scramble_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_scramble_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[4];
 
-  assign mp_region_cfg_3_ecc_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_ecc_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[5];
 
-  assign mp_region_cfg_3_he_en_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_he_en_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_he_en_3_wd = reg_wdata[6];
 
-  assign mp_region_cfg_3_base_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_base_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_base_3_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_3_size_3_we = addr_hit[20] & reg_we & !reg_error;
+  assign mp_region_cfg_3_size_3_we = addr_hit[21] & reg_we & !reg_error;
   assign mp_region_cfg_3_size_3_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_4_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_en_4_wd = reg_wdata[0];
 
-  assign mp_region_cfg_4_rd_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_rd_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_rd_en_4_wd = reg_wdata[1];
 
-  assign mp_region_cfg_4_prog_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_prog_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_prog_en_4_wd = reg_wdata[2];
 
-  assign mp_region_cfg_4_erase_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_erase_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_erase_en_4_wd = reg_wdata[3];
 
-  assign mp_region_cfg_4_scramble_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_scramble_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[4];
 
-  assign mp_region_cfg_4_ecc_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_ecc_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[5];
 
-  assign mp_region_cfg_4_he_en_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_he_en_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_he_en_4_wd = reg_wdata[6];
 
-  assign mp_region_cfg_4_base_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_base_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_base_4_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_4_size_4_we = addr_hit[21] & reg_we & !reg_error;
+  assign mp_region_cfg_4_size_4_we = addr_hit[22] & reg_we & !reg_error;
   assign mp_region_cfg_4_size_4_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_5_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_en_5_wd = reg_wdata[0];
 
-  assign mp_region_cfg_5_rd_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_rd_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_rd_en_5_wd = reg_wdata[1];
 
-  assign mp_region_cfg_5_prog_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_prog_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_prog_en_5_wd = reg_wdata[2];
 
-  assign mp_region_cfg_5_erase_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_erase_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_erase_en_5_wd = reg_wdata[3];
 
-  assign mp_region_cfg_5_scramble_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_scramble_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[4];
 
-  assign mp_region_cfg_5_ecc_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_ecc_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[5];
 
-  assign mp_region_cfg_5_he_en_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_he_en_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_he_en_5_wd = reg_wdata[6];
 
-  assign mp_region_cfg_5_base_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_base_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_base_5_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_5_size_5_we = addr_hit[22] & reg_we & !reg_error;
+  assign mp_region_cfg_5_size_5_we = addr_hit[23] & reg_we & !reg_error;
   assign mp_region_cfg_5_size_5_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_6_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_en_6_wd = reg_wdata[0];
 
-  assign mp_region_cfg_6_rd_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_rd_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_rd_en_6_wd = reg_wdata[1];
 
-  assign mp_region_cfg_6_prog_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_prog_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_prog_en_6_wd = reg_wdata[2];
 
-  assign mp_region_cfg_6_erase_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_erase_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_erase_en_6_wd = reg_wdata[3];
 
-  assign mp_region_cfg_6_scramble_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_scramble_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[4];
 
-  assign mp_region_cfg_6_ecc_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_ecc_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[5];
 
-  assign mp_region_cfg_6_he_en_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_he_en_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_he_en_6_wd = reg_wdata[6];
 
-  assign mp_region_cfg_6_base_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_base_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_base_6_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_6_size_6_we = addr_hit[23] & reg_we & !reg_error;
+  assign mp_region_cfg_6_size_6_we = addr_hit[24] & reg_we & !reg_error;
   assign mp_region_cfg_6_size_6_wd = reg_wdata[26:17];
 
-  assign mp_region_cfg_7_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_en_7_wd = reg_wdata[0];
 
-  assign mp_region_cfg_7_rd_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_rd_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_rd_en_7_wd = reg_wdata[1];
 
-  assign mp_region_cfg_7_prog_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_prog_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_prog_en_7_wd = reg_wdata[2];
 
-  assign mp_region_cfg_7_erase_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_erase_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_erase_en_7_wd = reg_wdata[3];
 
-  assign mp_region_cfg_7_scramble_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_scramble_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[4];
 
-  assign mp_region_cfg_7_ecc_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_ecc_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[5];
 
-  assign mp_region_cfg_7_he_en_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_he_en_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_he_en_7_wd = reg_wdata[6];
 
-  assign mp_region_cfg_7_base_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_base_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_base_7_wd = reg_wdata[16:8];
 
-  assign mp_region_cfg_7_size_7_we = addr_hit[24] & reg_we & !reg_error;
+  assign mp_region_cfg_7_size_7_we = addr_hit[25] & reg_we & !reg_error;
   assign mp_region_cfg_7_size_7_wd = reg_wdata[26:17];
 
-  assign default_region_rd_en_we = addr_hit[25] & reg_we & !reg_error;
+  assign default_region_rd_en_we = addr_hit[26] & reg_we & !reg_error;
   assign default_region_rd_en_wd = reg_wdata[0];
 
-  assign default_region_prog_en_we = addr_hit[25] & reg_we & !reg_error;
+  assign default_region_prog_en_we = addr_hit[26] & reg_we & !reg_error;
   assign default_region_prog_en_wd = reg_wdata[1];
 
-  assign default_region_erase_en_we = addr_hit[25] & reg_we & !reg_error;
+  assign default_region_erase_en_we = addr_hit[26] & reg_we & !reg_error;
   assign default_region_erase_en_wd = reg_wdata[2];
 
-  assign default_region_scramble_en_we = addr_hit[25] & reg_we & !reg_error;
+  assign default_region_scramble_en_we = addr_hit[26] & reg_we & !reg_error;
   assign default_region_scramble_en_wd = reg_wdata[3];
 
-  assign default_region_ecc_en_we = addr_hit[25] & reg_we & !reg_error;
+  assign default_region_ecc_en_we = addr_hit[26] & reg_we & !reg_error;
   assign default_region_ecc_en_wd = reg_wdata[4];
 
-  assign default_region_he_en_we = addr_hit[25] & reg_we & !reg_error;
+  assign default_region_he_en_we = addr_hit[26] & reg_we & !reg_error;
   assign default_region_he_en_wd = reg_wdata[5];
 
-  assign bank0_info0_regwen_0_we = addr_hit[26] & reg_we & !reg_error;
+  assign bank0_info0_regwen_0_we = addr_hit[27] & reg_we & !reg_error;
   assign bank0_info0_regwen_0_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_1_we = addr_hit[27] & reg_we & !reg_error;
+  assign bank0_info0_regwen_1_we = addr_hit[28] & reg_we & !reg_error;
   assign bank0_info0_regwen_1_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_2_we = addr_hit[28] & reg_we & !reg_error;
+  assign bank0_info0_regwen_2_we = addr_hit[29] & reg_we & !reg_error;
   assign bank0_info0_regwen_2_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_3_we = addr_hit[29] & reg_we & !reg_error;
+  assign bank0_info0_regwen_3_we = addr_hit[30] & reg_we & !reg_error;
   assign bank0_info0_regwen_3_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_4_we = addr_hit[30] & reg_we & !reg_error;
+  assign bank0_info0_regwen_4_we = addr_hit[31] & reg_we & !reg_error;
   assign bank0_info0_regwen_4_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_5_we = addr_hit[31] & reg_we & !reg_error;
+  assign bank0_info0_regwen_5_we = addr_hit[32] & reg_we & !reg_error;
   assign bank0_info0_regwen_5_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_6_we = addr_hit[32] & reg_we & !reg_error;
+  assign bank0_info0_regwen_6_we = addr_hit[33] & reg_we & !reg_error;
   assign bank0_info0_regwen_6_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_7_we = addr_hit[33] & reg_we & !reg_error;
+  assign bank0_info0_regwen_7_we = addr_hit[34] & reg_we & !reg_error;
   assign bank0_info0_regwen_7_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_8_we = addr_hit[34] & reg_we & !reg_error;
+  assign bank0_info0_regwen_8_we = addr_hit[35] & reg_we & !reg_error;
   assign bank0_info0_regwen_8_wd = reg_wdata[0];
 
-  assign bank0_info0_regwen_9_we = addr_hit[35] & reg_we & !reg_error;
+  assign bank0_info0_regwen_9_we = addr_hit[36] & reg_we & !reg_error;
   assign bank0_info0_regwen_9_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_0_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_en_0_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[36] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[37] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_1_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[37] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[38] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_2_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[38] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[39] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_3_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[39] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[40] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_4_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_en_4_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_4_rd_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_rd_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_rd_en_4_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_4_prog_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_prog_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_prog_en_4_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_4_erase_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_erase_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_erase_en_4_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_4_scramble_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_scramble_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_scramble_en_4_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_4_ecc_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_ecc_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_ecc_en_4_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_4_he_en_4_we = addr_hit[40] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_4_he_en_4_we = addr_hit[41] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_4_he_en_4_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_5_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_en_5_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_5_rd_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_rd_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_rd_en_5_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_5_prog_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_prog_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_prog_en_5_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_5_erase_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_erase_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_erase_en_5_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_5_scramble_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_scramble_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_scramble_en_5_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_5_ecc_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_ecc_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_ecc_en_5_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_5_he_en_5_we = addr_hit[41] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_5_he_en_5_we = addr_hit[42] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_5_he_en_5_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_6_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_en_6_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_6_rd_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_rd_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_rd_en_6_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_6_prog_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_prog_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_prog_en_6_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_6_erase_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_erase_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_erase_en_6_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_6_scramble_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_scramble_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_scramble_en_6_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_6_ecc_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_ecc_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_ecc_en_6_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_6_he_en_6_we = addr_hit[42] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_6_he_en_6_we = addr_hit[43] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_6_he_en_6_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_7_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_en_7_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_7_rd_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_rd_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_rd_en_7_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_7_prog_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_prog_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_prog_en_7_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_7_erase_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_erase_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_erase_en_7_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_7_scramble_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_scramble_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_scramble_en_7_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_7_ecc_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_ecc_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_ecc_en_7_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_7_he_en_7_we = addr_hit[43] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_7_he_en_7_we = addr_hit[44] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_7_he_en_7_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_8_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_en_8_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_8_rd_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_rd_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_rd_en_8_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_8_prog_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_prog_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_prog_en_8_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_8_erase_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_erase_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_erase_en_8_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_8_scramble_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_scramble_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_scramble_en_8_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_8_ecc_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_ecc_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_ecc_en_8_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_8_he_en_8_we = addr_hit[44] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_8_he_en_8_we = addr_hit[45] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_8_he_en_8_wd = reg_wdata[6];
 
-  assign bank0_info0_page_cfg_9_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_en_9_wd = reg_wdata[0];
 
-  assign bank0_info0_page_cfg_9_rd_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_rd_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_rd_en_9_wd = reg_wdata[1];
 
-  assign bank0_info0_page_cfg_9_prog_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_prog_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_prog_en_9_wd = reg_wdata[2];
 
-  assign bank0_info0_page_cfg_9_erase_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_erase_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_erase_en_9_wd = reg_wdata[3];
 
-  assign bank0_info0_page_cfg_9_scramble_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_scramble_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_scramble_en_9_wd = reg_wdata[4];
 
-  assign bank0_info0_page_cfg_9_ecc_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_ecc_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_ecc_en_9_wd = reg_wdata[5];
 
-  assign bank0_info0_page_cfg_9_he_en_9_we = addr_hit[45] & reg_we & !reg_error;
+  assign bank0_info0_page_cfg_9_he_en_9_we = addr_hit[46] & reg_we & !reg_error;
   assign bank0_info0_page_cfg_9_he_en_9_wd = reg_wdata[6];
 
-  assign bank0_info1_regwen_we = addr_hit[46] & reg_we & !reg_error;
+  assign bank0_info1_regwen_we = addr_hit[47] & reg_we & !reg_error;
   assign bank0_info1_regwen_wd = reg_wdata[0];
 
-  assign bank0_info1_page_cfg_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_en_0_wd = reg_wdata[0];
 
-  assign bank0_info1_page_cfg_rd_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_rd_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_rd_en_0_wd = reg_wdata[1];
 
-  assign bank0_info1_page_cfg_prog_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_prog_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_prog_en_0_wd = reg_wdata[2];
 
-  assign bank0_info1_page_cfg_erase_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_erase_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_erase_en_0_wd = reg_wdata[3];
 
-  assign bank0_info1_page_cfg_scramble_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_scramble_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_scramble_en_0_wd = reg_wdata[4];
 
-  assign bank0_info1_page_cfg_ecc_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_ecc_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_ecc_en_0_wd = reg_wdata[5];
 
-  assign bank0_info1_page_cfg_he_en_0_we = addr_hit[47] & reg_we & !reg_error;
+  assign bank0_info1_page_cfg_he_en_0_we = addr_hit[48] & reg_we & !reg_error;
   assign bank0_info1_page_cfg_he_en_0_wd = reg_wdata[6];
 
-  assign bank0_info2_regwen_0_we = addr_hit[48] & reg_we & !reg_error;
+  assign bank0_info2_regwen_0_we = addr_hit[49] & reg_we & !reg_error;
   assign bank0_info2_regwen_0_wd = reg_wdata[0];
 
-  assign bank0_info2_regwen_1_we = addr_hit[49] & reg_we & !reg_error;
+  assign bank0_info2_regwen_1_we = addr_hit[50] & reg_we & !reg_error;
   assign bank0_info2_regwen_1_wd = reg_wdata[0];
 
-  assign bank0_info2_page_cfg_0_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_en_0_wd = reg_wdata[0];
 
-  assign bank0_info2_page_cfg_0_rd_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_rd_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_rd_en_0_wd = reg_wdata[1];
 
-  assign bank0_info2_page_cfg_0_prog_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_prog_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_prog_en_0_wd = reg_wdata[2];
 
-  assign bank0_info2_page_cfg_0_erase_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_erase_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_erase_en_0_wd = reg_wdata[3];
 
-  assign bank0_info2_page_cfg_0_scramble_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_scramble_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
 
-  assign bank0_info2_page_cfg_0_ecc_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_ecc_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
 
-  assign bank0_info2_page_cfg_0_he_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_0_he_en_0_we = addr_hit[51] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_0_he_en_0_wd = reg_wdata[6];
 
-  assign bank0_info2_page_cfg_1_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_en_1_wd = reg_wdata[0];
 
-  assign bank0_info2_page_cfg_1_rd_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_rd_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_rd_en_1_wd = reg_wdata[1];
 
-  assign bank0_info2_page_cfg_1_prog_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_prog_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_prog_en_1_wd = reg_wdata[2];
 
-  assign bank0_info2_page_cfg_1_erase_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_erase_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_erase_en_1_wd = reg_wdata[3];
 
-  assign bank0_info2_page_cfg_1_scramble_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_scramble_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
 
-  assign bank0_info2_page_cfg_1_ecc_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_ecc_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
 
-  assign bank0_info2_page_cfg_1_he_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign bank0_info2_page_cfg_1_he_en_1_we = addr_hit[52] & reg_we & !reg_error;
   assign bank0_info2_page_cfg_1_he_en_1_wd = reg_wdata[6];
 
-  assign bank1_info0_regwen_0_we = addr_hit[52] & reg_we & !reg_error;
+  assign bank1_info0_regwen_0_we = addr_hit[53] & reg_we & !reg_error;
   assign bank1_info0_regwen_0_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_1_we = addr_hit[53] & reg_we & !reg_error;
+  assign bank1_info0_regwen_1_we = addr_hit[54] & reg_we & !reg_error;
   assign bank1_info0_regwen_1_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_2_we = addr_hit[54] & reg_we & !reg_error;
+  assign bank1_info0_regwen_2_we = addr_hit[55] & reg_we & !reg_error;
   assign bank1_info0_regwen_2_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_3_we = addr_hit[55] & reg_we & !reg_error;
+  assign bank1_info0_regwen_3_we = addr_hit[56] & reg_we & !reg_error;
   assign bank1_info0_regwen_3_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_4_we = addr_hit[56] & reg_we & !reg_error;
+  assign bank1_info0_regwen_4_we = addr_hit[57] & reg_we & !reg_error;
   assign bank1_info0_regwen_4_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_5_we = addr_hit[57] & reg_we & !reg_error;
+  assign bank1_info0_regwen_5_we = addr_hit[58] & reg_we & !reg_error;
   assign bank1_info0_regwen_5_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_6_we = addr_hit[58] & reg_we & !reg_error;
+  assign bank1_info0_regwen_6_we = addr_hit[59] & reg_we & !reg_error;
   assign bank1_info0_regwen_6_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_7_we = addr_hit[59] & reg_we & !reg_error;
+  assign bank1_info0_regwen_7_we = addr_hit[60] & reg_we & !reg_error;
   assign bank1_info0_regwen_7_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_8_we = addr_hit[60] & reg_we & !reg_error;
+  assign bank1_info0_regwen_8_we = addr_hit[61] & reg_we & !reg_error;
   assign bank1_info0_regwen_8_wd = reg_wdata[0];
 
-  assign bank1_info0_regwen_9_we = addr_hit[61] & reg_we & !reg_error;
+  assign bank1_info0_regwen_9_we = addr_hit[62] & reg_we & !reg_error;
   assign bank1_info0_regwen_9_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_0_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_en_0_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[62] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[63] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_1_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[63] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[64] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_2_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[64] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[65] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_3_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[65] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[66] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_4_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_en_4_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_4_rd_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_rd_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_rd_en_4_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_4_prog_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_prog_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_prog_en_4_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_4_erase_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_erase_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_erase_en_4_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_4_scramble_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_scramble_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_scramble_en_4_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_4_ecc_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_ecc_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_ecc_en_4_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_4_he_en_4_we = addr_hit[66] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_4_he_en_4_we = addr_hit[67] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_4_he_en_4_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_5_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_en_5_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_5_rd_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_rd_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_rd_en_5_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_5_prog_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_prog_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_prog_en_5_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_5_erase_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_erase_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_erase_en_5_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_5_scramble_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_scramble_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_scramble_en_5_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_5_ecc_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_ecc_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_ecc_en_5_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_5_he_en_5_we = addr_hit[67] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_5_he_en_5_we = addr_hit[68] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_5_he_en_5_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_6_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_en_6_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_6_rd_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_rd_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_rd_en_6_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_6_prog_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_prog_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_prog_en_6_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_6_erase_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_erase_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_erase_en_6_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_6_scramble_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_scramble_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_scramble_en_6_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_6_ecc_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_ecc_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_ecc_en_6_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_6_he_en_6_we = addr_hit[68] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_6_he_en_6_we = addr_hit[69] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_6_he_en_6_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_7_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_en_7_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_7_rd_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_rd_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_rd_en_7_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_7_prog_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_prog_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_prog_en_7_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_7_erase_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_erase_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_erase_en_7_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_7_scramble_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_scramble_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_scramble_en_7_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_7_ecc_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_ecc_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_ecc_en_7_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_7_he_en_7_we = addr_hit[69] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_7_he_en_7_we = addr_hit[70] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_7_he_en_7_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_8_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_en_8_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_8_rd_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_rd_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_rd_en_8_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_8_prog_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_prog_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_prog_en_8_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_8_erase_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_erase_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_erase_en_8_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_8_scramble_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_scramble_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_scramble_en_8_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_8_ecc_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_ecc_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_ecc_en_8_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_8_he_en_8_we = addr_hit[70] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_8_he_en_8_we = addr_hit[71] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_8_he_en_8_wd = reg_wdata[6];
 
-  assign bank1_info0_page_cfg_9_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_en_9_wd = reg_wdata[0];
 
-  assign bank1_info0_page_cfg_9_rd_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_rd_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_rd_en_9_wd = reg_wdata[1];
 
-  assign bank1_info0_page_cfg_9_prog_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_prog_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_prog_en_9_wd = reg_wdata[2];
 
-  assign bank1_info0_page_cfg_9_erase_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_erase_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_erase_en_9_wd = reg_wdata[3];
 
-  assign bank1_info0_page_cfg_9_scramble_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_scramble_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_scramble_en_9_wd = reg_wdata[4];
 
-  assign bank1_info0_page_cfg_9_ecc_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_ecc_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_ecc_en_9_wd = reg_wdata[5];
 
-  assign bank1_info0_page_cfg_9_he_en_9_we = addr_hit[71] & reg_we & !reg_error;
+  assign bank1_info0_page_cfg_9_he_en_9_we = addr_hit[72] & reg_we & !reg_error;
   assign bank1_info0_page_cfg_9_he_en_9_wd = reg_wdata[6];
 
-  assign bank1_info1_regwen_we = addr_hit[72] & reg_we & !reg_error;
+  assign bank1_info1_regwen_we = addr_hit[73] & reg_we & !reg_error;
   assign bank1_info1_regwen_wd = reg_wdata[0];
 
-  assign bank1_info1_page_cfg_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_en_0_wd = reg_wdata[0];
 
-  assign bank1_info1_page_cfg_rd_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_rd_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_rd_en_0_wd = reg_wdata[1];
 
-  assign bank1_info1_page_cfg_prog_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_prog_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_prog_en_0_wd = reg_wdata[2];
 
-  assign bank1_info1_page_cfg_erase_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_erase_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_erase_en_0_wd = reg_wdata[3];
 
-  assign bank1_info1_page_cfg_scramble_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_scramble_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_scramble_en_0_wd = reg_wdata[4];
 
-  assign bank1_info1_page_cfg_ecc_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_ecc_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_ecc_en_0_wd = reg_wdata[5];
 
-  assign bank1_info1_page_cfg_he_en_0_we = addr_hit[73] & reg_we & !reg_error;
+  assign bank1_info1_page_cfg_he_en_0_we = addr_hit[74] & reg_we & !reg_error;
   assign bank1_info1_page_cfg_he_en_0_wd = reg_wdata[6];
 
-  assign bank1_info2_regwen_0_we = addr_hit[74] & reg_we & !reg_error;
+  assign bank1_info2_regwen_0_we = addr_hit[75] & reg_we & !reg_error;
   assign bank1_info2_regwen_0_wd = reg_wdata[0];
 
-  assign bank1_info2_regwen_1_we = addr_hit[75] & reg_we & !reg_error;
+  assign bank1_info2_regwen_1_we = addr_hit[76] & reg_we & !reg_error;
   assign bank1_info2_regwen_1_wd = reg_wdata[0];
 
-  assign bank1_info2_page_cfg_0_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_en_0_wd = reg_wdata[0];
 
-  assign bank1_info2_page_cfg_0_rd_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_rd_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_rd_en_0_wd = reg_wdata[1];
 
-  assign bank1_info2_page_cfg_0_prog_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_prog_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_prog_en_0_wd = reg_wdata[2];
 
-  assign bank1_info2_page_cfg_0_erase_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_erase_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_erase_en_0_wd = reg_wdata[3];
 
-  assign bank1_info2_page_cfg_0_scramble_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_scramble_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
 
-  assign bank1_info2_page_cfg_0_ecc_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_ecc_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
 
-  assign bank1_info2_page_cfg_0_he_en_0_we = addr_hit[76] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_0_he_en_0_we = addr_hit[77] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_0_he_en_0_wd = reg_wdata[6];
 
-  assign bank1_info2_page_cfg_1_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_en_1_wd = reg_wdata[0];
 
-  assign bank1_info2_page_cfg_1_rd_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_rd_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_rd_en_1_wd = reg_wdata[1];
 
-  assign bank1_info2_page_cfg_1_prog_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_prog_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_prog_en_1_wd = reg_wdata[2];
 
-  assign bank1_info2_page_cfg_1_erase_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_erase_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_erase_en_1_wd = reg_wdata[3];
 
-  assign bank1_info2_page_cfg_1_scramble_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_scramble_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
 
-  assign bank1_info2_page_cfg_1_ecc_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_ecc_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
 
-  assign bank1_info2_page_cfg_1_he_en_1_we = addr_hit[77] & reg_we & !reg_error;
+  assign bank1_info2_page_cfg_1_he_en_1_we = addr_hit[78] & reg_we & !reg_error;
   assign bank1_info2_page_cfg_1_he_en_1_wd = reg_wdata[6];
 
-  assign bank_cfg_regwen_we = addr_hit[78] & reg_we & !reg_error;
+  assign bank_cfg_regwen_we = addr_hit[79] & reg_we & !reg_error;
   assign bank_cfg_regwen_wd = reg_wdata[0];
 
-  assign mp_bank_cfg_erase_en_0_we = addr_hit[79] & reg_we & !reg_error;
+  assign mp_bank_cfg_erase_en_0_we = addr_hit[80] & reg_we & !reg_error;
   assign mp_bank_cfg_erase_en_0_wd = reg_wdata[0];
 
-  assign mp_bank_cfg_erase_en_1_we = addr_hit[79] & reg_we & !reg_error;
+  assign mp_bank_cfg_erase_en_1_we = addr_hit[80] & reg_we & !reg_error;
   assign mp_bank_cfg_erase_en_1_wd = reg_wdata[1];
 
-  assign op_status_done_we = addr_hit[80] & reg_we & !reg_error;
+  assign op_status_done_we = addr_hit[81] & reg_we & !reg_error;
   assign op_status_done_wd = reg_wdata[0];
 
-  assign op_status_err_we = addr_hit[80] & reg_we & !reg_error;
+  assign op_status_err_we = addr_hit[81] & reg_we & !reg_error;
   assign op_status_err_wd = reg_wdata[1];
 
-  assign err_code_intr_en_flash_err_en_we = addr_hit[82] & reg_we & !reg_error;
+  assign err_code_intr_en_flash_err_en_we = addr_hit[83] & reg_we & !reg_error;
   assign err_code_intr_en_flash_err_en_wd = reg_wdata[0];
 
-  assign err_code_intr_en_flash_alert_en_we = addr_hit[82] & reg_we & !reg_error;
+  assign err_code_intr_en_flash_alert_en_we = addr_hit[83] & reg_we & !reg_error;
   assign err_code_intr_en_flash_alert_en_wd = reg_wdata[1];
 
-  assign err_code_intr_en_mp_err_we = addr_hit[82] & reg_we & !reg_error;
+  assign err_code_intr_en_mp_err_we = addr_hit[83] & reg_we & !reg_error;
   assign err_code_intr_en_mp_err_wd = reg_wdata[2];
 
-  assign err_code_intr_en_ecc_single_err_we = addr_hit[82] & reg_we & !reg_error;
+  assign err_code_intr_en_ecc_single_err_we = addr_hit[83] & reg_we & !reg_error;
   assign err_code_intr_en_ecc_single_err_wd = reg_wdata[3];
 
-  assign err_code_intr_en_ecc_multi_err_we = addr_hit[82] & reg_we & !reg_error;
+  assign err_code_intr_en_ecc_multi_err_we = addr_hit[83] & reg_we & !reg_error;
   assign err_code_intr_en_ecc_multi_err_wd = reg_wdata[4];
 
-  assign err_code_flash_err_we = addr_hit[83] & reg_we & !reg_error;
+  assign err_code_flash_err_we = addr_hit[84] & reg_we & !reg_error;
   assign err_code_flash_err_wd = reg_wdata[0];
 
-  assign err_code_flash_alert_we = addr_hit[83] & reg_we & !reg_error;
+  assign err_code_flash_alert_we = addr_hit[84] & reg_we & !reg_error;
   assign err_code_flash_alert_wd = reg_wdata[1];
 
-  assign err_code_mp_err_we = addr_hit[83] & reg_we & !reg_error;
+  assign err_code_mp_err_we = addr_hit[84] & reg_we & !reg_error;
   assign err_code_mp_err_wd = reg_wdata[2];
 
-  assign err_code_ecc_single_err_we = addr_hit[83] & reg_we & !reg_error;
+  assign err_code_ecc_single_err_we = addr_hit[84] & reg_we & !reg_error;
   assign err_code_ecc_single_err_wd = reg_wdata[3];
 
-  assign err_code_ecc_multi_err_we = addr_hit[83] & reg_we & !reg_error;
+  assign err_code_ecc_multi_err_we = addr_hit[84] & reg_we & !reg_error;
   assign err_code_ecc_multi_err_wd = reg_wdata[4];
 
-  assign ecc_single_err_cnt_we = addr_hit[85] & reg_we & !reg_error;
+  assign ecc_single_err_cnt_we = addr_hit[86] & reg_we & !reg_error;
   assign ecc_single_err_cnt_wd = reg_wdata[7:0];
 
-  assign ecc_multi_err_cnt_we = addr_hit[88] & reg_we & !reg_error;
+  assign ecc_multi_err_cnt_we = addr_hit[89] & reg_we & !reg_error;
   assign ecc_multi_err_cnt_wd = reg_wdata[7:0];
 
-  assign phy_err_cfg_regwen_we = addr_hit[91] & reg_we & !reg_error;
+  assign phy_err_cfg_regwen_we = addr_hit[92] & reg_we & !reg_error;
   assign phy_err_cfg_regwen_wd = reg_wdata[0];
 
-  assign phy_err_cfg_we = addr_hit[92] & reg_we & !reg_error;
+  assign phy_err_cfg_we = addr_hit[93] & reg_we & !reg_error;
   assign phy_err_cfg_wd = reg_wdata[0];
 
-  assign phy_alert_cfg_alert_ack_we = addr_hit[93] & reg_we & !reg_error;
+  assign phy_alert_cfg_alert_ack_we = addr_hit[94] & reg_we & !reg_error;
   assign phy_alert_cfg_alert_ack_wd = reg_wdata[0];
 
-  assign phy_alert_cfg_alert_trig_we = addr_hit[93] & reg_we & !reg_error;
+  assign phy_alert_cfg_alert_trig_we = addr_hit[94] & reg_we & !reg_error;
   assign phy_alert_cfg_alert_trig_wd = reg_wdata[1];
 
-  assign scratch_we = addr_hit[95] & reg_we & !reg_error;
+  assign scratch_we = addr_hit[96] & reg_we & !reg_error;
   assign scratch_wd = reg_wdata[31:0];
 
-  assign fifo_lvl_prog_we = addr_hit[96] & reg_we & !reg_error;
+  assign fifo_lvl_prog_we = addr_hit[97] & reg_we & !reg_error;
   assign fifo_lvl_prog_wd = reg_wdata[4:0];
 
-  assign fifo_lvl_rd_we = addr_hit[96] & reg_we & !reg_error;
+  assign fifo_lvl_rd_we = addr_hit[97] & reg_we & !reg_error;
   assign fifo_lvl_rd_wd = reg_wdata[12:8];
 
-  assign fifo_rst_we = addr_hit[97] & reg_we & !reg_error;
+  assign fifo_rst_we = addr_hit[98] & reg_we & !reg_error;
   assign fifo_rst_wd = reg_wdata[0];
 
   // Read data return
@@ -12125,10 +12160,14 @@
       end
 
       addr_hit[4]: begin
-        reg_rdata_next[0] = ctrl_regwen_qs;
+        reg_rdata_next[0] = init_qs;
       end
 
       addr_hit[5]: begin
+        reg_rdata_next[0] = ctrl_regwen_qs;
+      end
+
+      addr_hit[6]: begin
         reg_rdata_next[0] = control_start_qs;
         reg_rdata_next[5:4] = control_op_qs;
         reg_rdata_next[6] = control_prog_sel_qs;
@@ -12138,52 +12177,52 @@
         reg_rdata_next[27:16] = control_num_qs;
       end
 
-      addr_hit[6]: begin
+      addr_hit[7]: begin
         reg_rdata_next[31:0] = addr_qs;
       end
 
-      addr_hit[7]: begin
+      addr_hit[8]: begin
         reg_rdata_next[0] = prog_type_en_normal_qs;
         reg_rdata_next[1] = prog_type_en_repair_qs;
       end
 
-      addr_hit[8]: begin
+      addr_hit[9]: begin
         reg_rdata_next[0] = erase_suspend_qs;
       end
 
-      addr_hit[9]: begin
+      addr_hit[10]: begin
         reg_rdata_next[0] = region_cfg_regwen_0_qs;
       end
 
-      addr_hit[10]: begin
+      addr_hit[11]: begin
         reg_rdata_next[0] = region_cfg_regwen_1_qs;
       end
 
-      addr_hit[11]: begin
+      addr_hit[12]: begin
         reg_rdata_next[0] = region_cfg_regwen_2_qs;
       end
 
-      addr_hit[12]: begin
+      addr_hit[13]: begin
         reg_rdata_next[0] = region_cfg_regwen_3_qs;
       end
 
-      addr_hit[13]: begin
+      addr_hit[14]: begin
         reg_rdata_next[0] = region_cfg_regwen_4_qs;
       end
 
-      addr_hit[14]: begin
+      addr_hit[15]: begin
         reg_rdata_next[0] = region_cfg_regwen_5_qs;
       end
 
-      addr_hit[15]: begin
+      addr_hit[16]: begin
         reg_rdata_next[0] = region_cfg_regwen_6_qs;
       end
 
-      addr_hit[16]: begin
+      addr_hit[17]: begin
         reg_rdata_next[0] = region_cfg_regwen_7_qs;
       end
 
-      addr_hit[17]: begin
+      addr_hit[18]: begin
         reg_rdata_next[0] = mp_region_cfg_0_en_0_qs;
         reg_rdata_next[1] = mp_region_cfg_0_rd_en_0_qs;
         reg_rdata_next[2] = mp_region_cfg_0_prog_en_0_qs;
@@ -12195,7 +12234,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_0_size_0_qs;
       end
 
-      addr_hit[18]: begin
+      addr_hit[19]: begin
         reg_rdata_next[0] = mp_region_cfg_1_en_1_qs;
         reg_rdata_next[1] = mp_region_cfg_1_rd_en_1_qs;
         reg_rdata_next[2] = mp_region_cfg_1_prog_en_1_qs;
@@ -12207,7 +12246,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_1_size_1_qs;
       end
 
-      addr_hit[19]: begin
+      addr_hit[20]: begin
         reg_rdata_next[0] = mp_region_cfg_2_en_2_qs;
         reg_rdata_next[1] = mp_region_cfg_2_rd_en_2_qs;
         reg_rdata_next[2] = mp_region_cfg_2_prog_en_2_qs;
@@ -12219,7 +12258,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_2_size_2_qs;
       end
 
-      addr_hit[20]: begin
+      addr_hit[21]: begin
         reg_rdata_next[0] = mp_region_cfg_3_en_3_qs;
         reg_rdata_next[1] = mp_region_cfg_3_rd_en_3_qs;
         reg_rdata_next[2] = mp_region_cfg_3_prog_en_3_qs;
@@ -12231,7 +12270,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_3_size_3_qs;
       end
 
-      addr_hit[21]: begin
+      addr_hit[22]: begin
         reg_rdata_next[0] = mp_region_cfg_4_en_4_qs;
         reg_rdata_next[1] = mp_region_cfg_4_rd_en_4_qs;
         reg_rdata_next[2] = mp_region_cfg_4_prog_en_4_qs;
@@ -12243,7 +12282,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_4_size_4_qs;
       end
 
-      addr_hit[22]: begin
+      addr_hit[23]: begin
         reg_rdata_next[0] = mp_region_cfg_5_en_5_qs;
         reg_rdata_next[1] = mp_region_cfg_5_rd_en_5_qs;
         reg_rdata_next[2] = mp_region_cfg_5_prog_en_5_qs;
@@ -12255,7 +12294,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_5_size_5_qs;
       end
 
-      addr_hit[23]: begin
+      addr_hit[24]: begin
         reg_rdata_next[0] = mp_region_cfg_6_en_6_qs;
         reg_rdata_next[1] = mp_region_cfg_6_rd_en_6_qs;
         reg_rdata_next[2] = mp_region_cfg_6_prog_en_6_qs;
@@ -12267,7 +12306,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_6_size_6_qs;
       end
 
-      addr_hit[24]: begin
+      addr_hit[25]: begin
         reg_rdata_next[0] = mp_region_cfg_7_en_7_qs;
         reg_rdata_next[1] = mp_region_cfg_7_rd_en_7_qs;
         reg_rdata_next[2] = mp_region_cfg_7_prog_en_7_qs;
@@ -12279,7 +12318,7 @@
         reg_rdata_next[26:17] = mp_region_cfg_7_size_7_qs;
       end
 
-      addr_hit[25]: begin
+      addr_hit[26]: begin
         reg_rdata_next[0] = default_region_rd_en_qs;
         reg_rdata_next[1] = default_region_prog_en_qs;
         reg_rdata_next[2] = default_region_erase_en_qs;
@@ -12288,47 +12327,47 @@
         reg_rdata_next[5] = default_region_he_en_qs;
       end
 
-      addr_hit[26]: begin
+      addr_hit[27]: begin
         reg_rdata_next[0] = bank0_info0_regwen_0_qs;
       end
 
-      addr_hit[27]: begin
+      addr_hit[28]: begin
         reg_rdata_next[0] = bank0_info0_regwen_1_qs;
       end
 
-      addr_hit[28]: begin
+      addr_hit[29]: begin
         reg_rdata_next[0] = bank0_info0_regwen_2_qs;
       end
 
-      addr_hit[29]: begin
+      addr_hit[30]: begin
         reg_rdata_next[0] = bank0_info0_regwen_3_qs;
       end
 
-      addr_hit[30]: begin
+      addr_hit[31]: begin
         reg_rdata_next[0] = bank0_info0_regwen_4_qs;
       end
 
-      addr_hit[31]: begin
+      addr_hit[32]: begin
         reg_rdata_next[0] = bank0_info0_regwen_5_qs;
       end
 
-      addr_hit[32]: begin
+      addr_hit[33]: begin
         reg_rdata_next[0] = bank0_info0_regwen_6_qs;
       end
 
-      addr_hit[33]: begin
+      addr_hit[34]: begin
         reg_rdata_next[0] = bank0_info0_regwen_7_qs;
       end
 
-      addr_hit[34]: begin
+      addr_hit[35]: begin
         reg_rdata_next[0] = bank0_info0_regwen_8_qs;
       end
 
-      addr_hit[35]: begin
+      addr_hit[36]: begin
         reg_rdata_next[0] = bank0_info0_regwen_9_qs;
       end
 
-      addr_hit[36]: begin
+      addr_hit[37]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_0_en_0_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_0_rd_en_0_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_0_prog_en_0_qs;
@@ -12338,7 +12377,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_0_he_en_0_qs;
       end
 
-      addr_hit[37]: begin
+      addr_hit[38]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_1_en_1_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_1_rd_en_1_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_1_prog_en_1_qs;
@@ -12348,7 +12387,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_1_he_en_1_qs;
       end
 
-      addr_hit[38]: begin
+      addr_hit[39]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_2_en_2_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_2_rd_en_2_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_2_prog_en_2_qs;
@@ -12358,7 +12397,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_2_he_en_2_qs;
       end
 
-      addr_hit[39]: begin
+      addr_hit[40]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_3_en_3_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_3_rd_en_3_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_3_prog_en_3_qs;
@@ -12368,7 +12407,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_3_he_en_3_qs;
       end
 
-      addr_hit[40]: begin
+      addr_hit[41]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_4_en_4_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_4_rd_en_4_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_4_prog_en_4_qs;
@@ -12378,7 +12417,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_4_he_en_4_qs;
       end
 
-      addr_hit[41]: begin
+      addr_hit[42]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_5_en_5_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_5_rd_en_5_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_5_prog_en_5_qs;
@@ -12388,7 +12427,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_5_he_en_5_qs;
       end
 
-      addr_hit[42]: begin
+      addr_hit[43]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_6_en_6_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_6_rd_en_6_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_6_prog_en_6_qs;
@@ -12398,7 +12437,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_6_he_en_6_qs;
       end
 
-      addr_hit[43]: begin
+      addr_hit[44]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_7_en_7_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_7_rd_en_7_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_7_prog_en_7_qs;
@@ -12408,7 +12447,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_7_he_en_7_qs;
       end
 
-      addr_hit[44]: begin
+      addr_hit[45]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_8_en_8_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_8_rd_en_8_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_8_prog_en_8_qs;
@@ -12418,7 +12457,7 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_8_he_en_8_qs;
       end
 
-      addr_hit[45]: begin
+      addr_hit[46]: begin
         reg_rdata_next[0] = bank0_info0_page_cfg_9_en_9_qs;
         reg_rdata_next[1] = bank0_info0_page_cfg_9_rd_en_9_qs;
         reg_rdata_next[2] = bank0_info0_page_cfg_9_prog_en_9_qs;
@@ -12428,11 +12467,11 @@
         reg_rdata_next[6] = bank0_info0_page_cfg_9_he_en_9_qs;
       end
 
-      addr_hit[46]: begin
+      addr_hit[47]: begin
         reg_rdata_next[0] = bank0_info1_regwen_qs;
       end
 
-      addr_hit[47]: begin
+      addr_hit[48]: begin
         reg_rdata_next[0] = bank0_info1_page_cfg_en_0_qs;
         reg_rdata_next[1] = bank0_info1_page_cfg_rd_en_0_qs;
         reg_rdata_next[2] = bank0_info1_page_cfg_prog_en_0_qs;
@@ -12442,15 +12481,15 @@
         reg_rdata_next[6] = bank0_info1_page_cfg_he_en_0_qs;
       end
 
-      addr_hit[48]: begin
+      addr_hit[49]: begin
         reg_rdata_next[0] = bank0_info2_regwen_0_qs;
       end
 
-      addr_hit[49]: begin
+      addr_hit[50]: begin
         reg_rdata_next[0] = bank0_info2_regwen_1_qs;
       end
 
-      addr_hit[50]: begin
+      addr_hit[51]: begin
         reg_rdata_next[0] = bank0_info2_page_cfg_0_en_0_qs;
         reg_rdata_next[1] = bank0_info2_page_cfg_0_rd_en_0_qs;
         reg_rdata_next[2] = bank0_info2_page_cfg_0_prog_en_0_qs;
@@ -12460,7 +12499,7 @@
         reg_rdata_next[6] = bank0_info2_page_cfg_0_he_en_0_qs;
       end
 
-      addr_hit[51]: begin
+      addr_hit[52]: begin
         reg_rdata_next[0] = bank0_info2_page_cfg_1_en_1_qs;
         reg_rdata_next[1] = bank0_info2_page_cfg_1_rd_en_1_qs;
         reg_rdata_next[2] = bank0_info2_page_cfg_1_prog_en_1_qs;
@@ -12470,47 +12509,47 @@
         reg_rdata_next[6] = bank0_info2_page_cfg_1_he_en_1_qs;
       end
 
-      addr_hit[52]: begin
+      addr_hit[53]: begin
         reg_rdata_next[0] = bank1_info0_regwen_0_qs;
       end
 
-      addr_hit[53]: begin
+      addr_hit[54]: begin
         reg_rdata_next[0] = bank1_info0_regwen_1_qs;
       end
 
-      addr_hit[54]: begin
+      addr_hit[55]: begin
         reg_rdata_next[0] = bank1_info0_regwen_2_qs;
       end
 
-      addr_hit[55]: begin
+      addr_hit[56]: begin
         reg_rdata_next[0] = bank1_info0_regwen_3_qs;
       end
 
-      addr_hit[56]: begin
+      addr_hit[57]: begin
         reg_rdata_next[0] = bank1_info0_regwen_4_qs;
       end
 
-      addr_hit[57]: begin
+      addr_hit[58]: begin
         reg_rdata_next[0] = bank1_info0_regwen_5_qs;
       end
 
-      addr_hit[58]: begin
+      addr_hit[59]: begin
         reg_rdata_next[0] = bank1_info0_regwen_6_qs;
       end
 
-      addr_hit[59]: begin
+      addr_hit[60]: begin
         reg_rdata_next[0] = bank1_info0_regwen_7_qs;
       end
 
-      addr_hit[60]: begin
+      addr_hit[61]: begin
         reg_rdata_next[0] = bank1_info0_regwen_8_qs;
       end
 
-      addr_hit[61]: begin
+      addr_hit[62]: begin
         reg_rdata_next[0] = bank1_info0_regwen_9_qs;
       end
 
-      addr_hit[62]: begin
+      addr_hit[63]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_0_en_0_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_0_rd_en_0_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_0_prog_en_0_qs;
@@ -12520,7 +12559,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_0_he_en_0_qs;
       end
 
-      addr_hit[63]: begin
+      addr_hit[64]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_1_en_1_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_1_rd_en_1_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_1_prog_en_1_qs;
@@ -12530,7 +12569,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_1_he_en_1_qs;
       end
 
-      addr_hit[64]: begin
+      addr_hit[65]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_2_en_2_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_2_rd_en_2_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_2_prog_en_2_qs;
@@ -12540,7 +12579,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_2_he_en_2_qs;
       end
 
-      addr_hit[65]: begin
+      addr_hit[66]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_3_en_3_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_3_rd_en_3_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_3_prog_en_3_qs;
@@ -12550,7 +12589,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_3_he_en_3_qs;
       end
 
-      addr_hit[66]: begin
+      addr_hit[67]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_4_en_4_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_4_rd_en_4_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_4_prog_en_4_qs;
@@ -12560,7 +12599,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_4_he_en_4_qs;
       end
 
-      addr_hit[67]: begin
+      addr_hit[68]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_5_en_5_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_5_rd_en_5_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_5_prog_en_5_qs;
@@ -12570,7 +12609,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_5_he_en_5_qs;
       end
 
-      addr_hit[68]: begin
+      addr_hit[69]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_6_en_6_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_6_rd_en_6_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_6_prog_en_6_qs;
@@ -12580,7 +12619,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_6_he_en_6_qs;
       end
 
-      addr_hit[69]: begin
+      addr_hit[70]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_7_en_7_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_7_rd_en_7_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_7_prog_en_7_qs;
@@ -12590,7 +12629,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_7_he_en_7_qs;
       end
 
-      addr_hit[70]: begin
+      addr_hit[71]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_8_en_8_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_8_rd_en_8_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_8_prog_en_8_qs;
@@ -12600,7 +12639,7 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_8_he_en_8_qs;
       end
 
-      addr_hit[71]: begin
+      addr_hit[72]: begin
         reg_rdata_next[0] = bank1_info0_page_cfg_9_en_9_qs;
         reg_rdata_next[1] = bank1_info0_page_cfg_9_rd_en_9_qs;
         reg_rdata_next[2] = bank1_info0_page_cfg_9_prog_en_9_qs;
@@ -12610,11 +12649,11 @@
         reg_rdata_next[6] = bank1_info0_page_cfg_9_he_en_9_qs;
       end
 
-      addr_hit[72]: begin
+      addr_hit[73]: begin
         reg_rdata_next[0] = bank1_info1_regwen_qs;
       end
 
-      addr_hit[73]: begin
+      addr_hit[74]: begin
         reg_rdata_next[0] = bank1_info1_page_cfg_en_0_qs;
         reg_rdata_next[1] = bank1_info1_page_cfg_rd_en_0_qs;
         reg_rdata_next[2] = bank1_info1_page_cfg_prog_en_0_qs;
@@ -12624,15 +12663,15 @@
         reg_rdata_next[6] = bank1_info1_page_cfg_he_en_0_qs;
       end
 
-      addr_hit[74]: begin
+      addr_hit[75]: begin
         reg_rdata_next[0] = bank1_info2_regwen_0_qs;
       end
 
-      addr_hit[75]: begin
+      addr_hit[76]: begin
         reg_rdata_next[0] = bank1_info2_regwen_1_qs;
       end
 
-      addr_hit[76]: begin
+      addr_hit[77]: begin
         reg_rdata_next[0] = bank1_info2_page_cfg_0_en_0_qs;
         reg_rdata_next[1] = bank1_info2_page_cfg_0_rd_en_0_qs;
         reg_rdata_next[2] = bank1_info2_page_cfg_0_prog_en_0_qs;
@@ -12642,7 +12681,7 @@
         reg_rdata_next[6] = bank1_info2_page_cfg_0_he_en_0_qs;
       end
 
-      addr_hit[77]: begin
+      addr_hit[78]: begin
         reg_rdata_next[0] = bank1_info2_page_cfg_1_en_1_qs;
         reg_rdata_next[1] = bank1_info2_page_cfg_1_rd_en_1_qs;
         reg_rdata_next[2] = bank1_info2_page_cfg_1_prog_en_1_qs;
@@ -12652,21 +12691,21 @@
         reg_rdata_next[6] = bank1_info2_page_cfg_1_he_en_1_qs;
       end
 
-      addr_hit[78]: begin
+      addr_hit[79]: begin
         reg_rdata_next[0] = bank_cfg_regwen_qs;
       end
 
-      addr_hit[79]: begin
+      addr_hit[80]: begin
         reg_rdata_next[0] = mp_bank_cfg_erase_en_0_qs;
         reg_rdata_next[1] = mp_bank_cfg_erase_en_1_qs;
       end
 
-      addr_hit[80]: begin
+      addr_hit[81]: begin
         reg_rdata_next[0] = op_status_done_qs;
         reg_rdata_next[1] = op_status_err_qs;
       end
 
-      addr_hit[81]: begin
+      addr_hit[82]: begin
         reg_rdata_next[0] = status_rd_full_qs;
         reg_rdata_next[1] = status_rd_empty_qs;
         reg_rdata_next[2] = status_prog_full_qs;
@@ -12674,7 +12713,7 @@
         reg_rdata_next[4] = status_init_wip_qs;
       end
 
-      addr_hit[82]: begin
+      addr_hit[83]: begin
         reg_rdata_next[0] = err_code_intr_en_flash_err_en_qs;
         reg_rdata_next[1] = err_code_intr_en_flash_alert_en_qs;
         reg_rdata_next[2] = err_code_intr_en_mp_err_qs;
@@ -12682,7 +12721,7 @@
         reg_rdata_next[4] = err_code_intr_en_ecc_multi_err_qs;
       end
 
-      addr_hit[83]: begin
+      addr_hit[84]: begin
         reg_rdata_next[0] = err_code_flash_err_qs;
         reg_rdata_next[1] = err_code_flash_alert_qs;
         reg_rdata_next[2] = err_code_mp_err_qs;
@@ -12690,63 +12729,63 @@
         reg_rdata_next[4] = err_code_ecc_multi_err_qs;
       end
 
-      addr_hit[84]: begin
+      addr_hit[85]: begin
         reg_rdata_next[8:0] = err_addr_qs;
       end
 
-      addr_hit[85]: begin
+      addr_hit[86]: begin
         reg_rdata_next[7:0] = ecc_single_err_cnt_qs;
       end
 
-      addr_hit[86]: begin
+      addr_hit[87]: begin
         reg_rdata_next[19:0] = ecc_single_err_addr_0_qs;
       end
 
-      addr_hit[87]: begin
+      addr_hit[88]: begin
         reg_rdata_next[19:0] = ecc_single_err_addr_1_qs;
       end
 
-      addr_hit[88]: begin
+      addr_hit[89]: begin
         reg_rdata_next[7:0] = ecc_multi_err_cnt_qs;
       end
 
-      addr_hit[89]: begin
+      addr_hit[90]: begin
         reg_rdata_next[19:0] = ecc_multi_err_addr_0_qs;
       end
 
-      addr_hit[90]: begin
+      addr_hit[91]: begin
         reg_rdata_next[19:0] = ecc_multi_err_addr_1_qs;
       end
 
-      addr_hit[91]: begin
+      addr_hit[92]: begin
         reg_rdata_next[0] = phy_err_cfg_regwen_qs;
       end
 
-      addr_hit[92]: begin
+      addr_hit[93]: begin
         reg_rdata_next[0] = phy_err_cfg_qs;
       end
 
-      addr_hit[93]: begin
+      addr_hit[94]: begin
         reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
         reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
       end
 
-      addr_hit[94]: begin
+      addr_hit[95]: begin
         reg_rdata_next[0] = phy_status_init_wip_qs;
         reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
         reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
       end
 
-      addr_hit[95]: begin
+      addr_hit[96]: begin
         reg_rdata_next[31:0] = scratch_qs;
       end
 
-      addr_hit[96]: begin
+      addr_hit[97]: begin
         reg_rdata_next[4:0] = fifo_lvl_prog_qs;
         reg_rdata_next[12:8] = fifo_lvl_rd_qs;
       end
 
-      addr_hit[97]: begin
+      addr_hit[98]: begin
         reg_rdata_next[0] = fifo_rst_qs;
       end
 
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
index 437654c..5fca6c6 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
@@ -16,7 +16,6 @@
 
   // initialization command
   input init_i,
-  output logic init_done_o,
 
   // only access seeds when provisioned
   input provision_en_i,
@@ -106,7 +105,6 @@
   lc_ctrl_pkg::lc_tx_t err_sts;
   logic err_sts_set;
   lc_ctrl_pkg::lc_tx_t rma_ack_d, rma_ack_q;
-  logic init_done_d;
   logic validate_q, validate_d;
   logic [SeedCntWidth-1:0] seed_cnt_q;
   logic [SeedRdsWidth-1:0] addr_cnt_q;
@@ -127,12 +125,10 @@
       state_q <= StIdle;
       rma_ack_q <= lc_ctrl_pkg::Off;
       validate_q <= 1'b0;
-      init_done_o <= 1'b0;
     end else begin
       state_q <= state_d;
       rma_ack_q <= rma_ack_d;
       validate_q <= validate_d;
-      init_done_o <= init_done_d;
     end
   end
 
@@ -297,13 +293,6 @@
     // read buffer enable
     rd_buf_en_o = 1'b0;
 
-    // init status
-    // flash_ctrl handles its own arbitration between hardware and software.
-    // So once the init kicks off it is safe to ack.  The done signal is still
-    // to give a chance to hold off further power up progression in the future
-    // if required.
-    init_done_d = 1'b1;
-
     addr_key_req_d = 1'b0;
     data_key_req_d = 1'b0;
 
@@ -318,14 +307,13 @@
     unique case (state_q)
 
       StIdle: begin
-        init_done_d = 1'b0;
-        phase = PhaseSeed;
         if (init_q) begin
           state_d = StReqAddrKey;
         end
       end
 
       StReqAddrKey: begin
+        phase = PhaseSeed;
         addr_key_req_d = 1'b1;
         if (addr_key_ack_q) begin
           state_d = StReqDataKey;
@@ -333,6 +321,7 @@
       end
 
       StReqDataKey: begin
+        phase = PhaseSeed;
         data_key_req_d = 1'b1;
         if (data_key_ack_q) begin
           // provision_en is only a "good" value after otp/lc initialization
@@ -351,7 +340,7 @@
         info_sel = seed_info_sel;
 
         // we have checked all seeds, proceed
-        if (seed_cnt_q == NumSeeds[SeedCntWidth-1:0]) begin
+        if (seed_cnt_q == NumSeeds) begin
           start = 1'b0;
           state_d = StWait;
 
@@ -498,7 +487,7 @@
     end else if (word_cnt_clr) begin
       word_cnt <= '0;
     end else if (word_cnt_incr) begin
-      word_cnt <= word_cnt + WidthMultiple[WordCntWidth-1:0];
+      word_cnt <= word_cnt + WidthMultiple;
     end
   end
 
@@ -557,7 +546,7 @@
 
   assign rma_part_sel = RmaWipeEntries[rma_wipe_idx].part;
   assign rma_info_sel = RmaWipeEntries[rma_wipe_idx].info_sel;
-  assign rma_num_words = WidthMultiple[11:0] - 1;
+  assign rma_num_words = WidthMultiple - 1;
 
 
   //fsm for handling the actual wipe
@@ -605,7 +594,7 @@
       end
 
       StRmaWordSel: begin
-        if (word_cnt < BusWordsPerPage[WordCntWidth-1:0]) begin
+        if (word_cnt < BusWordsPerPage) begin
           rma_state_d = StRmaProgram;
         end else begin
           word_cnt_clr = 1'b1;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index 7a24434..1796bcf 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -119,6 +119,10 @@
   } flash_ctrl_reg2hw_alert_test_reg_t;
 
   typedef struct packed {
+    logic        q;
+  } flash_ctrl_reg2hw_init_reg_t;
+
+  typedef struct packed {
     struct packed {
       logic        q;
     } start;
@@ -574,10 +578,11 @@
 
   // Register -> HW type for core interface
   typedef struct packed {
-    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [556:551]
-    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [550:545]
-    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [544:533]
-    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [532:525]
+    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [557:552]
+    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [551:546]
+    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [545:534]
+    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [533:526]
+    flash_ctrl_reg2hw_init_reg_t init; // [525:525]
     flash_ctrl_reg2hw_control_reg_t control; // [524:505]
     flash_ctrl_reg2hw_addr_reg_t addr; // [504:473]
     flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [472:471]
@@ -624,100 +629,101 @@
   parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 9'h 4;
   parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_TEST_OFFSET = 9'h 8;
   parameter logic [CoreAw-1:0] FLASH_CTRL_ALERT_TEST_OFFSET = 9'h c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h 10;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 14;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ADDR_OFFSET = 9'h 18;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h 1c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h 20;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 24;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 28;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 2c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 30;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 34;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 38;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 3c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 40;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 44;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 48;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 4c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 50;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 54;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 58;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 5c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 60;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 64;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 68;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 6c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 70;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 74;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET = 9'h 78;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET = 9'h 7c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET = 9'h 80;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET = 9'h 84;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET = 9'h 88;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET = 9'h 8c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 90;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 94;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 98;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h 9c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET = 9'h a0;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET = 9'h a4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET = 9'h a8;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET = 9'h ac;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET = 9'h b0;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET = 9'h b4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET = 9'h b8;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET = 9'h bc;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET = 9'h c0;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET = 9'h c4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET = 9'h c8;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET = 9'h cc;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h d0;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h d4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h d8;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h dc;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET = 9'h e0;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET = 9'h e4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET = 9'h e8;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET = 9'h ec;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET = 9'h f0;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET = 9'h f4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h f8;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h fc;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h 100;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h 104;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET = 9'h 108;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET = 9'h 10c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET = 9'h 110;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET = 9'h 114;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET = 9'h 118;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET = 9'h 11c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET = 9'h 120;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET = 9'h 124;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET = 9'h 128;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET = 9'h 12c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET = 9'h 130;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET = 9'h 134;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h 138;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h 13c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 140;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 144;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_INTR_EN_OFFSET = 9'h 148;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 14c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 150;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 154;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 158;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 15c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_CNT_OFFSET = 9'h 160;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_ADDR_0_OFFSET = 9'h 164;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_ADDR_1_OFFSET = 9'h 168;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET = 9'h 16c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_OFFSET = 9'h 170;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 174;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 178;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 17c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 180;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 184;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_INIT_OFFSET = 9'h 10;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h 14;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 18;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ADDR_OFFSET = 9'h 1c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h 20;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h 24;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 28;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 2c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 30;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 34;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 38;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 3c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 40;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 44;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 48;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 4c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 50;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 54;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 58;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 5c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 60;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 64;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 68;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 6c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 70;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 74;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 78;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET = 9'h 7c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET = 9'h 80;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET = 9'h 84;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET = 9'h 88;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET = 9'h 8c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET = 9'h 90;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 94;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 98;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 9c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h a0;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET = 9'h a4;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET = 9'h a8;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET = 9'h ac;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET = 9'h b0;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET = 9'h b4;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET = 9'h b8;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET = 9'h bc;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET = 9'h c0;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET = 9'h c4;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET = 9'h c8;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET = 9'h cc;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET = 9'h d0;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h d4;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h d8;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h dc;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h e0;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET = 9'h e4;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET = 9'h e8;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET = 9'h ec;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET = 9'h f0;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET = 9'h f4;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET = 9'h f8;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h fc;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h 100;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h 104;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h 108;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET = 9'h 10c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET = 9'h 110;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET = 9'h 114;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET = 9'h 118;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET = 9'h 11c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET = 9'h 120;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET = 9'h 124;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET = 9'h 128;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET = 9'h 12c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET = 9'h 130;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET = 9'h 134;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET = 9'h 138;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h 13c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h 140;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 144;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 148;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_INTR_EN_OFFSET = 9'h 14c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 150;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 154;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 158;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 15c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 160;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_CNT_OFFSET = 9'h 164;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_ADDR_0_OFFSET = 9'h 168;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_ADDR_1_OFFSET = 9'h 16c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET = 9'h 170;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_OFFSET = 9'h 174;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 178;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 17c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 180;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 184;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 188;
 
   // Reset values for hwext registers and their fields for core interface
   parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h 0;
@@ -736,9 +742,9 @@
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
 
   // Window parameters for core interface
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 188;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 18c;
   parameter int unsigned       FLASH_CTRL_PROG_FIFO_SIZE   = 'h 4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 18c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 190;
   parameter int unsigned       FLASH_CTRL_RD_FIFO_SIZE   = 'h 4;
 
   // Register index for core interface
@@ -747,6 +753,7 @@
     FLASH_CTRL_INTR_ENABLE,
     FLASH_CTRL_INTR_TEST,
     FLASH_CTRL_ALERT_TEST,
+    FLASH_CTRL_INIT,
     FLASH_CTRL_CTRL_REGWEN,
     FLASH_CTRL_CONTROL,
     FLASH_CTRL_ADDR,
@@ -844,105 +851,106 @@
   } flash_ctrl_core_id_e;
 
   // Register width information to check illegal writes for core interface
-  parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [98] = '{
+  parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [99] = '{
     4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
     4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
     4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
     4'b 0001, // index[ 3] FLASH_CTRL_ALERT_TEST
-    4'b 0001, // index[ 4] FLASH_CTRL_CTRL_REGWEN
-    4'b 1111, // index[ 5] FLASH_CTRL_CONTROL
-    4'b 1111, // index[ 6] FLASH_CTRL_ADDR
-    4'b 0001, // index[ 7] FLASH_CTRL_PROG_TYPE_EN
-    4'b 0001, // index[ 8] FLASH_CTRL_ERASE_SUSPEND
-    4'b 0001, // index[ 9] FLASH_CTRL_REGION_CFG_REGWEN_0
-    4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_1
-    4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_2
-    4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_3
-    4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_4
-    4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_5
-    4'b 0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_6
-    4'b 0001, // index[16] FLASH_CTRL_REGION_CFG_REGWEN_7
-    4'b 1111, // index[17] FLASH_CTRL_MP_REGION_CFG_0
-    4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_1
-    4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_2
-    4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_3
-    4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_4
-    4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_5
-    4'b 1111, // index[23] FLASH_CTRL_MP_REGION_CFG_6
-    4'b 1111, // index[24] FLASH_CTRL_MP_REGION_CFG_7
-    4'b 0001, // index[25] FLASH_CTRL_DEFAULT_REGION
-    4'b 0001, // index[26] FLASH_CTRL_BANK0_INFO0_REGWEN_0
-    4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_REGWEN_1
-    4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_REGWEN_2
-    4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_REGWEN_3
-    4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_REGWEN_4
-    4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_REGWEN_5
-    4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO0_REGWEN_6
-    4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO0_REGWEN_7
-    4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO0_REGWEN_8
-    4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO0_REGWEN_9
-    4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
-    4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
-    4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
-    4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
-    4'b 0001, // index[40] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4
-    4'b 0001, // index[41] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5
-    4'b 0001, // index[42] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6
-    4'b 0001, // index[43] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7
-    4'b 0001, // index[44] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8
-    4'b 0001, // index[45] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9
-    4'b 0001, // index[46] FLASH_CTRL_BANK0_INFO1_REGWEN
-    4'b 0001, // index[47] FLASH_CTRL_BANK0_INFO1_PAGE_CFG
-    4'b 0001, // index[48] FLASH_CTRL_BANK0_INFO2_REGWEN_0
-    4'b 0001, // index[49] FLASH_CTRL_BANK0_INFO2_REGWEN_1
-    4'b 0001, // index[50] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0
-    4'b 0001, // index[51] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1
-    4'b 0001, // index[52] FLASH_CTRL_BANK1_INFO0_REGWEN_0
-    4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO0_REGWEN_1
-    4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO0_REGWEN_2
-    4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO0_REGWEN_3
-    4'b 0001, // index[56] FLASH_CTRL_BANK1_INFO0_REGWEN_4
-    4'b 0001, // index[57] FLASH_CTRL_BANK1_INFO0_REGWEN_5
-    4'b 0001, // index[58] FLASH_CTRL_BANK1_INFO0_REGWEN_6
-    4'b 0001, // index[59] FLASH_CTRL_BANK1_INFO0_REGWEN_7
-    4'b 0001, // index[60] FLASH_CTRL_BANK1_INFO0_REGWEN_8
-    4'b 0001, // index[61] FLASH_CTRL_BANK1_INFO0_REGWEN_9
-    4'b 0001, // index[62] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
-    4'b 0001, // index[63] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
-    4'b 0001, // index[64] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
-    4'b 0001, // index[65] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
-    4'b 0001, // index[66] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4
-    4'b 0001, // index[67] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5
-    4'b 0001, // index[68] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6
-    4'b 0001, // index[69] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7
-    4'b 0001, // index[70] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8
-    4'b 0001, // index[71] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9
-    4'b 0001, // index[72] FLASH_CTRL_BANK1_INFO1_REGWEN
-    4'b 0001, // index[73] FLASH_CTRL_BANK1_INFO1_PAGE_CFG
-    4'b 0001, // index[74] FLASH_CTRL_BANK1_INFO2_REGWEN_0
-    4'b 0001, // index[75] FLASH_CTRL_BANK1_INFO2_REGWEN_1
-    4'b 0001, // index[76] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0
-    4'b 0001, // index[77] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1
-    4'b 0001, // index[78] FLASH_CTRL_BANK_CFG_REGWEN
-    4'b 0001, // index[79] FLASH_CTRL_MP_BANK_CFG
-    4'b 0001, // index[80] FLASH_CTRL_OP_STATUS
-    4'b 0001, // index[81] FLASH_CTRL_STATUS
-    4'b 0001, // index[82] FLASH_CTRL_ERR_CODE_INTR_EN
-    4'b 0001, // index[83] FLASH_CTRL_ERR_CODE
-    4'b 0011, // index[84] FLASH_CTRL_ERR_ADDR
-    4'b 0001, // index[85] FLASH_CTRL_ECC_SINGLE_ERR_CNT
-    4'b 0111, // index[86] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
-    4'b 0111, // index[87] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
-    4'b 0001, // index[88] FLASH_CTRL_ECC_MULTI_ERR_CNT
-    4'b 0111, // index[89] FLASH_CTRL_ECC_MULTI_ERR_ADDR_0
-    4'b 0111, // index[90] FLASH_CTRL_ECC_MULTI_ERR_ADDR_1
-    4'b 0001, // index[91] FLASH_CTRL_PHY_ERR_CFG_REGWEN
-    4'b 0001, // index[92] FLASH_CTRL_PHY_ERR_CFG
-    4'b 0001, // index[93] FLASH_CTRL_PHY_ALERT_CFG
-    4'b 0001, // index[94] FLASH_CTRL_PHY_STATUS
-    4'b 1111, // index[95] FLASH_CTRL_SCRATCH
-    4'b 0011, // index[96] FLASH_CTRL_FIFO_LVL
-    4'b 0001  // index[97] FLASH_CTRL_FIFO_RST
+    4'b 0001, // index[ 4] FLASH_CTRL_INIT
+    4'b 0001, // index[ 5] FLASH_CTRL_CTRL_REGWEN
+    4'b 1111, // index[ 6] FLASH_CTRL_CONTROL
+    4'b 1111, // index[ 7] FLASH_CTRL_ADDR
+    4'b 0001, // index[ 8] FLASH_CTRL_PROG_TYPE_EN
+    4'b 0001, // index[ 9] FLASH_CTRL_ERASE_SUSPEND
+    4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_0
+    4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_1
+    4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_2
+    4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_3
+    4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_4
+    4'b 0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_5
+    4'b 0001, // index[16] FLASH_CTRL_REGION_CFG_REGWEN_6
+    4'b 0001, // index[17] FLASH_CTRL_REGION_CFG_REGWEN_7
+    4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_0
+    4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_1
+    4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_2
+    4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_3
+    4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_4
+    4'b 1111, // index[23] FLASH_CTRL_MP_REGION_CFG_5
+    4'b 1111, // index[24] FLASH_CTRL_MP_REGION_CFG_6
+    4'b 1111, // index[25] FLASH_CTRL_MP_REGION_CFG_7
+    4'b 0001, // index[26] FLASH_CTRL_DEFAULT_REGION
+    4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+    4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+    4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+    4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+    4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_REGWEN_4
+    4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO0_REGWEN_5
+    4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO0_REGWEN_6
+    4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO0_REGWEN_7
+    4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO0_REGWEN_8
+    4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO0_REGWEN_9
+    4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
+    4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
+    4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
+    4'b 0001, // index[40] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
+    4'b 0001, // index[41] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4
+    4'b 0001, // index[42] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5
+    4'b 0001, // index[43] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6
+    4'b 0001, // index[44] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7
+    4'b 0001, // index[45] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8
+    4'b 0001, // index[46] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9
+    4'b 0001, // index[47] FLASH_CTRL_BANK0_INFO1_REGWEN
+    4'b 0001, // index[48] FLASH_CTRL_BANK0_INFO1_PAGE_CFG
+    4'b 0001, // index[49] FLASH_CTRL_BANK0_INFO2_REGWEN_0
+    4'b 0001, // index[50] FLASH_CTRL_BANK0_INFO2_REGWEN_1
+    4'b 0001, // index[51] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0
+    4'b 0001, // index[52] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1
+    4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+    4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+    4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+    4'b 0001, // index[56] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+    4'b 0001, // index[57] FLASH_CTRL_BANK1_INFO0_REGWEN_4
+    4'b 0001, // index[58] FLASH_CTRL_BANK1_INFO0_REGWEN_5
+    4'b 0001, // index[59] FLASH_CTRL_BANK1_INFO0_REGWEN_6
+    4'b 0001, // index[60] FLASH_CTRL_BANK1_INFO0_REGWEN_7
+    4'b 0001, // index[61] FLASH_CTRL_BANK1_INFO0_REGWEN_8
+    4'b 0001, // index[62] FLASH_CTRL_BANK1_INFO0_REGWEN_9
+    4'b 0001, // index[63] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
+    4'b 0001, // index[64] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
+    4'b 0001, // index[65] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
+    4'b 0001, // index[66] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
+    4'b 0001, // index[67] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4
+    4'b 0001, // index[68] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5
+    4'b 0001, // index[69] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6
+    4'b 0001, // index[70] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7
+    4'b 0001, // index[71] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8
+    4'b 0001, // index[72] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9
+    4'b 0001, // index[73] FLASH_CTRL_BANK1_INFO1_REGWEN
+    4'b 0001, // index[74] FLASH_CTRL_BANK1_INFO1_PAGE_CFG
+    4'b 0001, // index[75] FLASH_CTRL_BANK1_INFO2_REGWEN_0
+    4'b 0001, // index[76] FLASH_CTRL_BANK1_INFO2_REGWEN_1
+    4'b 0001, // index[77] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0
+    4'b 0001, // index[78] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1
+    4'b 0001, // index[79] FLASH_CTRL_BANK_CFG_REGWEN
+    4'b 0001, // index[80] FLASH_CTRL_MP_BANK_CFG
+    4'b 0001, // index[81] FLASH_CTRL_OP_STATUS
+    4'b 0001, // index[82] FLASH_CTRL_STATUS
+    4'b 0001, // index[83] FLASH_CTRL_ERR_CODE_INTR_EN
+    4'b 0001, // index[84] FLASH_CTRL_ERR_CODE
+    4'b 0011, // index[85] FLASH_CTRL_ERR_ADDR
+    4'b 0001, // index[86] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+    4'b 0111, // index[87] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+    4'b 0111, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+    4'b 0001, // index[89] FLASH_CTRL_ECC_MULTI_ERR_CNT
+    4'b 0111, // index[90] FLASH_CTRL_ECC_MULTI_ERR_ADDR_0
+    4'b 0111, // index[91] FLASH_CTRL_ECC_MULTI_ERR_ADDR_1
+    4'b 0001, // index[92] FLASH_CTRL_PHY_ERR_CFG_REGWEN
+    4'b 0001, // index[93] FLASH_CTRL_PHY_ERR_CFG
+    4'b 0001, // index[94] FLASH_CTRL_PHY_ALERT_CFG
+    4'b 0001, // index[95] FLASH_CTRL_PHY_STATUS
+    4'b 1111, // index[96] FLASH_CTRL_SCRATCH
+    4'b 0011, // index[97] FLASH_CTRL_FIFO_LVL
+    4'b 0001  // index[98] FLASH_CTRL_FIFO_RST
   };
 
 endpackage