diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
index cd8fb8a..3689c36 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
@@ -30,8 +30,8 @@
   rand uint sram_host_byte_size;
   rand uint sram_device_byte_size;
 
-  rand uint tx_watermark_lvl;
-  rand uint rx_watermark_lvl;
+  rand bit [15:0] tx_watermark_lvl;
+  rand bit [15:0] rx_watermark_lvl;
 
   // core clk freq / spi clk freq is from 1/4 to 8. use below 2 var to represent the ratio
   // if spi_freq_faster,  core_spi_freq_ratio = spi clk freq / core clk freq (1:4)
diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_txrx_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_txrx_vseq.sv
index 972526d..028db86 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_txrx_vseq.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_txrx_vseq.sv
@@ -167,7 +167,8 @@
 
       // when fifo is empty, need to wait until fifo fetch data from sram before release semaphore
       if (allow_underflow_overflow) begin
-        cfg.clk_rst_vif.wait_clks(3);
+        // it takes 4 cycles to fetch data to async fifo
+        cfg.clk_rst_vif.wait_clks(4);
         tx_ptr_sema.put();
       end