diff --git a/hw/formal/README.md b/hw/formal/README.md
index aa79572..b773c66 100644
--- a/hw/formal/README.md
+++ b/hw/formal/README.md
@@ -207,6 +207,38 @@
 There are also powerful repetition operators, see
 [here](https://www.systemverilog.io/sva-basics) for more details.
 
+## Symbolic Variables
+
+When design has a set of modules or signals that share same properties,
+symbolic variables can be used to reduce duplicated assertions.
+For example, in the [rv_plic design](../ip/rv_plic/doc/rv_plic.md), the array of
+input `intr_src_i` are signals sharing same properties. Each
+`intr_src_i[index]` will trigger the interrupt pending (`ip`) signal depending
+on the corresponding level indicator (`le`) is set to level triggered or edge
+triggered.
+Without symbolic variables, the above assertions can be implemented as below:
+```systemverilog
+  genvar i;
+  generate for (i = 0; i < N_SOURCE; i++) begin : gen_rv_plic_fpv
+    `ASSERT(LevelTriggeredIp_A, $rose(rv_plic.ip[i]) |->
+            $past(rv_plic.le[i]) || $past(intr_src_i[i]), clk_i, !rst_ni)
+  end
+```
+
+In constrast, symbolic variable can abstract the design by declaring the index with
+constraints. To ensure the symbolic variable performs the expected behaviors,
+two assumptions need to be written:
+* Constraint the symoblic variable with the correct bound
+* Randomize the variable at the beginning of the simulation, then keep it stable
+  throughout the rest of the simulation
+```systemverilog
+  logic [$clog2(N_SOURCE)-1:0] src_sel;
+  `ASSUME_FPV(IsrcRange_M, src_sel >= 0 && src_sel < N_SOURCE, clk_i, !rst_ni)
+  `ASSUME_FPV(IsrcStable_M, ##1 $stable(src_sel), clk_i, !rst_ni)
+  `ASSERT(LevelTriggeredIp_A, $rose(rv_plic.ip[src_sel]) |->
+          $past(rv_plic.le[src_sel]) || $past(intr_src_i[src_sel]), clk_i, !rst_ni)
+```
+
 ## Coverpoints
 Coverpoints are used for properties and corner cases that the designer wants to
 make sure are being exercised by the testbench (e.g. FIFO-full checks). The
@@ -269,6 +301,15 @@
 ...
 ```
 
+## Naming Convenctions
+For assertions, it is preferred to use postfix `_A`, while for assumptions, use
+`_M`. For example:
+```systemverilog
+  `ASSUME_FPV(IsrcRange_M, src_sel >= 0 && src_sel < N_SOURCE, clk_i, !rst_ni)
+  `ASSERT(LevelTriggeredIp_A, $rose(rv_plic.ip[src_sel]) |->
+          $past(rv_plic.le[src_sel]) || $past(intr_src_i[src_sel]), clk_i, !rst_ni)
+```
+
 ## References
 *   [SVA Basics](https://www.systemverilog.io/sva-basics)
 *   [SVA Tutorial](https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/)
diff --git a/hw/ip/rv_plic/data/rv_plic_fpv_testplan.hjson b/hw/ip/rv_plic/data/rv_plic_fpv_testplan.hjson
new file mode 100644
index 0000000..82f0537
--- /dev/null
+++ b/hw/ip/rv_plic/data/rv_plic_fpv_testplan.hjson
@@ -0,0 +1,84 @@
+{
+  name: "rv_plic"
+  entries: [
+    {
+      name: LevelTriggeredIp_A
+      desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to
+            level triggered (`le=0`), then in the prvious clock cycle, the interrupt source
+            (`intr_src_i) should be set to 1.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: EdgeTriggeredIp_A
+      desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to
+            edge triggered (`le=1`), then in the prvious clock cycle, the interrupt source
+            (`intr_src_i) should be at the rising edge.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: LevelTriggeredIpWithClaim_A
+      desc: '''If `intr_src_i` is set to 1, level indicator is set to level triggered, and claim
+            signal is not set, then at the next clock cycle `ip` will be triggered.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: EdgeTriggeredIpWithClaim_A
+      desc: '''If `intr_src_i` is at the rising edge, level indicator is set to edge triggered, and claim
+            signal is not set, then at the next clock cycle `ip` will be triggered.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: IpStableAfterTriggered_A
+      desc: "Once `ip` is set, it stays stable until is being claimed."
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: IpClearAfterClaim_A
+      desc: "Once `ip` is set and being claimed, its value is cleared to 0."
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: IpStableAfterClaimed_A
+      desc: '''Once `ip` is cleared to 0, it stays stable until completed and being triggered
+            again.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: TriggerIrqForwardCheck_A
+      desc: '''If interrupt is enabled (`ie=1`), interrupt pending is set (`ip=1`), interrupt
+            input has the highest priority among the rest of the inputs, and its priority is
+            above the threshold. Then in the next clock clcye, the `irq_o` should be triggered,
+            and the `irq_id_o` will reflect the input ID.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+    {
+      name: TriggerIrqBackwardCheck_A
+      desc: '''If `irq_o` is set to 1, then in the previous clock cycle, the corresponding
+            `ip` should be set, `ie` should be enabled, and the interrupt source should above the
+            threshold and have the highest priority.'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+
+    }
+    {
+      name: IdChangeWithIrq_A
+      desc: '''If `irq_id_o` signal is changed and the signal does not change to 0 (value 0 does
+               not represent any interrupt source ID). Then either of the two condition should have
+               happened:
+               - `irq_o` is triggered
+               - No interrupt triggered, `ip` is set and `ie` is enabled, interrupt source priority is the
+                 largest among the rest of the interrupt, but the interrupt source
+                 priority is smaller than the threshold'''
+      milestone: V2
+      tests: ["rv_plic_assert"]
+    }
+  ]
+}
diff --git a/hw/ip/rv_plic/doc/fpv.svg b/hw/ip/rv_plic/doc/fpv.svg
new file mode 100644
index 0000000..8b27543
--- /dev/null
+++ b/hw/ip/rv_plic/doc/fpv.svg
@@ -0,0 +1 @@
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diff --git a/hw/ip/rv_plic/doc/rv_plic_fpv_plan.md b/hw/ip/rv_plic/doc/rv_plic_fpv_plan.md
new file mode 100644
index 0000000..08b386b
--- /dev/null
+++ b/hw/ip/rv_plic/doc/rv_plic_fpv_plan.md
@@ -0,0 +1,47 @@
+{{% lowrisc-doc-hdr RV_PLIC FPV Plan }}
+{{% import_testplan ../data/rv_plic_fpv_testplan.hjson }}
+
+{{% toc 4 }}
+
+## Goals
+* Verify all the RV_PLIC outputs by writing assumptions and assertions with a
+  FPV based testbench
+* Verify TileLink device protocol compliance with a FPV based testbench
+
+## Current status
+* [Design & verification stage](../../../../doc/project/hw_dashboard.md)
+  * [HW development stages](../../../../doc/ug/hw_stages.md)
+* FPV dashboard (link TBD)
+
+## Design features
+For detailed information on RV_PLIC design features, please see the
+[RV_PLIC design specification](rv_plic.md).
+
+## Testbench architecture
+RV_PLIC FPV testbench has been constructed based on the [formal
+architecture](../../../formal/README.md)
+
+### Block diagram
+![Block diagram](fpv.svg)
+
+#### TLUL assertions
+* The `../fpv/tb/rv_plic_bind.sv` binds the `tlul_assert` [assertions](../../tlul/doc/TlulProtocolChecker.md)
+  to rv_plic to ensure TileLink interface protocol compliance
+* TODO: Plan to implement csr assertions under `../fpv/vip/` to assert the
+  TileLink writes and reads correct CSRs
+
+#### RV_PLIC assertions
+The `../fpv/tb/rv_plic_bind.sv` binds the `rv_plic_assert` under
+`../fpv/vip/rv_plic_assert.sv`. The assertion file ensures RV_PLIC's outputs
+(`irq_o` and `irq_id_o`) and important signals (`ip`) are being asserted.
+
+##### Symbolic variables
+Due to there are large number of input interrupt sources, the symbolic variable
+is used to reduce the number of repeated assertions code. In RV_PLIC, we
+declared two symbolic variables `src_sel` and `tgt_sel` to represent the index for
+interrupt source and interrupt target.
+Detailed explanation is listed in the
+[Symbolic Variables](../../../formal/README.md#symbolic-variables) section.
+
+## Testplan
+{{% insert_testplan x }}
diff --git a/hw/ip/rv_plic/fpv/vip/rv_plic_assert.sv b/hw/ip/rv_plic/fpv/vip/rv_plic_assert.sv
index 899f495..a8590ec 100644
--- a/hw/ip/rv_plic/fpv/vip/rv_plic_assert.sv
+++ b/hw/ip/rv_plic/fpv/vip/rv_plic_assert.sv
@@ -24,33 +24,33 @@
   logic [SRCW-1:0] i_high_prio;
 
   // symbolic variables
-  int unsigned i_src;
-  int unsigned i_tgt;
+  int unsigned src_sel;
+  int unsigned tgt_sel;
 
-  `ASSUME_FPV(IsrcRange_M, i_src >= 0 && i_src < N_SOURCE, clk_i, !rst_ni)
-  `ASSUME_FPV(ItgtRange_M, i_tgt >= 0 && i_tgt < N_TARGET, clk_i, !rst_ni)
-  `ASSUME_FPV(IsrcStable_M, ##1 $stable(i_src), clk_i, !rst_ni)
-  `ASSUME_FPV(ItgtStable_M, ##1 $stable(i_tgt), clk_i, !rst_ni)
+  `ASSUME_FPV(IsrcRange_M, src_sel >= 0 && src_sel < N_SOURCE, clk_i, !rst_ni)
+  `ASSUME_FPV(ItgtRange_M, tgt_sel >= 0 && tgt_sel < N_TARGET, clk_i, !rst_ni)
+  `ASSUME_FPV(IsrcStable_M, ##1 $stable(src_sel), clk_i, !rst_ni)
+  `ASSUME_FPV(ItgtStable_M, ##1 $stable(tgt_sel), clk_i, !rst_ni)
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       claim <= 1'b0;
-    end else if (rv_plic.claim[i_src]) begin
+    end else if (rv_plic.claim[src_sel]) begin
       claim <= 1'b1;
-    end else if (rv_plic.complete[i_src]) begin
+    end else if (rv_plic.complete[src_sel]) begin
       claim <= 1'b0;
     end
   end
 
-  assign claimed = claim || rv_plic.claim[i_src];
+  assign claimed = claim || rv_plic.claim[src_sel];
 
   always_comb begin
     max_priority = 1'b1;
     for (int i = 0; i < N_SOURCE; i++) begin
-      // conditions that if i_src has the highest priority with the lowest ID
-      if (i != i_src && rv_plic.ip[i] && rv_plic.ie[i_tgt][i] &&
-          (rv_plic.prio[i] > rv_plic.prio[i_src] ||
-           (rv_plic.prio[i] == rv_plic.prio[i_src] && i < i_src))) begin
+      // conditions that if src_sel has the highest priority with the lowest ID
+      if (i != src_sel && rv_plic.ip[i] && rv_plic.ie[tgt_sel][i] &&
+          (rv_plic.prio[i] > rv_plic.prio[src_sel] ||
+           (rv_plic.prio[i] == rv_plic.prio[src_sel] && i < src_sel))) begin
         max_priority = 1'b0;
         break;
       end
@@ -60,48 +60,48 @@
   always_comb begin
     automatic logic [31:0] max_prio = 0;
     for (int i = N_SOURCE-1; i >= 0; i--) begin
-      if (rv_plic.ip[i] && rv_plic.ie[i_tgt][i] && rv_plic.prio[i] >= max_prio) begin
+      if (rv_plic.ip[i] && rv_plic.ie[tgt_sel][i] && rv_plic.prio[i] >= max_prio) begin
         max_prio = rv_plic.prio[i];
         i_high_prio = i; // i is the smallest id if have IPs with the same priority
       end
     end
-    if (max_prio > rv_plic.threshold[i_tgt]) irq = 1'b1;
+    if (max_prio > rv_plic.threshold[tgt_sel]) irq = 1'b1;
     else irq = 1'b0;
   end
 
   // when IP is set, previous cycle should follow edge or level triggered criteria
-  `ASSERT(LevelTriggeredIp_A, $rose(rv_plic.ip[i_src]) |->
-          $past(rv_plic.le[i_src]) || $past(intr_src_i[i_src]), clk_i, !rst_ni)
+  `ASSERT(LevelTriggeredIp_A, $rose(rv_plic.ip[src_sel]) |->
+          $past(rv_plic.le[src_sel]) || $past(intr_src_i[src_sel]), clk_i, !rst_ni)
 
-  `ASSERT(EdgeTriggeredIp_A, $rose(rv_plic.ip[i_src]) |->
-          !$past(rv_plic.le[i_src]) || $rose($past(intr_src_i[i_src])), clk_i, !rst_ni)
+  `ASSERT(EdgeTriggeredIp_A, $rose(rv_plic.ip[src_sel]) |->
+          !$past(rv_plic.le[src_sel]) || $rose($past(intr_src_i[src_sel])), clk_i, !rst_ni)
 
   // when interrupt is trigger, and nothing claimed yet, then next cycle should assert IP.
-  `ASSERT(LevelTriggeredIpWithClaim_A, !rv_plic.le[i_src] && intr_src_i[i_src] && !claimed |=>
-          rv_plic.ip[i_src], clk_i, !rst_ni)
+  `ASSERT(LevelTriggeredIpWithClaim_A, !rv_plic.le[src_sel] && intr_src_i[src_sel] && !claimed |=>
+          rv_plic.ip[src_sel], clk_i, !rst_ni)
 
-  `ASSERT(EdgeTriggeredIpWithClaim_A, rv_plic.le[i_src] && $rose(intr_src_i[i_src]) && !claimed |=>
-          rv_plic.ip[i_src], clk_i, !rst_ni)
+  `ASSERT(EdgeTriggeredIpWithClaim_A, rv_plic.le[src_sel] && $rose(intr_src_i[src_sel]) && !claimed |=>
+          rv_plic.ip[src_sel], clk_i, !rst_ni)
 
   // ip stays stable until claimed, reset to 0 after claimed, and stays 0 until complete
-  `ASSERT(IpStableAfterTriggered_A, rv_plic.ip[i_src] && !claimed |=>
-          rv_plic.ip[i_src], clk_i, !rst_ni)
-  `ASSERT(IpClearAfterClaim_A, rv_plic.ip[i_src] && rv_plic.claim[i_src] |=>
-          !rv_plic.ip[i_src], clk_i, !rst_ni)
-  `ASSERT(IpStableAfterClaimed_A, claimed |=> !rv_plic.ip[i_src], clk_i, !rst_ni)
+  `ASSERT(IpStableAfterTriggered_A, rv_plic.ip[src_sel] && !claimed |=>
+          rv_plic.ip[src_sel], clk_i, !rst_ni)
+  `ASSERT(IpClearAfterClaim_A, rv_plic.ip[src_sel] && rv_plic.claim[src_sel] |=>
+          !rv_plic.ip[src_sel], clk_i, !rst_ni)
+  `ASSERT(IpStableAfterClaimed_A, claimed |=> !rv_plic.ip[src_sel], clk_i, !rst_ni)
 
   // when ip is set and priority is the largest and above threshold, and interrupt enable is set,
   // assertion irq_o at next cycle
-  `ASSERT(TriggerIrqForwardCheck_A, rv_plic.ip[i_src] &&
-          rv_plic.prio[i_src] > rv_plic.threshold[i_tgt] &&
-          max_priority && rv_plic.ie[i_tgt][i_src] |=> irq_o[i_tgt], clk_i, !rst_ni)
+  `ASSERT(TriggerIrqForwardCheck_A, rv_plic.ip[src_sel] &&
+          rv_plic.prio[src_sel] > rv_plic.threshold[tgt_sel] &&
+          max_priority && rv_plic.ie[tgt_sel][src_sel] |=> irq_o[tgt_sel], clk_i, !rst_ni)
 
-  `ASSERT(TriggerIrqBackwardCheck_A, $rose(irq_o[i_tgt]) |->
-          $past(irq) && (irq_id_o[i_tgt] - 1) == $past(i_high_prio), clk_i, !rst_ni)
+  `ASSERT(TriggerIrqBackwardCheck_A, $rose(irq_o[tgt_sel]) |->
+          $past(irq) && (irq_id_o[tgt_sel] - 1) == $past(i_high_prio), clk_i, !rst_ni)
 
   // when irq ID changed, but not to ID=0, irq_o should be high, or irq represents the largest prio
   // but smaller than the threshold
-  `ASSERT(IdChangeWithIrq_A, !$stable(irq_id_o[i_tgt]) && irq_id_o[i_tgt] != 0 |->
-          irq_o[i_tgt] || ((irq_id_o[i_tgt] - 1) == $past(i_high_prio) && !$past(irq)),
+  `ASSERT(IdChangeWithIrq_A, !$stable(irq_id_o[tgt_sel]) && irq_id_o[tgt_sel] != 0 |->
+          irq_o[tgt_sel] || ((irq_id_o[tgt_sel] - 1) == $past(i_high_prio) && !$past(irq)),
           clk_i, !rst_ni)
 endmodule