)]}'
{
  "commit": "6b02a011b1cfb57a74dfb90e57952aa33a970a11",
  "tree": "dfaed8c674870ba0bfe00e95b923cdcee2aaa05b",
  "parents": [
    "4f0b0905b461b9673f35657073b42cffd1e06a7d"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Mon Jan 27 17:23:45 2020 -0800"
  },
  "committer": {
    "name": "sriyerg",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Tue Jan 28 12:49:01 2020 -0800"
  },
  "message": "[dv] fusesoc with export + Chip sims with dvsim\n\nFusesoc updates:\n- This PR updates the fusesoc invoked within DV to export the sources to\nthe build area.\n- This is done to enable the tool to use GCP resources for sim deployment (or LSF)\n\nChip top sim updates:\n- This PR also updates the chip level to use the DVSIM regression flow.\nIt adds a chip testplan and the sim cfg hjson file to enable it.\n\nDVSIM Script updates:\n- This regression script has a minor update to enable top_earlgrey sims\nusing the dvsim flow.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
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