hw/ip/spi_host/dv/spi_host_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: spi_host

  // Top level dut name (sv module).
  dut: spi_host

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: xcelium

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:spi_host_sim:1.0

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/spi_host/data/spi_host_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/spi_host/data/spi_host.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                // TODO: comment out for V2
                //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["spi_host_bind", "sec_cm_prim_onehot_check_bind"]

  // Coverage exclusion
  xcelium_cov_refine_files: ["{proj_root}/hw/ip/spi_host/dv/cov/spi_host_unr_excl.vRefine"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: spi_host_base_test
  uvm_test_seq: spi_host_base_vseq

  component_a: "uvm_test_top.env.scoreboard"
  id_a: _ALL_
  verbosity_a: UVM_MEDIUM
  phase_a: run

  run_modes: [
    {
      name: set_verbosity_comp_a_uvm_debug
      run_opts: ["+uvm_set_verbosity={component_a},{id_a},{verbosity_a},{phase_a}"]
    }
  ]

  run_opts: ["+uvm_set_verbosity={component_a},{id_a},{verbosity_a},{phase_a}",
             "+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: spi_host_smoke
      uvm_test_seq: spi_host_smoke_vseq
    }
    {
      name: spi_host_speed
      uvm_test_seq: spi_host_speed_vseq
    }
    {
      name: spi_host_performance
      uvm_test_seq: spi_host_performance_vseq
    }
    {
      name: spi_host_sw_reset
      uvm_test_seq: spi_host_sw_reset_vseq
      run_opts: ["+test_timeout_ns=1_000_000_000"]
    }
    {
      name: spi_host_overflow_underflow
      uvm_test_seq: spi_host_overflow_underflow_vseq
      run_opts: ["+en_scb=0"]
    }
    {
      name: spi_host_error_cmd
      uvm_test_seq: spi_host_error_cmd_vseq
      run_opts: ["+en_scb=0"]
    }
    {
      name: spi_host_event
      uvm_test_seq: spi_host_event_vseq
      run_opts: ["+en_scb=0", "+test_timeout_ns=1_000_000_000"]
    }
    {
      name: spi_host_passthrough_mode
      uvm_test_seq: spi_host_passthrough_mode_vseq
      run_opts: ["+en_scb=0"]
    }
    {
      name: spi_host_status_stall
      uvm_test_seq: spi_host_status_stall_vseq
      run_opts: ["+test_timeout_ns=1_00_000_000"]
    }
    {
      name: spi_host_idlecsbactive
      uvm_test_seq: spi_host_idlecsbactive_vseq
    }
    {
      name: spi_host_stress_all
      uvm_test_seq: spi_host_stress_all_vseq
      run_opts: ["+test_timeout_ns=1_000_000_000"]
    }
    {
      name: spi_host_spien
      uvm_test_seq: spi_host_spien_vseq
    }
    // TODO: add more tests here
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["spi_host_smoke"]
    }
  ]
}