| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module pinmux_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input clk_aon_i, |
| input rst_aon_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| // To HW |
| output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write |
| input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import pinmux_reg_pkg::* ; |
| |
| localparam int AW = 11; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [413:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(414) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(1) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| assign tl_reg_h2d = tl_i; |
| assign tl_o_pre = tl_reg_d2h; |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(0) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic alert_test_we; |
| logic alert_test_wd; |
| logic mio_periph_insel_regwen_0_we; |
| logic mio_periph_insel_regwen_0_qs; |
| logic mio_periph_insel_regwen_0_wd; |
| logic mio_periph_insel_regwen_1_we; |
| logic mio_periph_insel_regwen_1_qs; |
| logic mio_periph_insel_regwen_1_wd; |
| logic mio_periph_insel_regwen_2_we; |
| logic mio_periph_insel_regwen_2_qs; |
| logic mio_periph_insel_regwen_2_wd; |
| logic mio_periph_insel_regwen_3_we; |
| logic mio_periph_insel_regwen_3_qs; |
| logic mio_periph_insel_regwen_3_wd; |
| logic mio_periph_insel_regwen_4_we; |
| logic mio_periph_insel_regwen_4_qs; |
| logic mio_periph_insel_regwen_4_wd; |
| logic mio_periph_insel_regwen_5_we; |
| logic mio_periph_insel_regwen_5_qs; |
| logic mio_periph_insel_regwen_5_wd; |
| logic mio_periph_insel_regwen_6_we; |
| logic mio_periph_insel_regwen_6_qs; |
| logic mio_periph_insel_regwen_6_wd; |
| logic mio_periph_insel_regwen_7_we; |
| logic mio_periph_insel_regwen_7_qs; |
| logic mio_periph_insel_regwen_7_wd; |
| logic mio_periph_insel_regwen_8_we; |
| logic mio_periph_insel_regwen_8_qs; |
| logic mio_periph_insel_regwen_8_wd; |
| logic mio_periph_insel_regwen_9_we; |
| logic mio_periph_insel_regwen_9_qs; |
| logic mio_periph_insel_regwen_9_wd; |
| logic mio_periph_insel_regwen_10_we; |
| logic mio_periph_insel_regwen_10_qs; |
| logic mio_periph_insel_regwen_10_wd; |
| logic mio_periph_insel_regwen_11_we; |
| logic mio_periph_insel_regwen_11_qs; |
| logic mio_periph_insel_regwen_11_wd; |
| logic mio_periph_insel_regwen_12_we; |
| logic mio_periph_insel_regwen_12_qs; |
| logic mio_periph_insel_regwen_12_wd; |
| logic mio_periph_insel_regwen_13_we; |
| logic mio_periph_insel_regwen_13_qs; |
| logic mio_periph_insel_regwen_13_wd; |
| logic mio_periph_insel_regwen_14_we; |
| logic mio_periph_insel_regwen_14_qs; |
| logic mio_periph_insel_regwen_14_wd; |
| logic mio_periph_insel_regwen_15_we; |
| logic mio_periph_insel_regwen_15_qs; |
| logic mio_periph_insel_regwen_15_wd; |
| logic mio_periph_insel_regwen_16_we; |
| logic mio_periph_insel_regwen_16_qs; |
| logic mio_periph_insel_regwen_16_wd; |
| logic mio_periph_insel_regwen_17_we; |
| logic mio_periph_insel_regwen_17_qs; |
| logic mio_periph_insel_regwen_17_wd; |
| logic mio_periph_insel_regwen_18_we; |
| logic mio_periph_insel_regwen_18_qs; |
| logic mio_periph_insel_regwen_18_wd; |
| logic mio_periph_insel_regwen_19_we; |
| logic mio_periph_insel_regwen_19_qs; |
| logic mio_periph_insel_regwen_19_wd; |
| logic mio_periph_insel_regwen_20_we; |
| logic mio_periph_insel_regwen_20_qs; |
| logic mio_periph_insel_regwen_20_wd; |
| logic mio_periph_insel_regwen_21_we; |
| logic mio_periph_insel_regwen_21_qs; |
| logic mio_periph_insel_regwen_21_wd; |
| logic mio_periph_insel_regwen_22_we; |
| logic mio_periph_insel_regwen_22_qs; |
| logic mio_periph_insel_regwen_22_wd; |
| logic mio_periph_insel_regwen_23_we; |
| logic mio_periph_insel_regwen_23_qs; |
| logic mio_periph_insel_regwen_23_wd; |
| logic mio_periph_insel_regwen_24_we; |
| logic mio_periph_insel_regwen_24_qs; |
| logic mio_periph_insel_regwen_24_wd; |
| logic mio_periph_insel_regwen_25_we; |
| logic mio_periph_insel_regwen_25_qs; |
| logic mio_periph_insel_regwen_25_wd; |
| logic mio_periph_insel_regwen_26_we; |
| logic mio_periph_insel_regwen_26_qs; |
| logic mio_periph_insel_regwen_26_wd; |
| logic mio_periph_insel_regwen_27_we; |
| logic mio_periph_insel_regwen_27_qs; |
| logic mio_periph_insel_regwen_27_wd; |
| logic mio_periph_insel_regwen_28_we; |
| logic mio_periph_insel_regwen_28_qs; |
| logic mio_periph_insel_regwen_28_wd; |
| logic mio_periph_insel_regwen_29_we; |
| logic mio_periph_insel_regwen_29_qs; |
| logic mio_periph_insel_regwen_29_wd; |
| logic mio_periph_insel_regwen_30_we; |
| logic mio_periph_insel_regwen_30_qs; |
| logic mio_periph_insel_regwen_30_wd; |
| logic mio_periph_insel_regwen_31_we; |
| logic mio_periph_insel_regwen_31_qs; |
| logic mio_periph_insel_regwen_31_wd; |
| logic mio_periph_insel_regwen_32_we; |
| logic mio_periph_insel_regwen_32_qs; |
| logic mio_periph_insel_regwen_32_wd; |
| logic mio_periph_insel_0_we; |
| logic [5:0] mio_periph_insel_0_qs; |
| logic [5:0] mio_periph_insel_0_wd; |
| logic mio_periph_insel_1_we; |
| logic [5:0] mio_periph_insel_1_qs; |
| logic [5:0] mio_periph_insel_1_wd; |
| logic mio_periph_insel_2_we; |
| logic [5:0] mio_periph_insel_2_qs; |
| logic [5:0] mio_periph_insel_2_wd; |
| logic mio_periph_insel_3_we; |
| logic [5:0] mio_periph_insel_3_qs; |
| logic [5:0] mio_periph_insel_3_wd; |
| logic mio_periph_insel_4_we; |
| logic [5:0] mio_periph_insel_4_qs; |
| logic [5:0] mio_periph_insel_4_wd; |
| logic mio_periph_insel_5_we; |
| logic [5:0] mio_periph_insel_5_qs; |
| logic [5:0] mio_periph_insel_5_wd; |
| logic mio_periph_insel_6_we; |
| logic [5:0] mio_periph_insel_6_qs; |
| logic [5:0] mio_periph_insel_6_wd; |
| logic mio_periph_insel_7_we; |
| logic [5:0] mio_periph_insel_7_qs; |
| logic [5:0] mio_periph_insel_7_wd; |
| logic mio_periph_insel_8_we; |
| logic [5:0] mio_periph_insel_8_qs; |
| logic [5:0] mio_periph_insel_8_wd; |
| logic mio_periph_insel_9_we; |
| logic [5:0] mio_periph_insel_9_qs; |
| logic [5:0] mio_periph_insel_9_wd; |
| logic mio_periph_insel_10_we; |
| logic [5:0] mio_periph_insel_10_qs; |
| logic [5:0] mio_periph_insel_10_wd; |
| logic mio_periph_insel_11_we; |
| logic [5:0] mio_periph_insel_11_qs; |
| logic [5:0] mio_periph_insel_11_wd; |
| logic mio_periph_insel_12_we; |
| logic [5:0] mio_periph_insel_12_qs; |
| logic [5:0] mio_periph_insel_12_wd; |
| logic mio_periph_insel_13_we; |
| logic [5:0] mio_periph_insel_13_qs; |
| logic [5:0] mio_periph_insel_13_wd; |
| logic mio_periph_insel_14_we; |
| logic [5:0] mio_periph_insel_14_qs; |
| logic [5:0] mio_periph_insel_14_wd; |
| logic mio_periph_insel_15_we; |
| logic [5:0] mio_periph_insel_15_qs; |
| logic [5:0] mio_periph_insel_15_wd; |
| logic mio_periph_insel_16_we; |
| logic [5:0] mio_periph_insel_16_qs; |
| logic [5:0] mio_periph_insel_16_wd; |
| logic mio_periph_insel_17_we; |
| logic [5:0] mio_periph_insel_17_qs; |
| logic [5:0] mio_periph_insel_17_wd; |
| logic mio_periph_insel_18_we; |
| logic [5:0] mio_periph_insel_18_qs; |
| logic [5:0] mio_periph_insel_18_wd; |
| logic mio_periph_insel_19_we; |
| logic [5:0] mio_periph_insel_19_qs; |
| logic [5:0] mio_periph_insel_19_wd; |
| logic mio_periph_insel_20_we; |
| logic [5:0] mio_periph_insel_20_qs; |
| logic [5:0] mio_periph_insel_20_wd; |
| logic mio_periph_insel_21_we; |
| logic [5:0] mio_periph_insel_21_qs; |
| logic [5:0] mio_periph_insel_21_wd; |
| logic mio_periph_insel_22_we; |
| logic [5:0] mio_periph_insel_22_qs; |
| logic [5:0] mio_periph_insel_22_wd; |
| logic mio_periph_insel_23_we; |
| logic [5:0] mio_periph_insel_23_qs; |
| logic [5:0] mio_periph_insel_23_wd; |
| logic mio_periph_insel_24_we; |
| logic [5:0] mio_periph_insel_24_qs; |
| logic [5:0] mio_periph_insel_24_wd; |
| logic mio_periph_insel_25_we; |
| logic [5:0] mio_periph_insel_25_qs; |
| logic [5:0] mio_periph_insel_25_wd; |
| logic mio_periph_insel_26_we; |
| logic [5:0] mio_periph_insel_26_qs; |
| logic [5:0] mio_periph_insel_26_wd; |
| logic mio_periph_insel_27_we; |
| logic [5:0] mio_periph_insel_27_qs; |
| logic [5:0] mio_periph_insel_27_wd; |
| logic mio_periph_insel_28_we; |
| logic [5:0] mio_periph_insel_28_qs; |
| logic [5:0] mio_periph_insel_28_wd; |
| logic mio_periph_insel_29_we; |
| logic [5:0] mio_periph_insel_29_qs; |
| logic [5:0] mio_periph_insel_29_wd; |
| logic mio_periph_insel_30_we; |
| logic [5:0] mio_periph_insel_30_qs; |
| logic [5:0] mio_periph_insel_30_wd; |
| logic mio_periph_insel_31_we; |
| logic [5:0] mio_periph_insel_31_qs; |
| logic [5:0] mio_periph_insel_31_wd; |
| logic mio_periph_insel_32_we; |
| logic [5:0] mio_periph_insel_32_qs; |
| logic [5:0] mio_periph_insel_32_wd; |
| logic mio_outsel_regwen_0_we; |
| logic mio_outsel_regwen_0_qs; |
| logic mio_outsel_regwen_0_wd; |
| logic mio_outsel_regwen_1_we; |
| logic mio_outsel_regwen_1_qs; |
| logic mio_outsel_regwen_1_wd; |
| logic mio_outsel_regwen_2_we; |
| logic mio_outsel_regwen_2_qs; |
| logic mio_outsel_regwen_2_wd; |
| logic mio_outsel_regwen_3_we; |
| logic mio_outsel_regwen_3_qs; |
| logic mio_outsel_regwen_3_wd; |
| logic mio_outsel_regwen_4_we; |
| logic mio_outsel_regwen_4_qs; |
| logic mio_outsel_regwen_4_wd; |
| logic mio_outsel_regwen_5_we; |
| logic mio_outsel_regwen_5_qs; |
| logic mio_outsel_regwen_5_wd; |
| logic mio_outsel_regwen_6_we; |
| logic mio_outsel_regwen_6_qs; |
| logic mio_outsel_regwen_6_wd; |
| logic mio_outsel_regwen_7_we; |
| logic mio_outsel_regwen_7_qs; |
| logic mio_outsel_regwen_7_wd; |
| logic mio_outsel_regwen_8_we; |
| logic mio_outsel_regwen_8_qs; |
| logic mio_outsel_regwen_8_wd; |
| logic mio_outsel_regwen_9_we; |
| logic mio_outsel_regwen_9_qs; |
| logic mio_outsel_regwen_9_wd; |
| logic mio_outsel_regwen_10_we; |
| logic mio_outsel_regwen_10_qs; |
| logic mio_outsel_regwen_10_wd; |
| logic mio_outsel_regwen_11_we; |
| logic mio_outsel_regwen_11_qs; |
| logic mio_outsel_regwen_11_wd; |
| logic mio_outsel_regwen_12_we; |
| logic mio_outsel_regwen_12_qs; |
| logic mio_outsel_regwen_12_wd; |
| logic mio_outsel_regwen_13_we; |
| logic mio_outsel_regwen_13_qs; |
| logic mio_outsel_regwen_13_wd; |
| logic mio_outsel_regwen_14_we; |
| logic mio_outsel_regwen_14_qs; |
| logic mio_outsel_regwen_14_wd; |
| logic mio_outsel_regwen_15_we; |
| logic mio_outsel_regwen_15_qs; |
| logic mio_outsel_regwen_15_wd; |
| logic mio_outsel_regwen_16_we; |
| logic mio_outsel_regwen_16_qs; |
| logic mio_outsel_regwen_16_wd; |
| logic mio_outsel_regwen_17_we; |
| logic mio_outsel_regwen_17_qs; |
| logic mio_outsel_regwen_17_wd; |
| logic mio_outsel_regwen_18_we; |
| logic mio_outsel_regwen_18_qs; |
| logic mio_outsel_regwen_18_wd; |
| logic mio_outsel_regwen_19_we; |
| logic mio_outsel_regwen_19_qs; |
| logic mio_outsel_regwen_19_wd; |
| logic mio_outsel_regwen_20_we; |
| logic mio_outsel_regwen_20_qs; |
| logic mio_outsel_regwen_20_wd; |
| logic mio_outsel_regwen_21_we; |
| logic mio_outsel_regwen_21_qs; |
| logic mio_outsel_regwen_21_wd; |
| logic mio_outsel_regwen_22_we; |
| logic mio_outsel_regwen_22_qs; |
| logic mio_outsel_regwen_22_wd; |
| logic mio_outsel_regwen_23_we; |
| logic mio_outsel_regwen_23_qs; |
| logic mio_outsel_regwen_23_wd; |
| logic mio_outsel_regwen_24_we; |
| logic mio_outsel_regwen_24_qs; |
| logic mio_outsel_regwen_24_wd; |
| logic mio_outsel_regwen_25_we; |
| logic mio_outsel_regwen_25_qs; |
| logic mio_outsel_regwen_25_wd; |
| logic mio_outsel_regwen_26_we; |
| logic mio_outsel_regwen_26_qs; |
| logic mio_outsel_regwen_26_wd; |
| logic mio_outsel_regwen_27_we; |
| logic mio_outsel_regwen_27_qs; |
| logic mio_outsel_regwen_27_wd; |
| logic mio_outsel_regwen_28_we; |
| logic mio_outsel_regwen_28_qs; |
| logic mio_outsel_regwen_28_wd; |
| logic mio_outsel_regwen_29_we; |
| logic mio_outsel_regwen_29_qs; |
| logic mio_outsel_regwen_29_wd; |
| logic mio_outsel_regwen_30_we; |
| logic mio_outsel_regwen_30_qs; |
| logic mio_outsel_regwen_30_wd; |
| logic mio_outsel_regwen_31_we; |
| logic mio_outsel_regwen_31_qs; |
| logic mio_outsel_regwen_31_wd; |
| logic mio_outsel_0_we; |
| logic [5:0] mio_outsel_0_qs; |
| logic [5:0] mio_outsel_0_wd; |
| logic mio_outsel_1_we; |
| logic [5:0] mio_outsel_1_qs; |
| logic [5:0] mio_outsel_1_wd; |
| logic mio_outsel_2_we; |
| logic [5:0] mio_outsel_2_qs; |
| logic [5:0] mio_outsel_2_wd; |
| logic mio_outsel_3_we; |
| logic [5:0] mio_outsel_3_qs; |
| logic [5:0] mio_outsel_3_wd; |
| logic mio_outsel_4_we; |
| logic [5:0] mio_outsel_4_qs; |
| logic [5:0] mio_outsel_4_wd; |
| logic mio_outsel_5_we; |
| logic [5:0] mio_outsel_5_qs; |
| logic [5:0] mio_outsel_5_wd; |
| logic mio_outsel_6_we; |
| logic [5:0] mio_outsel_6_qs; |
| logic [5:0] mio_outsel_6_wd; |
| logic mio_outsel_7_we; |
| logic [5:0] mio_outsel_7_qs; |
| logic [5:0] mio_outsel_7_wd; |
| logic mio_outsel_8_we; |
| logic [5:0] mio_outsel_8_qs; |
| logic [5:0] mio_outsel_8_wd; |
| logic mio_outsel_9_we; |
| logic [5:0] mio_outsel_9_qs; |
| logic [5:0] mio_outsel_9_wd; |
| logic mio_outsel_10_we; |
| logic [5:0] mio_outsel_10_qs; |
| logic [5:0] mio_outsel_10_wd; |
| logic mio_outsel_11_we; |
| logic [5:0] mio_outsel_11_qs; |
| logic [5:0] mio_outsel_11_wd; |
| logic mio_outsel_12_we; |
| logic [5:0] mio_outsel_12_qs; |
| logic [5:0] mio_outsel_12_wd; |
| logic mio_outsel_13_we; |
| logic [5:0] mio_outsel_13_qs; |
| logic [5:0] mio_outsel_13_wd; |
| logic mio_outsel_14_we; |
| logic [5:0] mio_outsel_14_qs; |
| logic [5:0] mio_outsel_14_wd; |
| logic mio_outsel_15_we; |
| logic [5:0] mio_outsel_15_qs; |
| logic [5:0] mio_outsel_15_wd; |
| logic mio_outsel_16_we; |
| logic [5:0] mio_outsel_16_qs; |
| logic [5:0] mio_outsel_16_wd; |
| logic mio_outsel_17_we; |
| logic [5:0] mio_outsel_17_qs; |
| logic [5:0] mio_outsel_17_wd; |
| logic mio_outsel_18_we; |
| logic [5:0] mio_outsel_18_qs; |
| logic [5:0] mio_outsel_18_wd; |
| logic mio_outsel_19_we; |
| logic [5:0] mio_outsel_19_qs; |
| logic [5:0] mio_outsel_19_wd; |
| logic mio_outsel_20_we; |
| logic [5:0] mio_outsel_20_qs; |
| logic [5:0] mio_outsel_20_wd; |
| logic mio_outsel_21_we; |
| logic [5:0] mio_outsel_21_qs; |
| logic [5:0] mio_outsel_21_wd; |
| logic mio_outsel_22_we; |
| logic [5:0] mio_outsel_22_qs; |
| logic [5:0] mio_outsel_22_wd; |
| logic mio_outsel_23_we; |
| logic [5:0] mio_outsel_23_qs; |
| logic [5:0] mio_outsel_23_wd; |
| logic mio_outsel_24_we; |
| logic [5:0] mio_outsel_24_qs; |
| logic [5:0] mio_outsel_24_wd; |
| logic mio_outsel_25_we; |
| logic [5:0] mio_outsel_25_qs; |
| logic [5:0] mio_outsel_25_wd; |
| logic mio_outsel_26_we; |
| logic [5:0] mio_outsel_26_qs; |
| logic [5:0] mio_outsel_26_wd; |
| logic mio_outsel_27_we; |
| logic [5:0] mio_outsel_27_qs; |
| logic [5:0] mio_outsel_27_wd; |
| logic mio_outsel_28_we; |
| logic [5:0] mio_outsel_28_qs; |
| logic [5:0] mio_outsel_28_wd; |
| logic mio_outsel_29_we; |
| logic [5:0] mio_outsel_29_qs; |
| logic [5:0] mio_outsel_29_wd; |
| logic mio_outsel_30_we; |
| logic [5:0] mio_outsel_30_qs; |
| logic [5:0] mio_outsel_30_wd; |
| logic mio_outsel_31_we; |
| logic [5:0] mio_outsel_31_qs; |
| logic [5:0] mio_outsel_31_wd; |
| logic mio_pad_attr_regwen_0_we; |
| logic mio_pad_attr_regwen_0_qs; |
| logic mio_pad_attr_regwen_0_wd; |
| logic mio_pad_attr_regwen_1_we; |
| logic mio_pad_attr_regwen_1_qs; |
| logic mio_pad_attr_regwen_1_wd; |
| logic mio_pad_attr_regwen_2_we; |
| logic mio_pad_attr_regwen_2_qs; |
| logic mio_pad_attr_regwen_2_wd; |
| logic mio_pad_attr_regwen_3_we; |
| logic mio_pad_attr_regwen_3_qs; |
| logic mio_pad_attr_regwen_3_wd; |
| logic mio_pad_attr_regwen_4_we; |
| logic mio_pad_attr_regwen_4_qs; |
| logic mio_pad_attr_regwen_4_wd; |
| logic mio_pad_attr_regwen_5_we; |
| logic mio_pad_attr_regwen_5_qs; |
| logic mio_pad_attr_regwen_5_wd; |
| logic mio_pad_attr_regwen_6_we; |
| logic mio_pad_attr_regwen_6_qs; |
| logic mio_pad_attr_regwen_6_wd; |
| logic mio_pad_attr_regwen_7_we; |
| logic mio_pad_attr_regwen_7_qs; |
| logic mio_pad_attr_regwen_7_wd; |
| logic mio_pad_attr_regwen_8_we; |
| logic mio_pad_attr_regwen_8_qs; |
| logic mio_pad_attr_regwen_8_wd; |
| logic mio_pad_attr_regwen_9_we; |
| logic mio_pad_attr_regwen_9_qs; |
| logic mio_pad_attr_regwen_9_wd; |
| logic mio_pad_attr_regwen_10_we; |
| logic mio_pad_attr_regwen_10_qs; |
| logic mio_pad_attr_regwen_10_wd; |
| logic mio_pad_attr_regwen_11_we; |
| logic mio_pad_attr_regwen_11_qs; |
| logic mio_pad_attr_regwen_11_wd; |
| logic mio_pad_attr_regwen_12_we; |
| logic mio_pad_attr_regwen_12_qs; |
| logic mio_pad_attr_regwen_12_wd; |
| logic mio_pad_attr_regwen_13_we; |
| logic mio_pad_attr_regwen_13_qs; |
| logic mio_pad_attr_regwen_13_wd; |
| logic mio_pad_attr_regwen_14_we; |
| logic mio_pad_attr_regwen_14_qs; |
| logic mio_pad_attr_regwen_14_wd; |
| logic mio_pad_attr_regwen_15_we; |
| logic mio_pad_attr_regwen_15_qs; |
| logic mio_pad_attr_regwen_15_wd; |
| logic mio_pad_attr_regwen_16_we; |
| logic mio_pad_attr_regwen_16_qs; |
| logic mio_pad_attr_regwen_16_wd; |
| logic mio_pad_attr_regwen_17_we; |
| logic mio_pad_attr_regwen_17_qs; |
| logic mio_pad_attr_regwen_17_wd; |
| logic mio_pad_attr_regwen_18_we; |
| logic mio_pad_attr_regwen_18_qs; |
| logic mio_pad_attr_regwen_18_wd; |
| logic mio_pad_attr_regwen_19_we; |
| logic mio_pad_attr_regwen_19_qs; |
| logic mio_pad_attr_regwen_19_wd; |
| logic mio_pad_attr_regwen_20_we; |
| logic mio_pad_attr_regwen_20_qs; |
| logic mio_pad_attr_regwen_20_wd; |
| logic mio_pad_attr_regwen_21_we; |
| logic mio_pad_attr_regwen_21_qs; |
| logic mio_pad_attr_regwen_21_wd; |
| logic mio_pad_attr_regwen_22_we; |
| logic mio_pad_attr_regwen_22_qs; |
| logic mio_pad_attr_regwen_22_wd; |
| logic mio_pad_attr_regwen_23_we; |
| logic mio_pad_attr_regwen_23_qs; |
| logic mio_pad_attr_regwen_23_wd; |
| logic mio_pad_attr_regwen_24_we; |
| logic mio_pad_attr_regwen_24_qs; |
| logic mio_pad_attr_regwen_24_wd; |
| logic mio_pad_attr_regwen_25_we; |
| logic mio_pad_attr_regwen_25_qs; |
| logic mio_pad_attr_regwen_25_wd; |
| logic mio_pad_attr_regwen_26_we; |
| logic mio_pad_attr_regwen_26_qs; |
| logic mio_pad_attr_regwen_26_wd; |
| logic mio_pad_attr_regwen_27_we; |
| logic mio_pad_attr_regwen_27_qs; |
| logic mio_pad_attr_regwen_27_wd; |
| logic mio_pad_attr_regwen_28_we; |
| logic mio_pad_attr_regwen_28_qs; |
| logic mio_pad_attr_regwen_28_wd; |
| logic mio_pad_attr_regwen_29_we; |
| logic mio_pad_attr_regwen_29_qs; |
| logic mio_pad_attr_regwen_29_wd; |
| logic mio_pad_attr_regwen_30_we; |
| logic mio_pad_attr_regwen_30_qs; |
| logic mio_pad_attr_regwen_30_wd; |
| logic mio_pad_attr_regwen_31_we; |
| logic mio_pad_attr_regwen_31_qs; |
| logic mio_pad_attr_regwen_31_wd; |
| logic mio_pad_attr_0_re; |
| logic mio_pad_attr_0_we; |
| logic mio_pad_attr_0_invert_0_qs; |
| logic mio_pad_attr_0_invert_0_wd; |
| logic mio_pad_attr_0_virtual_od_en_0_qs; |
| logic mio_pad_attr_0_virtual_od_en_0_wd; |
| logic mio_pad_attr_0_pull_en_0_qs; |
| logic mio_pad_attr_0_pull_en_0_wd; |
| logic mio_pad_attr_0_pull_select_0_qs; |
| logic mio_pad_attr_0_pull_select_0_wd; |
| logic mio_pad_attr_0_keeper_en_0_qs; |
| logic mio_pad_attr_0_keeper_en_0_wd; |
| logic mio_pad_attr_0_schmitt_en_0_qs; |
| logic mio_pad_attr_0_schmitt_en_0_wd; |
| logic mio_pad_attr_0_od_en_0_qs; |
| logic mio_pad_attr_0_od_en_0_wd; |
| logic [1:0] mio_pad_attr_0_slew_rate_0_qs; |
| logic [1:0] mio_pad_attr_0_slew_rate_0_wd; |
| logic [3:0] mio_pad_attr_0_drive_strength_0_qs; |
| logic [3:0] mio_pad_attr_0_drive_strength_0_wd; |
| logic mio_pad_attr_1_re; |
| logic mio_pad_attr_1_we; |
| logic mio_pad_attr_1_invert_1_qs; |
| logic mio_pad_attr_1_invert_1_wd; |
| logic mio_pad_attr_1_virtual_od_en_1_qs; |
| logic mio_pad_attr_1_virtual_od_en_1_wd; |
| logic mio_pad_attr_1_pull_en_1_qs; |
| logic mio_pad_attr_1_pull_en_1_wd; |
| logic mio_pad_attr_1_pull_select_1_qs; |
| logic mio_pad_attr_1_pull_select_1_wd; |
| logic mio_pad_attr_1_keeper_en_1_qs; |
| logic mio_pad_attr_1_keeper_en_1_wd; |
| logic mio_pad_attr_1_schmitt_en_1_qs; |
| logic mio_pad_attr_1_schmitt_en_1_wd; |
| logic mio_pad_attr_1_od_en_1_qs; |
| logic mio_pad_attr_1_od_en_1_wd; |
| logic [1:0] mio_pad_attr_1_slew_rate_1_qs; |
| logic [1:0] mio_pad_attr_1_slew_rate_1_wd; |
| logic [3:0] mio_pad_attr_1_drive_strength_1_qs; |
| logic [3:0] mio_pad_attr_1_drive_strength_1_wd; |
| logic mio_pad_attr_2_re; |
| logic mio_pad_attr_2_we; |
| logic mio_pad_attr_2_invert_2_qs; |
| logic mio_pad_attr_2_invert_2_wd; |
| logic mio_pad_attr_2_virtual_od_en_2_qs; |
| logic mio_pad_attr_2_virtual_od_en_2_wd; |
| logic mio_pad_attr_2_pull_en_2_qs; |
| logic mio_pad_attr_2_pull_en_2_wd; |
| logic mio_pad_attr_2_pull_select_2_qs; |
| logic mio_pad_attr_2_pull_select_2_wd; |
| logic mio_pad_attr_2_keeper_en_2_qs; |
| logic mio_pad_attr_2_keeper_en_2_wd; |
| logic mio_pad_attr_2_schmitt_en_2_qs; |
| logic mio_pad_attr_2_schmitt_en_2_wd; |
| logic mio_pad_attr_2_od_en_2_qs; |
| logic mio_pad_attr_2_od_en_2_wd; |
| logic [1:0] mio_pad_attr_2_slew_rate_2_qs; |
| logic [1:0] mio_pad_attr_2_slew_rate_2_wd; |
| logic [3:0] mio_pad_attr_2_drive_strength_2_qs; |
| logic [3:0] mio_pad_attr_2_drive_strength_2_wd; |
| logic mio_pad_attr_3_re; |
| logic mio_pad_attr_3_we; |
| logic mio_pad_attr_3_invert_3_qs; |
| logic mio_pad_attr_3_invert_3_wd; |
| logic mio_pad_attr_3_virtual_od_en_3_qs; |
| logic mio_pad_attr_3_virtual_od_en_3_wd; |
| logic mio_pad_attr_3_pull_en_3_qs; |
| logic mio_pad_attr_3_pull_en_3_wd; |
| logic mio_pad_attr_3_pull_select_3_qs; |
| logic mio_pad_attr_3_pull_select_3_wd; |
| logic mio_pad_attr_3_keeper_en_3_qs; |
| logic mio_pad_attr_3_keeper_en_3_wd; |
| logic mio_pad_attr_3_schmitt_en_3_qs; |
| logic mio_pad_attr_3_schmitt_en_3_wd; |
| logic mio_pad_attr_3_od_en_3_qs; |
| logic mio_pad_attr_3_od_en_3_wd; |
| logic [1:0] mio_pad_attr_3_slew_rate_3_qs; |
| logic [1:0] mio_pad_attr_3_slew_rate_3_wd; |
| logic [3:0] mio_pad_attr_3_drive_strength_3_qs; |
| logic [3:0] mio_pad_attr_3_drive_strength_3_wd; |
| logic mio_pad_attr_4_re; |
| logic mio_pad_attr_4_we; |
| logic mio_pad_attr_4_invert_4_qs; |
| logic mio_pad_attr_4_invert_4_wd; |
| logic mio_pad_attr_4_virtual_od_en_4_qs; |
| logic mio_pad_attr_4_virtual_od_en_4_wd; |
| logic mio_pad_attr_4_pull_en_4_qs; |
| logic mio_pad_attr_4_pull_en_4_wd; |
| logic mio_pad_attr_4_pull_select_4_qs; |
| logic mio_pad_attr_4_pull_select_4_wd; |
| logic mio_pad_attr_4_keeper_en_4_qs; |
| logic mio_pad_attr_4_keeper_en_4_wd; |
| logic mio_pad_attr_4_schmitt_en_4_qs; |
| logic mio_pad_attr_4_schmitt_en_4_wd; |
| logic mio_pad_attr_4_od_en_4_qs; |
| logic mio_pad_attr_4_od_en_4_wd; |
| logic [1:0] mio_pad_attr_4_slew_rate_4_qs; |
| logic [1:0] mio_pad_attr_4_slew_rate_4_wd; |
| logic [3:0] mio_pad_attr_4_drive_strength_4_qs; |
| logic [3:0] mio_pad_attr_4_drive_strength_4_wd; |
| logic mio_pad_attr_5_re; |
| logic mio_pad_attr_5_we; |
| logic mio_pad_attr_5_invert_5_qs; |
| logic mio_pad_attr_5_invert_5_wd; |
| logic mio_pad_attr_5_virtual_od_en_5_qs; |
| logic mio_pad_attr_5_virtual_od_en_5_wd; |
| logic mio_pad_attr_5_pull_en_5_qs; |
| logic mio_pad_attr_5_pull_en_5_wd; |
| logic mio_pad_attr_5_pull_select_5_qs; |
| logic mio_pad_attr_5_pull_select_5_wd; |
| logic mio_pad_attr_5_keeper_en_5_qs; |
| logic mio_pad_attr_5_keeper_en_5_wd; |
| logic mio_pad_attr_5_schmitt_en_5_qs; |
| logic mio_pad_attr_5_schmitt_en_5_wd; |
| logic mio_pad_attr_5_od_en_5_qs; |
| logic mio_pad_attr_5_od_en_5_wd; |
| logic [1:0] mio_pad_attr_5_slew_rate_5_qs; |
| logic [1:0] mio_pad_attr_5_slew_rate_5_wd; |
| logic [3:0] mio_pad_attr_5_drive_strength_5_qs; |
| logic [3:0] mio_pad_attr_5_drive_strength_5_wd; |
| logic mio_pad_attr_6_re; |
| logic mio_pad_attr_6_we; |
| logic mio_pad_attr_6_invert_6_qs; |
| logic mio_pad_attr_6_invert_6_wd; |
| logic mio_pad_attr_6_virtual_od_en_6_qs; |
| logic mio_pad_attr_6_virtual_od_en_6_wd; |
| logic mio_pad_attr_6_pull_en_6_qs; |
| logic mio_pad_attr_6_pull_en_6_wd; |
| logic mio_pad_attr_6_pull_select_6_qs; |
| logic mio_pad_attr_6_pull_select_6_wd; |
| logic mio_pad_attr_6_keeper_en_6_qs; |
| logic mio_pad_attr_6_keeper_en_6_wd; |
| logic mio_pad_attr_6_schmitt_en_6_qs; |
| logic mio_pad_attr_6_schmitt_en_6_wd; |
| logic mio_pad_attr_6_od_en_6_qs; |
| logic mio_pad_attr_6_od_en_6_wd; |
| logic [1:0] mio_pad_attr_6_slew_rate_6_qs; |
| logic [1:0] mio_pad_attr_6_slew_rate_6_wd; |
| logic [3:0] mio_pad_attr_6_drive_strength_6_qs; |
| logic [3:0] mio_pad_attr_6_drive_strength_6_wd; |
| logic mio_pad_attr_7_re; |
| logic mio_pad_attr_7_we; |
| logic mio_pad_attr_7_invert_7_qs; |
| logic mio_pad_attr_7_invert_7_wd; |
| logic mio_pad_attr_7_virtual_od_en_7_qs; |
| logic mio_pad_attr_7_virtual_od_en_7_wd; |
| logic mio_pad_attr_7_pull_en_7_qs; |
| logic mio_pad_attr_7_pull_en_7_wd; |
| logic mio_pad_attr_7_pull_select_7_qs; |
| logic mio_pad_attr_7_pull_select_7_wd; |
| logic mio_pad_attr_7_keeper_en_7_qs; |
| logic mio_pad_attr_7_keeper_en_7_wd; |
| logic mio_pad_attr_7_schmitt_en_7_qs; |
| logic mio_pad_attr_7_schmitt_en_7_wd; |
| logic mio_pad_attr_7_od_en_7_qs; |
| logic mio_pad_attr_7_od_en_7_wd; |
| logic [1:0] mio_pad_attr_7_slew_rate_7_qs; |
| logic [1:0] mio_pad_attr_7_slew_rate_7_wd; |
| logic [3:0] mio_pad_attr_7_drive_strength_7_qs; |
| logic [3:0] mio_pad_attr_7_drive_strength_7_wd; |
| logic mio_pad_attr_8_re; |
| logic mio_pad_attr_8_we; |
| logic mio_pad_attr_8_invert_8_qs; |
| logic mio_pad_attr_8_invert_8_wd; |
| logic mio_pad_attr_8_virtual_od_en_8_qs; |
| logic mio_pad_attr_8_virtual_od_en_8_wd; |
| logic mio_pad_attr_8_pull_en_8_qs; |
| logic mio_pad_attr_8_pull_en_8_wd; |
| logic mio_pad_attr_8_pull_select_8_qs; |
| logic mio_pad_attr_8_pull_select_8_wd; |
| logic mio_pad_attr_8_keeper_en_8_qs; |
| logic mio_pad_attr_8_keeper_en_8_wd; |
| logic mio_pad_attr_8_schmitt_en_8_qs; |
| logic mio_pad_attr_8_schmitt_en_8_wd; |
| logic mio_pad_attr_8_od_en_8_qs; |
| logic mio_pad_attr_8_od_en_8_wd; |
| logic [1:0] mio_pad_attr_8_slew_rate_8_qs; |
| logic [1:0] mio_pad_attr_8_slew_rate_8_wd; |
| logic [3:0] mio_pad_attr_8_drive_strength_8_qs; |
| logic [3:0] mio_pad_attr_8_drive_strength_8_wd; |
| logic mio_pad_attr_9_re; |
| logic mio_pad_attr_9_we; |
| logic mio_pad_attr_9_invert_9_qs; |
| logic mio_pad_attr_9_invert_9_wd; |
| logic mio_pad_attr_9_virtual_od_en_9_qs; |
| logic mio_pad_attr_9_virtual_od_en_9_wd; |
| logic mio_pad_attr_9_pull_en_9_qs; |
| logic mio_pad_attr_9_pull_en_9_wd; |
| logic mio_pad_attr_9_pull_select_9_qs; |
| logic mio_pad_attr_9_pull_select_9_wd; |
| logic mio_pad_attr_9_keeper_en_9_qs; |
| logic mio_pad_attr_9_keeper_en_9_wd; |
| logic mio_pad_attr_9_schmitt_en_9_qs; |
| logic mio_pad_attr_9_schmitt_en_9_wd; |
| logic mio_pad_attr_9_od_en_9_qs; |
| logic mio_pad_attr_9_od_en_9_wd; |
| logic [1:0] mio_pad_attr_9_slew_rate_9_qs; |
| logic [1:0] mio_pad_attr_9_slew_rate_9_wd; |
| logic [3:0] mio_pad_attr_9_drive_strength_9_qs; |
| logic [3:0] mio_pad_attr_9_drive_strength_9_wd; |
| logic mio_pad_attr_10_re; |
| logic mio_pad_attr_10_we; |
| logic mio_pad_attr_10_invert_10_qs; |
| logic mio_pad_attr_10_invert_10_wd; |
| logic mio_pad_attr_10_virtual_od_en_10_qs; |
| logic mio_pad_attr_10_virtual_od_en_10_wd; |
| logic mio_pad_attr_10_pull_en_10_qs; |
| logic mio_pad_attr_10_pull_en_10_wd; |
| logic mio_pad_attr_10_pull_select_10_qs; |
| logic mio_pad_attr_10_pull_select_10_wd; |
| logic mio_pad_attr_10_keeper_en_10_qs; |
| logic mio_pad_attr_10_keeper_en_10_wd; |
| logic mio_pad_attr_10_schmitt_en_10_qs; |
| logic mio_pad_attr_10_schmitt_en_10_wd; |
| logic mio_pad_attr_10_od_en_10_qs; |
| logic mio_pad_attr_10_od_en_10_wd; |
| logic [1:0] mio_pad_attr_10_slew_rate_10_qs; |
| logic [1:0] mio_pad_attr_10_slew_rate_10_wd; |
| logic [3:0] mio_pad_attr_10_drive_strength_10_qs; |
| logic [3:0] mio_pad_attr_10_drive_strength_10_wd; |
| logic mio_pad_attr_11_re; |
| logic mio_pad_attr_11_we; |
| logic mio_pad_attr_11_invert_11_qs; |
| logic mio_pad_attr_11_invert_11_wd; |
| logic mio_pad_attr_11_virtual_od_en_11_qs; |
| logic mio_pad_attr_11_virtual_od_en_11_wd; |
| logic mio_pad_attr_11_pull_en_11_qs; |
| logic mio_pad_attr_11_pull_en_11_wd; |
| logic mio_pad_attr_11_pull_select_11_qs; |
| logic mio_pad_attr_11_pull_select_11_wd; |
| logic mio_pad_attr_11_keeper_en_11_qs; |
| logic mio_pad_attr_11_keeper_en_11_wd; |
| logic mio_pad_attr_11_schmitt_en_11_qs; |
| logic mio_pad_attr_11_schmitt_en_11_wd; |
| logic mio_pad_attr_11_od_en_11_qs; |
| logic mio_pad_attr_11_od_en_11_wd; |
| logic [1:0] mio_pad_attr_11_slew_rate_11_qs; |
| logic [1:0] mio_pad_attr_11_slew_rate_11_wd; |
| logic [3:0] mio_pad_attr_11_drive_strength_11_qs; |
| logic [3:0] mio_pad_attr_11_drive_strength_11_wd; |
| logic mio_pad_attr_12_re; |
| logic mio_pad_attr_12_we; |
| logic mio_pad_attr_12_invert_12_qs; |
| logic mio_pad_attr_12_invert_12_wd; |
| logic mio_pad_attr_12_virtual_od_en_12_qs; |
| logic mio_pad_attr_12_virtual_od_en_12_wd; |
| logic mio_pad_attr_12_pull_en_12_qs; |
| logic mio_pad_attr_12_pull_en_12_wd; |
| logic mio_pad_attr_12_pull_select_12_qs; |
| logic mio_pad_attr_12_pull_select_12_wd; |
| logic mio_pad_attr_12_keeper_en_12_qs; |
| logic mio_pad_attr_12_keeper_en_12_wd; |
| logic mio_pad_attr_12_schmitt_en_12_qs; |
| logic mio_pad_attr_12_schmitt_en_12_wd; |
| logic mio_pad_attr_12_od_en_12_qs; |
| logic mio_pad_attr_12_od_en_12_wd; |
| logic [1:0] mio_pad_attr_12_slew_rate_12_qs; |
| logic [1:0] mio_pad_attr_12_slew_rate_12_wd; |
| logic [3:0] mio_pad_attr_12_drive_strength_12_qs; |
| logic [3:0] mio_pad_attr_12_drive_strength_12_wd; |
| logic mio_pad_attr_13_re; |
| logic mio_pad_attr_13_we; |
| logic mio_pad_attr_13_invert_13_qs; |
| logic mio_pad_attr_13_invert_13_wd; |
| logic mio_pad_attr_13_virtual_od_en_13_qs; |
| logic mio_pad_attr_13_virtual_od_en_13_wd; |
| logic mio_pad_attr_13_pull_en_13_qs; |
| logic mio_pad_attr_13_pull_en_13_wd; |
| logic mio_pad_attr_13_pull_select_13_qs; |
| logic mio_pad_attr_13_pull_select_13_wd; |
| logic mio_pad_attr_13_keeper_en_13_qs; |
| logic mio_pad_attr_13_keeper_en_13_wd; |
| logic mio_pad_attr_13_schmitt_en_13_qs; |
| logic mio_pad_attr_13_schmitt_en_13_wd; |
| logic mio_pad_attr_13_od_en_13_qs; |
| logic mio_pad_attr_13_od_en_13_wd; |
| logic [1:0] mio_pad_attr_13_slew_rate_13_qs; |
| logic [1:0] mio_pad_attr_13_slew_rate_13_wd; |
| logic [3:0] mio_pad_attr_13_drive_strength_13_qs; |
| logic [3:0] mio_pad_attr_13_drive_strength_13_wd; |
| logic mio_pad_attr_14_re; |
| logic mio_pad_attr_14_we; |
| logic mio_pad_attr_14_invert_14_qs; |
| logic mio_pad_attr_14_invert_14_wd; |
| logic mio_pad_attr_14_virtual_od_en_14_qs; |
| logic mio_pad_attr_14_virtual_od_en_14_wd; |
| logic mio_pad_attr_14_pull_en_14_qs; |
| logic mio_pad_attr_14_pull_en_14_wd; |
| logic mio_pad_attr_14_pull_select_14_qs; |
| logic mio_pad_attr_14_pull_select_14_wd; |
| logic mio_pad_attr_14_keeper_en_14_qs; |
| logic mio_pad_attr_14_keeper_en_14_wd; |
| logic mio_pad_attr_14_schmitt_en_14_qs; |
| logic mio_pad_attr_14_schmitt_en_14_wd; |
| logic mio_pad_attr_14_od_en_14_qs; |
| logic mio_pad_attr_14_od_en_14_wd; |
| logic [1:0] mio_pad_attr_14_slew_rate_14_qs; |
| logic [1:0] mio_pad_attr_14_slew_rate_14_wd; |
| logic [3:0] mio_pad_attr_14_drive_strength_14_qs; |
| logic [3:0] mio_pad_attr_14_drive_strength_14_wd; |
| logic mio_pad_attr_15_re; |
| logic mio_pad_attr_15_we; |
| logic mio_pad_attr_15_invert_15_qs; |
| logic mio_pad_attr_15_invert_15_wd; |
| logic mio_pad_attr_15_virtual_od_en_15_qs; |
| logic mio_pad_attr_15_virtual_od_en_15_wd; |
| logic mio_pad_attr_15_pull_en_15_qs; |
| logic mio_pad_attr_15_pull_en_15_wd; |
| logic mio_pad_attr_15_pull_select_15_qs; |
| logic mio_pad_attr_15_pull_select_15_wd; |
| logic mio_pad_attr_15_keeper_en_15_qs; |
| logic mio_pad_attr_15_keeper_en_15_wd; |
| logic mio_pad_attr_15_schmitt_en_15_qs; |
| logic mio_pad_attr_15_schmitt_en_15_wd; |
| logic mio_pad_attr_15_od_en_15_qs; |
| logic mio_pad_attr_15_od_en_15_wd; |
| logic [1:0] mio_pad_attr_15_slew_rate_15_qs; |
| logic [1:0] mio_pad_attr_15_slew_rate_15_wd; |
| logic [3:0] mio_pad_attr_15_drive_strength_15_qs; |
| logic [3:0] mio_pad_attr_15_drive_strength_15_wd; |
| logic mio_pad_attr_16_re; |
| logic mio_pad_attr_16_we; |
| logic mio_pad_attr_16_invert_16_qs; |
| logic mio_pad_attr_16_invert_16_wd; |
| logic mio_pad_attr_16_virtual_od_en_16_qs; |
| logic mio_pad_attr_16_virtual_od_en_16_wd; |
| logic mio_pad_attr_16_pull_en_16_qs; |
| logic mio_pad_attr_16_pull_en_16_wd; |
| logic mio_pad_attr_16_pull_select_16_qs; |
| logic mio_pad_attr_16_pull_select_16_wd; |
| logic mio_pad_attr_16_keeper_en_16_qs; |
| logic mio_pad_attr_16_keeper_en_16_wd; |
| logic mio_pad_attr_16_schmitt_en_16_qs; |
| logic mio_pad_attr_16_schmitt_en_16_wd; |
| logic mio_pad_attr_16_od_en_16_qs; |
| logic mio_pad_attr_16_od_en_16_wd; |
| logic [1:0] mio_pad_attr_16_slew_rate_16_qs; |
| logic [1:0] mio_pad_attr_16_slew_rate_16_wd; |
| logic [3:0] mio_pad_attr_16_drive_strength_16_qs; |
| logic [3:0] mio_pad_attr_16_drive_strength_16_wd; |
| logic mio_pad_attr_17_re; |
| logic mio_pad_attr_17_we; |
| logic mio_pad_attr_17_invert_17_qs; |
| logic mio_pad_attr_17_invert_17_wd; |
| logic mio_pad_attr_17_virtual_od_en_17_qs; |
| logic mio_pad_attr_17_virtual_od_en_17_wd; |
| logic mio_pad_attr_17_pull_en_17_qs; |
| logic mio_pad_attr_17_pull_en_17_wd; |
| logic mio_pad_attr_17_pull_select_17_qs; |
| logic mio_pad_attr_17_pull_select_17_wd; |
| logic mio_pad_attr_17_keeper_en_17_qs; |
| logic mio_pad_attr_17_keeper_en_17_wd; |
| logic mio_pad_attr_17_schmitt_en_17_qs; |
| logic mio_pad_attr_17_schmitt_en_17_wd; |
| logic mio_pad_attr_17_od_en_17_qs; |
| logic mio_pad_attr_17_od_en_17_wd; |
| logic [1:0] mio_pad_attr_17_slew_rate_17_qs; |
| logic [1:0] mio_pad_attr_17_slew_rate_17_wd; |
| logic [3:0] mio_pad_attr_17_drive_strength_17_qs; |
| logic [3:0] mio_pad_attr_17_drive_strength_17_wd; |
| logic mio_pad_attr_18_re; |
| logic mio_pad_attr_18_we; |
| logic mio_pad_attr_18_invert_18_qs; |
| logic mio_pad_attr_18_invert_18_wd; |
| logic mio_pad_attr_18_virtual_od_en_18_qs; |
| logic mio_pad_attr_18_virtual_od_en_18_wd; |
| logic mio_pad_attr_18_pull_en_18_qs; |
| logic mio_pad_attr_18_pull_en_18_wd; |
| logic mio_pad_attr_18_pull_select_18_qs; |
| logic mio_pad_attr_18_pull_select_18_wd; |
| logic mio_pad_attr_18_keeper_en_18_qs; |
| logic mio_pad_attr_18_keeper_en_18_wd; |
| logic mio_pad_attr_18_schmitt_en_18_qs; |
| logic mio_pad_attr_18_schmitt_en_18_wd; |
| logic mio_pad_attr_18_od_en_18_qs; |
| logic mio_pad_attr_18_od_en_18_wd; |
| logic [1:0] mio_pad_attr_18_slew_rate_18_qs; |
| logic [1:0] mio_pad_attr_18_slew_rate_18_wd; |
| logic [3:0] mio_pad_attr_18_drive_strength_18_qs; |
| logic [3:0] mio_pad_attr_18_drive_strength_18_wd; |
| logic mio_pad_attr_19_re; |
| logic mio_pad_attr_19_we; |
| logic mio_pad_attr_19_invert_19_qs; |
| logic mio_pad_attr_19_invert_19_wd; |
| logic mio_pad_attr_19_virtual_od_en_19_qs; |
| logic mio_pad_attr_19_virtual_od_en_19_wd; |
| logic mio_pad_attr_19_pull_en_19_qs; |
| logic mio_pad_attr_19_pull_en_19_wd; |
| logic mio_pad_attr_19_pull_select_19_qs; |
| logic mio_pad_attr_19_pull_select_19_wd; |
| logic mio_pad_attr_19_keeper_en_19_qs; |
| logic mio_pad_attr_19_keeper_en_19_wd; |
| logic mio_pad_attr_19_schmitt_en_19_qs; |
| logic mio_pad_attr_19_schmitt_en_19_wd; |
| logic mio_pad_attr_19_od_en_19_qs; |
| logic mio_pad_attr_19_od_en_19_wd; |
| logic [1:0] mio_pad_attr_19_slew_rate_19_qs; |
| logic [1:0] mio_pad_attr_19_slew_rate_19_wd; |
| logic [3:0] mio_pad_attr_19_drive_strength_19_qs; |
| logic [3:0] mio_pad_attr_19_drive_strength_19_wd; |
| logic mio_pad_attr_20_re; |
| logic mio_pad_attr_20_we; |
| logic mio_pad_attr_20_invert_20_qs; |
| logic mio_pad_attr_20_invert_20_wd; |
| logic mio_pad_attr_20_virtual_od_en_20_qs; |
| logic mio_pad_attr_20_virtual_od_en_20_wd; |
| logic mio_pad_attr_20_pull_en_20_qs; |
| logic mio_pad_attr_20_pull_en_20_wd; |
| logic mio_pad_attr_20_pull_select_20_qs; |
| logic mio_pad_attr_20_pull_select_20_wd; |
| logic mio_pad_attr_20_keeper_en_20_qs; |
| logic mio_pad_attr_20_keeper_en_20_wd; |
| logic mio_pad_attr_20_schmitt_en_20_qs; |
| logic mio_pad_attr_20_schmitt_en_20_wd; |
| logic mio_pad_attr_20_od_en_20_qs; |
| logic mio_pad_attr_20_od_en_20_wd; |
| logic [1:0] mio_pad_attr_20_slew_rate_20_qs; |
| logic [1:0] mio_pad_attr_20_slew_rate_20_wd; |
| logic [3:0] mio_pad_attr_20_drive_strength_20_qs; |
| logic [3:0] mio_pad_attr_20_drive_strength_20_wd; |
| logic mio_pad_attr_21_re; |
| logic mio_pad_attr_21_we; |
| logic mio_pad_attr_21_invert_21_qs; |
| logic mio_pad_attr_21_invert_21_wd; |
| logic mio_pad_attr_21_virtual_od_en_21_qs; |
| logic mio_pad_attr_21_virtual_od_en_21_wd; |
| logic mio_pad_attr_21_pull_en_21_qs; |
| logic mio_pad_attr_21_pull_en_21_wd; |
| logic mio_pad_attr_21_pull_select_21_qs; |
| logic mio_pad_attr_21_pull_select_21_wd; |
| logic mio_pad_attr_21_keeper_en_21_qs; |
| logic mio_pad_attr_21_keeper_en_21_wd; |
| logic mio_pad_attr_21_schmitt_en_21_qs; |
| logic mio_pad_attr_21_schmitt_en_21_wd; |
| logic mio_pad_attr_21_od_en_21_qs; |
| logic mio_pad_attr_21_od_en_21_wd; |
| logic [1:0] mio_pad_attr_21_slew_rate_21_qs; |
| logic [1:0] mio_pad_attr_21_slew_rate_21_wd; |
| logic [3:0] mio_pad_attr_21_drive_strength_21_qs; |
| logic [3:0] mio_pad_attr_21_drive_strength_21_wd; |
| logic mio_pad_attr_22_re; |
| logic mio_pad_attr_22_we; |
| logic mio_pad_attr_22_invert_22_qs; |
| logic mio_pad_attr_22_invert_22_wd; |
| logic mio_pad_attr_22_virtual_od_en_22_qs; |
| logic mio_pad_attr_22_virtual_od_en_22_wd; |
| logic mio_pad_attr_22_pull_en_22_qs; |
| logic mio_pad_attr_22_pull_en_22_wd; |
| logic mio_pad_attr_22_pull_select_22_qs; |
| logic mio_pad_attr_22_pull_select_22_wd; |
| logic mio_pad_attr_22_keeper_en_22_qs; |
| logic mio_pad_attr_22_keeper_en_22_wd; |
| logic mio_pad_attr_22_schmitt_en_22_qs; |
| logic mio_pad_attr_22_schmitt_en_22_wd; |
| logic mio_pad_attr_22_od_en_22_qs; |
| logic mio_pad_attr_22_od_en_22_wd; |
| logic [1:0] mio_pad_attr_22_slew_rate_22_qs; |
| logic [1:0] mio_pad_attr_22_slew_rate_22_wd; |
| logic [3:0] mio_pad_attr_22_drive_strength_22_qs; |
| logic [3:0] mio_pad_attr_22_drive_strength_22_wd; |
| logic mio_pad_attr_23_re; |
| logic mio_pad_attr_23_we; |
| logic mio_pad_attr_23_invert_23_qs; |
| logic mio_pad_attr_23_invert_23_wd; |
| logic mio_pad_attr_23_virtual_od_en_23_qs; |
| logic mio_pad_attr_23_virtual_od_en_23_wd; |
| logic mio_pad_attr_23_pull_en_23_qs; |
| logic mio_pad_attr_23_pull_en_23_wd; |
| logic mio_pad_attr_23_pull_select_23_qs; |
| logic mio_pad_attr_23_pull_select_23_wd; |
| logic mio_pad_attr_23_keeper_en_23_qs; |
| logic mio_pad_attr_23_keeper_en_23_wd; |
| logic mio_pad_attr_23_schmitt_en_23_qs; |
| logic mio_pad_attr_23_schmitt_en_23_wd; |
| logic mio_pad_attr_23_od_en_23_qs; |
| logic mio_pad_attr_23_od_en_23_wd; |
| logic [1:0] mio_pad_attr_23_slew_rate_23_qs; |
| logic [1:0] mio_pad_attr_23_slew_rate_23_wd; |
| logic [3:0] mio_pad_attr_23_drive_strength_23_qs; |
| logic [3:0] mio_pad_attr_23_drive_strength_23_wd; |
| logic mio_pad_attr_24_re; |
| logic mio_pad_attr_24_we; |
| logic mio_pad_attr_24_invert_24_qs; |
| logic mio_pad_attr_24_invert_24_wd; |
| logic mio_pad_attr_24_virtual_od_en_24_qs; |
| logic mio_pad_attr_24_virtual_od_en_24_wd; |
| logic mio_pad_attr_24_pull_en_24_qs; |
| logic mio_pad_attr_24_pull_en_24_wd; |
| logic mio_pad_attr_24_pull_select_24_qs; |
| logic mio_pad_attr_24_pull_select_24_wd; |
| logic mio_pad_attr_24_keeper_en_24_qs; |
| logic mio_pad_attr_24_keeper_en_24_wd; |
| logic mio_pad_attr_24_schmitt_en_24_qs; |
| logic mio_pad_attr_24_schmitt_en_24_wd; |
| logic mio_pad_attr_24_od_en_24_qs; |
| logic mio_pad_attr_24_od_en_24_wd; |
| logic [1:0] mio_pad_attr_24_slew_rate_24_qs; |
| logic [1:0] mio_pad_attr_24_slew_rate_24_wd; |
| logic [3:0] mio_pad_attr_24_drive_strength_24_qs; |
| logic [3:0] mio_pad_attr_24_drive_strength_24_wd; |
| logic mio_pad_attr_25_re; |
| logic mio_pad_attr_25_we; |
| logic mio_pad_attr_25_invert_25_qs; |
| logic mio_pad_attr_25_invert_25_wd; |
| logic mio_pad_attr_25_virtual_od_en_25_qs; |
| logic mio_pad_attr_25_virtual_od_en_25_wd; |
| logic mio_pad_attr_25_pull_en_25_qs; |
| logic mio_pad_attr_25_pull_en_25_wd; |
| logic mio_pad_attr_25_pull_select_25_qs; |
| logic mio_pad_attr_25_pull_select_25_wd; |
| logic mio_pad_attr_25_keeper_en_25_qs; |
| logic mio_pad_attr_25_keeper_en_25_wd; |
| logic mio_pad_attr_25_schmitt_en_25_qs; |
| logic mio_pad_attr_25_schmitt_en_25_wd; |
| logic mio_pad_attr_25_od_en_25_qs; |
| logic mio_pad_attr_25_od_en_25_wd; |
| logic [1:0] mio_pad_attr_25_slew_rate_25_qs; |
| logic [1:0] mio_pad_attr_25_slew_rate_25_wd; |
| logic [3:0] mio_pad_attr_25_drive_strength_25_qs; |
| logic [3:0] mio_pad_attr_25_drive_strength_25_wd; |
| logic mio_pad_attr_26_re; |
| logic mio_pad_attr_26_we; |
| logic mio_pad_attr_26_invert_26_qs; |
| logic mio_pad_attr_26_invert_26_wd; |
| logic mio_pad_attr_26_virtual_od_en_26_qs; |
| logic mio_pad_attr_26_virtual_od_en_26_wd; |
| logic mio_pad_attr_26_pull_en_26_qs; |
| logic mio_pad_attr_26_pull_en_26_wd; |
| logic mio_pad_attr_26_pull_select_26_qs; |
| logic mio_pad_attr_26_pull_select_26_wd; |
| logic mio_pad_attr_26_keeper_en_26_qs; |
| logic mio_pad_attr_26_keeper_en_26_wd; |
| logic mio_pad_attr_26_schmitt_en_26_qs; |
| logic mio_pad_attr_26_schmitt_en_26_wd; |
| logic mio_pad_attr_26_od_en_26_qs; |
| logic mio_pad_attr_26_od_en_26_wd; |
| logic [1:0] mio_pad_attr_26_slew_rate_26_qs; |
| logic [1:0] mio_pad_attr_26_slew_rate_26_wd; |
| logic [3:0] mio_pad_attr_26_drive_strength_26_qs; |
| logic [3:0] mio_pad_attr_26_drive_strength_26_wd; |
| logic mio_pad_attr_27_re; |
| logic mio_pad_attr_27_we; |
| logic mio_pad_attr_27_invert_27_qs; |
| logic mio_pad_attr_27_invert_27_wd; |
| logic mio_pad_attr_27_virtual_od_en_27_qs; |
| logic mio_pad_attr_27_virtual_od_en_27_wd; |
| logic mio_pad_attr_27_pull_en_27_qs; |
| logic mio_pad_attr_27_pull_en_27_wd; |
| logic mio_pad_attr_27_pull_select_27_qs; |
| logic mio_pad_attr_27_pull_select_27_wd; |
| logic mio_pad_attr_27_keeper_en_27_qs; |
| logic mio_pad_attr_27_keeper_en_27_wd; |
| logic mio_pad_attr_27_schmitt_en_27_qs; |
| logic mio_pad_attr_27_schmitt_en_27_wd; |
| logic mio_pad_attr_27_od_en_27_qs; |
| logic mio_pad_attr_27_od_en_27_wd; |
| logic [1:0] mio_pad_attr_27_slew_rate_27_qs; |
| logic [1:0] mio_pad_attr_27_slew_rate_27_wd; |
| logic [3:0] mio_pad_attr_27_drive_strength_27_qs; |
| logic [3:0] mio_pad_attr_27_drive_strength_27_wd; |
| logic mio_pad_attr_28_re; |
| logic mio_pad_attr_28_we; |
| logic mio_pad_attr_28_invert_28_qs; |
| logic mio_pad_attr_28_invert_28_wd; |
| logic mio_pad_attr_28_virtual_od_en_28_qs; |
| logic mio_pad_attr_28_virtual_od_en_28_wd; |
| logic mio_pad_attr_28_pull_en_28_qs; |
| logic mio_pad_attr_28_pull_en_28_wd; |
| logic mio_pad_attr_28_pull_select_28_qs; |
| logic mio_pad_attr_28_pull_select_28_wd; |
| logic mio_pad_attr_28_keeper_en_28_qs; |
| logic mio_pad_attr_28_keeper_en_28_wd; |
| logic mio_pad_attr_28_schmitt_en_28_qs; |
| logic mio_pad_attr_28_schmitt_en_28_wd; |
| logic mio_pad_attr_28_od_en_28_qs; |
| logic mio_pad_attr_28_od_en_28_wd; |
| logic [1:0] mio_pad_attr_28_slew_rate_28_qs; |
| logic [1:0] mio_pad_attr_28_slew_rate_28_wd; |
| logic [3:0] mio_pad_attr_28_drive_strength_28_qs; |
| logic [3:0] mio_pad_attr_28_drive_strength_28_wd; |
| logic mio_pad_attr_29_re; |
| logic mio_pad_attr_29_we; |
| logic mio_pad_attr_29_invert_29_qs; |
| logic mio_pad_attr_29_invert_29_wd; |
| logic mio_pad_attr_29_virtual_od_en_29_qs; |
| logic mio_pad_attr_29_virtual_od_en_29_wd; |
| logic mio_pad_attr_29_pull_en_29_qs; |
| logic mio_pad_attr_29_pull_en_29_wd; |
| logic mio_pad_attr_29_pull_select_29_qs; |
| logic mio_pad_attr_29_pull_select_29_wd; |
| logic mio_pad_attr_29_keeper_en_29_qs; |
| logic mio_pad_attr_29_keeper_en_29_wd; |
| logic mio_pad_attr_29_schmitt_en_29_qs; |
| logic mio_pad_attr_29_schmitt_en_29_wd; |
| logic mio_pad_attr_29_od_en_29_qs; |
| logic mio_pad_attr_29_od_en_29_wd; |
| logic [1:0] mio_pad_attr_29_slew_rate_29_qs; |
| logic [1:0] mio_pad_attr_29_slew_rate_29_wd; |
| logic [3:0] mio_pad_attr_29_drive_strength_29_qs; |
| logic [3:0] mio_pad_attr_29_drive_strength_29_wd; |
| logic mio_pad_attr_30_re; |
| logic mio_pad_attr_30_we; |
| logic mio_pad_attr_30_invert_30_qs; |
| logic mio_pad_attr_30_invert_30_wd; |
| logic mio_pad_attr_30_virtual_od_en_30_qs; |
| logic mio_pad_attr_30_virtual_od_en_30_wd; |
| logic mio_pad_attr_30_pull_en_30_qs; |
| logic mio_pad_attr_30_pull_en_30_wd; |
| logic mio_pad_attr_30_pull_select_30_qs; |
| logic mio_pad_attr_30_pull_select_30_wd; |
| logic mio_pad_attr_30_keeper_en_30_qs; |
| logic mio_pad_attr_30_keeper_en_30_wd; |
| logic mio_pad_attr_30_schmitt_en_30_qs; |
| logic mio_pad_attr_30_schmitt_en_30_wd; |
| logic mio_pad_attr_30_od_en_30_qs; |
| logic mio_pad_attr_30_od_en_30_wd; |
| logic [1:0] mio_pad_attr_30_slew_rate_30_qs; |
| logic [1:0] mio_pad_attr_30_slew_rate_30_wd; |
| logic [3:0] mio_pad_attr_30_drive_strength_30_qs; |
| logic [3:0] mio_pad_attr_30_drive_strength_30_wd; |
| logic mio_pad_attr_31_re; |
| logic mio_pad_attr_31_we; |
| logic mio_pad_attr_31_invert_31_qs; |
| logic mio_pad_attr_31_invert_31_wd; |
| logic mio_pad_attr_31_virtual_od_en_31_qs; |
| logic mio_pad_attr_31_virtual_od_en_31_wd; |
| logic mio_pad_attr_31_pull_en_31_qs; |
| logic mio_pad_attr_31_pull_en_31_wd; |
| logic mio_pad_attr_31_pull_select_31_qs; |
| logic mio_pad_attr_31_pull_select_31_wd; |
| logic mio_pad_attr_31_keeper_en_31_qs; |
| logic mio_pad_attr_31_keeper_en_31_wd; |
| logic mio_pad_attr_31_schmitt_en_31_qs; |
| logic mio_pad_attr_31_schmitt_en_31_wd; |
| logic mio_pad_attr_31_od_en_31_qs; |
| logic mio_pad_attr_31_od_en_31_wd; |
| logic [1:0] mio_pad_attr_31_slew_rate_31_qs; |
| logic [1:0] mio_pad_attr_31_slew_rate_31_wd; |
| logic [3:0] mio_pad_attr_31_drive_strength_31_qs; |
| logic [3:0] mio_pad_attr_31_drive_strength_31_wd; |
| logic dio_pad_attr_regwen_0_we; |
| logic dio_pad_attr_regwen_0_qs; |
| logic dio_pad_attr_regwen_0_wd; |
| logic dio_pad_attr_regwen_1_we; |
| logic dio_pad_attr_regwen_1_qs; |
| logic dio_pad_attr_regwen_1_wd; |
| logic dio_pad_attr_regwen_2_we; |
| logic dio_pad_attr_regwen_2_qs; |
| logic dio_pad_attr_regwen_2_wd; |
| logic dio_pad_attr_regwen_3_we; |
| logic dio_pad_attr_regwen_3_qs; |
| logic dio_pad_attr_regwen_3_wd; |
| logic dio_pad_attr_regwen_4_we; |
| logic dio_pad_attr_regwen_4_qs; |
| logic dio_pad_attr_regwen_4_wd; |
| logic dio_pad_attr_regwen_5_we; |
| logic dio_pad_attr_regwen_5_qs; |
| logic dio_pad_attr_regwen_5_wd; |
| logic dio_pad_attr_regwen_6_we; |
| logic dio_pad_attr_regwen_6_qs; |
| logic dio_pad_attr_regwen_6_wd; |
| logic dio_pad_attr_regwen_7_we; |
| logic dio_pad_attr_regwen_7_qs; |
| logic dio_pad_attr_regwen_7_wd; |
| logic dio_pad_attr_regwen_8_we; |
| logic dio_pad_attr_regwen_8_qs; |
| logic dio_pad_attr_regwen_8_wd; |
| logic dio_pad_attr_regwen_9_we; |
| logic dio_pad_attr_regwen_9_qs; |
| logic dio_pad_attr_regwen_9_wd; |
| logic dio_pad_attr_regwen_10_we; |
| logic dio_pad_attr_regwen_10_qs; |
| logic dio_pad_attr_regwen_10_wd; |
| logic dio_pad_attr_regwen_11_we; |
| logic dio_pad_attr_regwen_11_qs; |
| logic dio_pad_attr_regwen_11_wd; |
| logic dio_pad_attr_regwen_12_we; |
| logic dio_pad_attr_regwen_12_qs; |
| logic dio_pad_attr_regwen_12_wd; |
| logic dio_pad_attr_regwen_13_we; |
| logic dio_pad_attr_regwen_13_qs; |
| logic dio_pad_attr_regwen_13_wd; |
| logic dio_pad_attr_regwen_14_we; |
| logic dio_pad_attr_regwen_14_qs; |
| logic dio_pad_attr_regwen_14_wd; |
| logic dio_pad_attr_regwen_15_we; |
| logic dio_pad_attr_regwen_15_qs; |
| logic dio_pad_attr_regwen_15_wd; |
| logic dio_pad_attr_0_re; |
| logic dio_pad_attr_0_we; |
| logic dio_pad_attr_0_invert_0_qs; |
| logic dio_pad_attr_0_invert_0_wd; |
| logic dio_pad_attr_0_virtual_od_en_0_qs; |
| logic dio_pad_attr_0_virtual_od_en_0_wd; |
| logic dio_pad_attr_0_pull_en_0_qs; |
| logic dio_pad_attr_0_pull_en_0_wd; |
| logic dio_pad_attr_0_pull_select_0_qs; |
| logic dio_pad_attr_0_pull_select_0_wd; |
| logic dio_pad_attr_0_keeper_en_0_qs; |
| logic dio_pad_attr_0_keeper_en_0_wd; |
| logic dio_pad_attr_0_schmitt_en_0_qs; |
| logic dio_pad_attr_0_schmitt_en_0_wd; |
| logic dio_pad_attr_0_od_en_0_qs; |
| logic dio_pad_attr_0_od_en_0_wd; |
| logic [1:0] dio_pad_attr_0_slew_rate_0_qs; |
| logic [1:0] dio_pad_attr_0_slew_rate_0_wd; |
| logic [3:0] dio_pad_attr_0_drive_strength_0_qs; |
| logic [3:0] dio_pad_attr_0_drive_strength_0_wd; |
| logic dio_pad_attr_1_re; |
| logic dio_pad_attr_1_we; |
| logic dio_pad_attr_1_invert_1_qs; |
| logic dio_pad_attr_1_invert_1_wd; |
| logic dio_pad_attr_1_virtual_od_en_1_qs; |
| logic dio_pad_attr_1_virtual_od_en_1_wd; |
| logic dio_pad_attr_1_pull_en_1_qs; |
| logic dio_pad_attr_1_pull_en_1_wd; |
| logic dio_pad_attr_1_pull_select_1_qs; |
| logic dio_pad_attr_1_pull_select_1_wd; |
| logic dio_pad_attr_1_keeper_en_1_qs; |
| logic dio_pad_attr_1_keeper_en_1_wd; |
| logic dio_pad_attr_1_schmitt_en_1_qs; |
| logic dio_pad_attr_1_schmitt_en_1_wd; |
| logic dio_pad_attr_1_od_en_1_qs; |
| logic dio_pad_attr_1_od_en_1_wd; |
| logic [1:0] dio_pad_attr_1_slew_rate_1_qs; |
| logic [1:0] dio_pad_attr_1_slew_rate_1_wd; |
| logic [3:0] dio_pad_attr_1_drive_strength_1_qs; |
| logic [3:0] dio_pad_attr_1_drive_strength_1_wd; |
| logic dio_pad_attr_2_re; |
| logic dio_pad_attr_2_we; |
| logic dio_pad_attr_2_invert_2_qs; |
| logic dio_pad_attr_2_invert_2_wd; |
| logic dio_pad_attr_2_virtual_od_en_2_qs; |
| logic dio_pad_attr_2_virtual_od_en_2_wd; |
| logic dio_pad_attr_2_pull_en_2_qs; |
| logic dio_pad_attr_2_pull_en_2_wd; |
| logic dio_pad_attr_2_pull_select_2_qs; |
| logic dio_pad_attr_2_pull_select_2_wd; |
| logic dio_pad_attr_2_keeper_en_2_qs; |
| logic dio_pad_attr_2_keeper_en_2_wd; |
| logic dio_pad_attr_2_schmitt_en_2_qs; |
| logic dio_pad_attr_2_schmitt_en_2_wd; |
| logic dio_pad_attr_2_od_en_2_qs; |
| logic dio_pad_attr_2_od_en_2_wd; |
| logic [1:0] dio_pad_attr_2_slew_rate_2_qs; |
| logic [1:0] dio_pad_attr_2_slew_rate_2_wd; |
| logic [3:0] dio_pad_attr_2_drive_strength_2_qs; |
| logic [3:0] dio_pad_attr_2_drive_strength_2_wd; |
| logic dio_pad_attr_3_re; |
| logic dio_pad_attr_3_we; |
| logic dio_pad_attr_3_invert_3_qs; |
| logic dio_pad_attr_3_invert_3_wd; |
| logic dio_pad_attr_3_virtual_od_en_3_qs; |
| logic dio_pad_attr_3_virtual_od_en_3_wd; |
| logic dio_pad_attr_3_pull_en_3_qs; |
| logic dio_pad_attr_3_pull_en_3_wd; |
| logic dio_pad_attr_3_pull_select_3_qs; |
| logic dio_pad_attr_3_pull_select_3_wd; |
| logic dio_pad_attr_3_keeper_en_3_qs; |
| logic dio_pad_attr_3_keeper_en_3_wd; |
| logic dio_pad_attr_3_schmitt_en_3_qs; |
| logic dio_pad_attr_3_schmitt_en_3_wd; |
| logic dio_pad_attr_3_od_en_3_qs; |
| logic dio_pad_attr_3_od_en_3_wd; |
| logic [1:0] dio_pad_attr_3_slew_rate_3_qs; |
| logic [1:0] dio_pad_attr_3_slew_rate_3_wd; |
| logic [3:0] dio_pad_attr_3_drive_strength_3_qs; |
| logic [3:0] dio_pad_attr_3_drive_strength_3_wd; |
| logic dio_pad_attr_4_re; |
| logic dio_pad_attr_4_we; |
| logic dio_pad_attr_4_invert_4_qs; |
| logic dio_pad_attr_4_invert_4_wd; |
| logic dio_pad_attr_4_virtual_od_en_4_qs; |
| logic dio_pad_attr_4_virtual_od_en_4_wd; |
| logic dio_pad_attr_4_pull_en_4_qs; |
| logic dio_pad_attr_4_pull_en_4_wd; |
| logic dio_pad_attr_4_pull_select_4_qs; |
| logic dio_pad_attr_4_pull_select_4_wd; |
| logic dio_pad_attr_4_keeper_en_4_qs; |
| logic dio_pad_attr_4_keeper_en_4_wd; |
| logic dio_pad_attr_4_schmitt_en_4_qs; |
| logic dio_pad_attr_4_schmitt_en_4_wd; |
| logic dio_pad_attr_4_od_en_4_qs; |
| logic dio_pad_attr_4_od_en_4_wd; |
| logic [1:0] dio_pad_attr_4_slew_rate_4_qs; |
| logic [1:0] dio_pad_attr_4_slew_rate_4_wd; |
| logic [3:0] dio_pad_attr_4_drive_strength_4_qs; |
| logic [3:0] dio_pad_attr_4_drive_strength_4_wd; |
| logic dio_pad_attr_5_re; |
| logic dio_pad_attr_5_we; |
| logic dio_pad_attr_5_invert_5_qs; |
| logic dio_pad_attr_5_invert_5_wd; |
| logic dio_pad_attr_5_virtual_od_en_5_qs; |
| logic dio_pad_attr_5_virtual_od_en_5_wd; |
| logic dio_pad_attr_5_pull_en_5_qs; |
| logic dio_pad_attr_5_pull_en_5_wd; |
| logic dio_pad_attr_5_pull_select_5_qs; |
| logic dio_pad_attr_5_pull_select_5_wd; |
| logic dio_pad_attr_5_keeper_en_5_qs; |
| logic dio_pad_attr_5_keeper_en_5_wd; |
| logic dio_pad_attr_5_schmitt_en_5_qs; |
| logic dio_pad_attr_5_schmitt_en_5_wd; |
| logic dio_pad_attr_5_od_en_5_qs; |
| logic dio_pad_attr_5_od_en_5_wd; |
| logic [1:0] dio_pad_attr_5_slew_rate_5_qs; |
| logic [1:0] dio_pad_attr_5_slew_rate_5_wd; |
| logic [3:0] dio_pad_attr_5_drive_strength_5_qs; |
| logic [3:0] dio_pad_attr_5_drive_strength_5_wd; |
| logic dio_pad_attr_6_re; |
| logic dio_pad_attr_6_we; |
| logic dio_pad_attr_6_invert_6_qs; |
| logic dio_pad_attr_6_invert_6_wd; |
| logic dio_pad_attr_6_virtual_od_en_6_qs; |
| logic dio_pad_attr_6_virtual_od_en_6_wd; |
| logic dio_pad_attr_6_pull_en_6_qs; |
| logic dio_pad_attr_6_pull_en_6_wd; |
| logic dio_pad_attr_6_pull_select_6_qs; |
| logic dio_pad_attr_6_pull_select_6_wd; |
| logic dio_pad_attr_6_keeper_en_6_qs; |
| logic dio_pad_attr_6_keeper_en_6_wd; |
| logic dio_pad_attr_6_schmitt_en_6_qs; |
| logic dio_pad_attr_6_schmitt_en_6_wd; |
| logic dio_pad_attr_6_od_en_6_qs; |
| logic dio_pad_attr_6_od_en_6_wd; |
| logic [1:0] dio_pad_attr_6_slew_rate_6_qs; |
| logic [1:0] dio_pad_attr_6_slew_rate_6_wd; |
| logic [3:0] dio_pad_attr_6_drive_strength_6_qs; |
| logic [3:0] dio_pad_attr_6_drive_strength_6_wd; |
| logic dio_pad_attr_7_re; |
| logic dio_pad_attr_7_we; |
| logic dio_pad_attr_7_invert_7_qs; |
| logic dio_pad_attr_7_invert_7_wd; |
| logic dio_pad_attr_7_virtual_od_en_7_qs; |
| logic dio_pad_attr_7_virtual_od_en_7_wd; |
| logic dio_pad_attr_7_pull_en_7_qs; |
| logic dio_pad_attr_7_pull_en_7_wd; |
| logic dio_pad_attr_7_pull_select_7_qs; |
| logic dio_pad_attr_7_pull_select_7_wd; |
| logic dio_pad_attr_7_keeper_en_7_qs; |
| logic dio_pad_attr_7_keeper_en_7_wd; |
| logic dio_pad_attr_7_schmitt_en_7_qs; |
| logic dio_pad_attr_7_schmitt_en_7_wd; |
| logic dio_pad_attr_7_od_en_7_qs; |
| logic dio_pad_attr_7_od_en_7_wd; |
| logic [1:0] dio_pad_attr_7_slew_rate_7_qs; |
| logic [1:0] dio_pad_attr_7_slew_rate_7_wd; |
| logic [3:0] dio_pad_attr_7_drive_strength_7_qs; |
| logic [3:0] dio_pad_attr_7_drive_strength_7_wd; |
| logic dio_pad_attr_8_re; |
| logic dio_pad_attr_8_we; |
| logic dio_pad_attr_8_invert_8_qs; |
| logic dio_pad_attr_8_invert_8_wd; |
| logic dio_pad_attr_8_virtual_od_en_8_qs; |
| logic dio_pad_attr_8_virtual_od_en_8_wd; |
| logic dio_pad_attr_8_pull_en_8_qs; |
| logic dio_pad_attr_8_pull_en_8_wd; |
| logic dio_pad_attr_8_pull_select_8_qs; |
| logic dio_pad_attr_8_pull_select_8_wd; |
| logic dio_pad_attr_8_keeper_en_8_qs; |
| logic dio_pad_attr_8_keeper_en_8_wd; |
| logic dio_pad_attr_8_schmitt_en_8_qs; |
| logic dio_pad_attr_8_schmitt_en_8_wd; |
| logic dio_pad_attr_8_od_en_8_qs; |
| logic dio_pad_attr_8_od_en_8_wd; |
| logic [1:0] dio_pad_attr_8_slew_rate_8_qs; |
| logic [1:0] dio_pad_attr_8_slew_rate_8_wd; |
| logic [3:0] dio_pad_attr_8_drive_strength_8_qs; |
| logic [3:0] dio_pad_attr_8_drive_strength_8_wd; |
| logic dio_pad_attr_9_re; |
| logic dio_pad_attr_9_we; |
| logic dio_pad_attr_9_invert_9_qs; |
| logic dio_pad_attr_9_invert_9_wd; |
| logic dio_pad_attr_9_virtual_od_en_9_qs; |
| logic dio_pad_attr_9_virtual_od_en_9_wd; |
| logic dio_pad_attr_9_pull_en_9_qs; |
| logic dio_pad_attr_9_pull_en_9_wd; |
| logic dio_pad_attr_9_pull_select_9_qs; |
| logic dio_pad_attr_9_pull_select_9_wd; |
| logic dio_pad_attr_9_keeper_en_9_qs; |
| logic dio_pad_attr_9_keeper_en_9_wd; |
| logic dio_pad_attr_9_schmitt_en_9_qs; |
| logic dio_pad_attr_9_schmitt_en_9_wd; |
| logic dio_pad_attr_9_od_en_9_qs; |
| logic dio_pad_attr_9_od_en_9_wd; |
| logic [1:0] dio_pad_attr_9_slew_rate_9_qs; |
| logic [1:0] dio_pad_attr_9_slew_rate_9_wd; |
| logic [3:0] dio_pad_attr_9_drive_strength_9_qs; |
| logic [3:0] dio_pad_attr_9_drive_strength_9_wd; |
| logic dio_pad_attr_10_re; |
| logic dio_pad_attr_10_we; |
| logic dio_pad_attr_10_invert_10_qs; |
| logic dio_pad_attr_10_invert_10_wd; |
| logic dio_pad_attr_10_virtual_od_en_10_qs; |
| logic dio_pad_attr_10_virtual_od_en_10_wd; |
| logic dio_pad_attr_10_pull_en_10_qs; |
| logic dio_pad_attr_10_pull_en_10_wd; |
| logic dio_pad_attr_10_pull_select_10_qs; |
| logic dio_pad_attr_10_pull_select_10_wd; |
| logic dio_pad_attr_10_keeper_en_10_qs; |
| logic dio_pad_attr_10_keeper_en_10_wd; |
| logic dio_pad_attr_10_schmitt_en_10_qs; |
| logic dio_pad_attr_10_schmitt_en_10_wd; |
| logic dio_pad_attr_10_od_en_10_qs; |
| logic dio_pad_attr_10_od_en_10_wd; |
| logic [1:0] dio_pad_attr_10_slew_rate_10_qs; |
| logic [1:0] dio_pad_attr_10_slew_rate_10_wd; |
| logic [3:0] dio_pad_attr_10_drive_strength_10_qs; |
| logic [3:0] dio_pad_attr_10_drive_strength_10_wd; |
| logic dio_pad_attr_11_re; |
| logic dio_pad_attr_11_we; |
| logic dio_pad_attr_11_invert_11_qs; |
| logic dio_pad_attr_11_invert_11_wd; |
| logic dio_pad_attr_11_virtual_od_en_11_qs; |
| logic dio_pad_attr_11_virtual_od_en_11_wd; |
| logic dio_pad_attr_11_pull_en_11_qs; |
| logic dio_pad_attr_11_pull_en_11_wd; |
| logic dio_pad_attr_11_pull_select_11_qs; |
| logic dio_pad_attr_11_pull_select_11_wd; |
| logic dio_pad_attr_11_keeper_en_11_qs; |
| logic dio_pad_attr_11_keeper_en_11_wd; |
| logic dio_pad_attr_11_schmitt_en_11_qs; |
| logic dio_pad_attr_11_schmitt_en_11_wd; |
| logic dio_pad_attr_11_od_en_11_qs; |
| logic dio_pad_attr_11_od_en_11_wd; |
| logic [1:0] dio_pad_attr_11_slew_rate_11_qs; |
| logic [1:0] dio_pad_attr_11_slew_rate_11_wd; |
| logic [3:0] dio_pad_attr_11_drive_strength_11_qs; |
| logic [3:0] dio_pad_attr_11_drive_strength_11_wd; |
| logic dio_pad_attr_12_re; |
| logic dio_pad_attr_12_we; |
| logic dio_pad_attr_12_invert_12_qs; |
| logic dio_pad_attr_12_invert_12_wd; |
| logic dio_pad_attr_12_virtual_od_en_12_qs; |
| logic dio_pad_attr_12_virtual_od_en_12_wd; |
| logic dio_pad_attr_12_pull_en_12_qs; |
| logic dio_pad_attr_12_pull_en_12_wd; |
| logic dio_pad_attr_12_pull_select_12_qs; |
| logic dio_pad_attr_12_pull_select_12_wd; |
| logic dio_pad_attr_12_keeper_en_12_qs; |
| logic dio_pad_attr_12_keeper_en_12_wd; |
| logic dio_pad_attr_12_schmitt_en_12_qs; |
| logic dio_pad_attr_12_schmitt_en_12_wd; |
| logic dio_pad_attr_12_od_en_12_qs; |
| logic dio_pad_attr_12_od_en_12_wd; |
| logic [1:0] dio_pad_attr_12_slew_rate_12_qs; |
| logic [1:0] dio_pad_attr_12_slew_rate_12_wd; |
| logic [3:0] dio_pad_attr_12_drive_strength_12_qs; |
| logic [3:0] dio_pad_attr_12_drive_strength_12_wd; |
| logic dio_pad_attr_13_re; |
| logic dio_pad_attr_13_we; |
| logic dio_pad_attr_13_invert_13_qs; |
| logic dio_pad_attr_13_invert_13_wd; |
| logic dio_pad_attr_13_virtual_od_en_13_qs; |
| logic dio_pad_attr_13_virtual_od_en_13_wd; |
| logic dio_pad_attr_13_pull_en_13_qs; |
| logic dio_pad_attr_13_pull_en_13_wd; |
| logic dio_pad_attr_13_pull_select_13_qs; |
| logic dio_pad_attr_13_pull_select_13_wd; |
| logic dio_pad_attr_13_keeper_en_13_qs; |
| logic dio_pad_attr_13_keeper_en_13_wd; |
| logic dio_pad_attr_13_schmitt_en_13_qs; |
| logic dio_pad_attr_13_schmitt_en_13_wd; |
| logic dio_pad_attr_13_od_en_13_qs; |
| logic dio_pad_attr_13_od_en_13_wd; |
| logic [1:0] dio_pad_attr_13_slew_rate_13_qs; |
| logic [1:0] dio_pad_attr_13_slew_rate_13_wd; |
| logic [3:0] dio_pad_attr_13_drive_strength_13_qs; |
| logic [3:0] dio_pad_attr_13_drive_strength_13_wd; |
| logic dio_pad_attr_14_re; |
| logic dio_pad_attr_14_we; |
| logic dio_pad_attr_14_invert_14_qs; |
| logic dio_pad_attr_14_invert_14_wd; |
| logic dio_pad_attr_14_virtual_od_en_14_qs; |
| logic dio_pad_attr_14_virtual_od_en_14_wd; |
| logic dio_pad_attr_14_pull_en_14_qs; |
| logic dio_pad_attr_14_pull_en_14_wd; |
| logic dio_pad_attr_14_pull_select_14_qs; |
| logic dio_pad_attr_14_pull_select_14_wd; |
| logic dio_pad_attr_14_keeper_en_14_qs; |
| logic dio_pad_attr_14_keeper_en_14_wd; |
| logic dio_pad_attr_14_schmitt_en_14_qs; |
| logic dio_pad_attr_14_schmitt_en_14_wd; |
| logic dio_pad_attr_14_od_en_14_qs; |
| logic dio_pad_attr_14_od_en_14_wd; |
| logic [1:0] dio_pad_attr_14_slew_rate_14_qs; |
| logic [1:0] dio_pad_attr_14_slew_rate_14_wd; |
| logic [3:0] dio_pad_attr_14_drive_strength_14_qs; |
| logic [3:0] dio_pad_attr_14_drive_strength_14_wd; |
| logic dio_pad_attr_15_re; |
| logic dio_pad_attr_15_we; |
| logic dio_pad_attr_15_invert_15_qs; |
| logic dio_pad_attr_15_invert_15_wd; |
| logic dio_pad_attr_15_virtual_od_en_15_qs; |
| logic dio_pad_attr_15_virtual_od_en_15_wd; |
| logic dio_pad_attr_15_pull_en_15_qs; |
| logic dio_pad_attr_15_pull_en_15_wd; |
| logic dio_pad_attr_15_pull_select_15_qs; |
| logic dio_pad_attr_15_pull_select_15_wd; |
| logic dio_pad_attr_15_keeper_en_15_qs; |
| logic dio_pad_attr_15_keeper_en_15_wd; |
| logic dio_pad_attr_15_schmitt_en_15_qs; |
| logic dio_pad_attr_15_schmitt_en_15_wd; |
| logic dio_pad_attr_15_od_en_15_qs; |
| logic dio_pad_attr_15_od_en_15_wd; |
| logic [1:0] dio_pad_attr_15_slew_rate_15_qs; |
| logic [1:0] dio_pad_attr_15_slew_rate_15_wd; |
| logic [3:0] dio_pad_attr_15_drive_strength_15_qs; |
| logic [3:0] dio_pad_attr_15_drive_strength_15_wd; |
| logic mio_pad_sleep_status_we; |
| logic mio_pad_sleep_status_en_0_qs; |
| logic mio_pad_sleep_status_en_0_wd; |
| logic mio_pad_sleep_status_en_1_qs; |
| logic mio_pad_sleep_status_en_1_wd; |
| logic mio_pad_sleep_status_en_2_qs; |
| logic mio_pad_sleep_status_en_2_wd; |
| logic mio_pad_sleep_status_en_3_qs; |
| logic mio_pad_sleep_status_en_3_wd; |
| logic mio_pad_sleep_status_en_4_qs; |
| logic mio_pad_sleep_status_en_4_wd; |
| logic mio_pad_sleep_status_en_5_qs; |
| logic mio_pad_sleep_status_en_5_wd; |
| logic mio_pad_sleep_status_en_6_qs; |
| logic mio_pad_sleep_status_en_6_wd; |
| logic mio_pad_sleep_status_en_7_qs; |
| logic mio_pad_sleep_status_en_7_wd; |
| logic mio_pad_sleep_status_en_8_qs; |
| logic mio_pad_sleep_status_en_8_wd; |
| logic mio_pad_sleep_status_en_9_qs; |
| logic mio_pad_sleep_status_en_9_wd; |
| logic mio_pad_sleep_status_en_10_qs; |
| logic mio_pad_sleep_status_en_10_wd; |
| logic mio_pad_sleep_status_en_11_qs; |
| logic mio_pad_sleep_status_en_11_wd; |
| logic mio_pad_sleep_status_en_12_qs; |
| logic mio_pad_sleep_status_en_12_wd; |
| logic mio_pad_sleep_status_en_13_qs; |
| logic mio_pad_sleep_status_en_13_wd; |
| logic mio_pad_sleep_status_en_14_qs; |
| logic mio_pad_sleep_status_en_14_wd; |
| logic mio_pad_sleep_status_en_15_qs; |
| logic mio_pad_sleep_status_en_15_wd; |
| logic mio_pad_sleep_status_en_16_qs; |
| logic mio_pad_sleep_status_en_16_wd; |
| logic mio_pad_sleep_status_en_17_qs; |
| logic mio_pad_sleep_status_en_17_wd; |
| logic mio_pad_sleep_status_en_18_qs; |
| logic mio_pad_sleep_status_en_18_wd; |
| logic mio_pad_sleep_status_en_19_qs; |
| logic mio_pad_sleep_status_en_19_wd; |
| logic mio_pad_sleep_status_en_20_qs; |
| logic mio_pad_sleep_status_en_20_wd; |
| logic mio_pad_sleep_status_en_21_qs; |
| logic mio_pad_sleep_status_en_21_wd; |
| logic mio_pad_sleep_status_en_22_qs; |
| logic mio_pad_sleep_status_en_22_wd; |
| logic mio_pad_sleep_status_en_23_qs; |
| logic mio_pad_sleep_status_en_23_wd; |
| logic mio_pad_sleep_status_en_24_qs; |
| logic mio_pad_sleep_status_en_24_wd; |
| logic mio_pad_sleep_status_en_25_qs; |
| logic mio_pad_sleep_status_en_25_wd; |
| logic mio_pad_sleep_status_en_26_qs; |
| logic mio_pad_sleep_status_en_26_wd; |
| logic mio_pad_sleep_status_en_27_qs; |
| logic mio_pad_sleep_status_en_27_wd; |
| logic mio_pad_sleep_status_en_28_qs; |
| logic mio_pad_sleep_status_en_28_wd; |
| logic mio_pad_sleep_status_en_29_qs; |
| logic mio_pad_sleep_status_en_29_wd; |
| logic mio_pad_sleep_status_en_30_qs; |
| logic mio_pad_sleep_status_en_30_wd; |
| logic mio_pad_sleep_status_en_31_qs; |
| logic mio_pad_sleep_status_en_31_wd; |
| logic mio_pad_sleep_regwen_0_we; |
| logic mio_pad_sleep_regwen_0_qs; |
| logic mio_pad_sleep_regwen_0_wd; |
| logic mio_pad_sleep_regwen_1_we; |
| logic mio_pad_sleep_regwen_1_qs; |
| logic mio_pad_sleep_regwen_1_wd; |
| logic mio_pad_sleep_regwen_2_we; |
| logic mio_pad_sleep_regwen_2_qs; |
| logic mio_pad_sleep_regwen_2_wd; |
| logic mio_pad_sleep_regwen_3_we; |
| logic mio_pad_sleep_regwen_3_qs; |
| logic mio_pad_sleep_regwen_3_wd; |
| logic mio_pad_sleep_regwen_4_we; |
| logic mio_pad_sleep_regwen_4_qs; |
| logic mio_pad_sleep_regwen_4_wd; |
| logic mio_pad_sleep_regwen_5_we; |
| logic mio_pad_sleep_regwen_5_qs; |
| logic mio_pad_sleep_regwen_5_wd; |
| logic mio_pad_sleep_regwen_6_we; |
| logic mio_pad_sleep_regwen_6_qs; |
| logic mio_pad_sleep_regwen_6_wd; |
| logic mio_pad_sleep_regwen_7_we; |
| logic mio_pad_sleep_regwen_7_qs; |
| logic mio_pad_sleep_regwen_7_wd; |
| logic mio_pad_sleep_regwen_8_we; |
| logic mio_pad_sleep_regwen_8_qs; |
| logic mio_pad_sleep_regwen_8_wd; |
| logic mio_pad_sleep_regwen_9_we; |
| logic mio_pad_sleep_regwen_9_qs; |
| logic mio_pad_sleep_regwen_9_wd; |
| logic mio_pad_sleep_regwen_10_we; |
| logic mio_pad_sleep_regwen_10_qs; |
| logic mio_pad_sleep_regwen_10_wd; |
| logic mio_pad_sleep_regwen_11_we; |
| logic mio_pad_sleep_regwen_11_qs; |
| logic mio_pad_sleep_regwen_11_wd; |
| logic mio_pad_sleep_regwen_12_we; |
| logic mio_pad_sleep_regwen_12_qs; |
| logic mio_pad_sleep_regwen_12_wd; |
| logic mio_pad_sleep_regwen_13_we; |
| logic mio_pad_sleep_regwen_13_qs; |
| logic mio_pad_sleep_regwen_13_wd; |
| logic mio_pad_sleep_regwen_14_we; |
| logic mio_pad_sleep_regwen_14_qs; |
| logic mio_pad_sleep_regwen_14_wd; |
| logic mio_pad_sleep_regwen_15_we; |
| logic mio_pad_sleep_regwen_15_qs; |
| logic mio_pad_sleep_regwen_15_wd; |
| logic mio_pad_sleep_regwen_16_we; |
| logic mio_pad_sleep_regwen_16_qs; |
| logic mio_pad_sleep_regwen_16_wd; |
| logic mio_pad_sleep_regwen_17_we; |
| logic mio_pad_sleep_regwen_17_qs; |
| logic mio_pad_sleep_regwen_17_wd; |
| logic mio_pad_sleep_regwen_18_we; |
| logic mio_pad_sleep_regwen_18_qs; |
| logic mio_pad_sleep_regwen_18_wd; |
| logic mio_pad_sleep_regwen_19_we; |
| logic mio_pad_sleep_regwen_19_qs; |
| logic mio_pad_sleep_regwen_19_wd; |
| logic mio_pad_sleep_regwen_20_we; |
| logic mio_pad_sleep_regwen_20_qs; |
| logic mio_pad_sleep_regwen_20_wd; |
| logic mio_pad_sleep_regwen_21_we; |
| logic mio_pad_sleep_regwen_21_qs; |
| logic mio_pad_sleep_regwen_21_wd; |
| logic mio_pad_sleep_regwen_22_we; |
| logic mio_pad_sleep_regwen_22_qs; |
| logic mio_pad_sleep_regwen_22_wd; |
| logic mio_pad_sleep_regwen_23_we; |
| logic mio_pad_sleep_regwen_23_qs; |
| logic mio_pad_sleep_regwen_23_wd; |
| logic mio_pad_sleep_regwen_24_we; |
| logic mio_pad_sleep_regwen_24_qs; |
| logic mio_pad_sleep_regwen_24_wd; |
| logic mio_pad_sleep_regwen_25_we; |
| logic mio_pad_sleep_regwen_25_qs; |
| logic mio_pad_sleep_regwen_25_wd; |
| logic mio_pad_sleep_regwen_26_we; |
| logic mio_pad_sleep_regwen_26_qs; |
| logic mio_pad_sleep_regwen_26_wd; |
| logic mio_pad_sleep_regwen_27_we; |
| logic mio_pad_sleep_regwen_27_qs; |
| logic mio_pad_sleep_regwen_27_wd; |
| logic mio_pad_sleep_regwen_28_we; |
| logic mio_pad_sleep_regwen_28_qs; |
| logic mio_pad_sleep_regwen_28_wd; |
| logic mio_pad_sleep_regwen_29_we; |
| logic mio_pad_sleep_regwen_29_qs; |
| logic mio_pad_sleep_regwen_29_wd; |
| logic mio_pad_sleep_regwen_30_we; |
| logic mio_pad_sleep_regwen_30_qs; |
| logic mio_pad_sleep_regwen_30_wd; |
| logic mio_pad_sleep_regwen_31_we; |
| logic mio_pad_sleep_regwen_31_qs; |
| logic mio_pad_sleep_regwen_31_wd; |
| logic mio_pad_sleep_en_0_we; |
| logic mio_pad_sleep_en_0_qs; |
| logic mio_pad_sleep_en_0_wd; |
| logic mio_pad_sleep_en_1_we; |
| logic mio_pad_sleep_en_1_qs; |
| logic mio_pad_sleep_en_1_wd; |
| logic mio_pad_sleep_en_2_we; |
| logic mio_pad_sleep_en_2_qs; |
| logic mio_pad_sleep_en_2_wd; |
| logic mio_pad_sleep_en_3_we; |
| logic mio_pad_sleep_en_3_qs; |
| logic mio_pad_sleep_en_3_wd; |
| logic mio_pad_sleep_en_4_we; |
| logic mio_pad_sleep_en_4_qs; |
| logic mio_pad_sleep_en_4_wd; |
| logic mio_pad_sleep_en_5_we; |
| logic mio_pad_sleep_en_5_qs; |
| logic mio_pad_sleep_en_5_wd; |
| logic mio_pad_sleep_en_6_we; |
| logic mio_pad_sleep_en_6_qs; |
| logic mio_pad_sleep_en_6_wd; |
| logic mio_pad_sleep_en_7_we; |
| logic mio_pad_sleep_en_7_qs; |
| logic mio_pad_sleep_en_7_wd; |
| logic mio_pad_sleep_en_8_we; |
| logic mio_pad_sleep_en_8_qs; |
| logic mio_pad_sleep_en_8_wd; |
| logic mio_pad_sleep_en_9_we; |
| logic mio_pad_sleep_en_9_qs; |
| logic mio_pad_sleep_en_9_wd; |
| logic mio_pad_sleep_en_10_we; |
| logic mio_pad_sleep_en_10_qs; |
| logic mio_pad_sleep_en_10_wd; |
| logic mio_pad_sleep_en_11_we; |
| logic mio_pad_sleep_en_11_qs; |
| logic mio_pad_sleep_en_11_wd; |
| logic mio_pad_sleep_en_12_we; |
| logic mio_pad_sleep_en_12_qs; |
| logic mio_pad_sleep_en_12_wd; |
| logic mio_pad_sleep_en_13_we; |
| logic mio_pad_sleep_en_13_qs; |
| logic mio_pad_sleep_en_13_wd; |
| logic mio_pad_sleep_en_14_we; |
| logic mio_pad_sleep_en_14_qs; |
| logic mio_pad_sleep_en_14_wd; |
| logic mio_pad_sleep_en_15_we; |
| logic mio_pad_sleep_en_15_qs; |
| logic mio_pad_sleep_en_15_wd; |
| logic mio_pad_sleep_en_16_we; |
| logic mio_pad_sleep_en_16_qs; |
| logic mio_pad_sleep_en_16_wd; |
| logic mio_pad_sleep_en_17_we; |
| logic mio_pad_sleep_en_17_qs; |
| logic mio_pad_sleep_en_17_wd; |
| logic mio_pad_sleep_en_18_we; |
| logic mio_pad_sleep_en_18_qs; |
| logic mio_pad_sleep_en_18_wd; |
| logic mio_pad_sleep_en_19_we; |
| logic mio_pad_sleep_en_19_qs; |
| logic mio_pad_sleep_en_19_wd; |
| logic mio_pad_sleep_en_20_we; |
| logic mio_pad_sleep_en_20_qs; |
| logic mio_pad_sleep_en_20_wd; |
| logic mio_pad_sleep_en_21_we; |
| logic mio_pad_sleep_en_21_qs; |
| logic mio_pad_sleep_en_21_wd; |
| logic mio_pad_sleep_en_22_we; |
| logic mio_pad_sleep_en_22_qs; |
| logic mio_pad_sleep_en_22_wd; |
| logic mio_pad_sleep_en_23_we; |
| logic mio_pad_sleep_en_23_qs; |
| logic mio_pad_sleep_en_23_wd; |
| logic mio_pad_sleep_en_24_we; |
| logic mio_pad_sleep_en_24_qs; |
| logic mio_pad_sleep_en_24_wd; |
| logic mio_pad_sleep_en_25_we; |
| logic mio_pad_sleep_en_25_qs; |
| logic mio_pad_sleep_en_25_wd; |
| logic mio_pad_sleep_en_26_we; |
| logic mio_pad_sleep_en_26_qs; |
| logic mio_pad_sleep_en_26_wd; |
| logic mio_pad_sleep_en_27_we; |
| logic mio_pad_sleep_en_27_qs; |
| logic mio_pad_sleep_en_27_wd; |
| logic mio_pad_sleep_en_28_we; |
| logic mio_pad_sleep_en_28_qs; |
| logic mio_pad_sleep_en_28_wd; |
| logic mio_pad_sleep_en_29_we; |
| logic mio_pad_sleep_en_29_qs; |
| logic mio_pad_sleep_en_29_wd; |
| logic mio_pad_sleep_en_30_we; |
| logic mio_pad_sleep_en_30_qs; |
| logic mio_pad_sleep_en_30_wd; |
| logic mio_pad_sleep_en_31_we; |
| logic mio_pad_sleep_en_31_qs; |
| logic mio_pad_sleep_en_31_wd; |
| logic mio_pad_sleep_mode_0_we; |
| logic [1:0] mio_pad_sleep_mode_0_qs; |
| logic [1:0] mio_pad_sleep_mode_0_wd; |
| logic mio_pad_sleep_mode_1_we; |
| logic [1:0] mio_pad_sleep_mode_1_qs; |
| logic [1:0] mio_pad_sleep_mode_1_wd; |
| logic mio_pad_sleep_mode_2_we; |
| logic [1:0] mio_pad_sleep_mode_2_qs; |
| logic [1:0] mio_pad_sleep_mode_2_wd; |
| logic mio_pad_sleep_mode_3_we; |
| logic [1:0] mio_pad_sleep_mode_3_qs; |
| logic [1:0] mio_pad_sleep_mode_3_wd; |
| logic mio_pad_sleep_mode_4_we; |
| logic [1:0] mio_pad_sleep_mode_4_qs; |
| logic [1:0] mio_pad_sleep_mode_4_wd; |
| logic mio_pad_sleep_mode_5_we; |
| logic [1:0] mio_pad_sleep_mode_5_qs; |
| logic [1:0] mio_pad_sleep_mode_5_wd; |
| logic mio_pad_sleep_mode_6_we; |
| logic [1:0] mio_pad_sleep_mode_6_qs; |
| logic [1:0] mio_pad_sleep_mode_6_wd; |
| logic mio_pad_sleep_mode_7_we; |
| logic [1:0] mio_pad_sleep_mode_7_qs; |
| logic [1:0] mio_pad_sleep_mode_7_wd; |
| logic mio_pad_sleep_mode_8_we; |
| logic [1:0] mio_pad_sleep_mode_8_qs; |
| logic [1:0] mio_pad_sleep_mode_8_wd; |
| logic mio_pad_sleep_mode_9_we; |
| logic [1:0] mio_pad_sleep_mode_9_qs; |
| logic [1:0] mio_pad_sleep_mode_9_wd; |
| logic mio_pad_sleep_mode_10_we; |
| logic [1:0] mio_pad_sleep_mode_10_qs; |
| logic [1:0] mio_pad_sleep_mode_10_wd; |
| logic mio_pad_sleep_mode_11_we; |
| logic [1:0] mio_pad_sleep_mode_11_qs; |
| logic [1:0] mio_pad_sleep_mode_11_wd; |
| logic mio_pad_sleep_mode_12_we; |
| logic [1:0] mio_pad_sleep_mode_12_qs; |
| logic [1:0] mio_pad_sleep_mode_12_wd; |
| logic mio_pad_sleep_mode_13_we; |
| logic [1:0] mio_pad_sleep_mode_13_qs; |
| logic [1:0] mio_pad_sleep_mode_13_wd; |
| logic mio_pad_sleep_mode_14_we; |
| logic [1:0] mio_pad_sleep_mode_14_qs; |
| logic [1:0] mio_pad_sleep_mode_14_wd; |
| logic mio_pad_sleep_mode_15_we; |
| logic [1:0] mio_pad_sleep_mode_15_qs; |
| logic [1:0] mio_pad_sleep_mode_15_wd; |
| logic mio_pad_sleep_mode_16_we; |
| logic [1:0] mio_pad_sleep_mode_16_qs; |
| logic [1:0] mio_pad_sleep_mode_16_wd; |
| logic mio_pad_sleep_mode_17_we; |
| logic [1:0] mio_pad_sleep_mode_17_qs; |
| logic [1:0] mio_pad_sleep_mode_17_wd; |
| logic mio_pad_sleep_mode_18_we; |
| logic [1:0] mio_pad_sleep_mode_18_qs; |
| logic [1:0] mio_pad_sleep_mode_18_wd; |
| logic mio_pad_sleep_mode_19_we; |
| logic [1:0] mio_pad_sleep_mode_19_qs; |
| logic [1:0] mio_pad_sleep_mode_19_wd; |
| logic mio_pad_sleep_mode_20_we; |
| logic [1:0] mio_pad_sleep_mode_20_qs; |
| logic [1:0] mio_pad_sleep_mode_20_wd; |
| logic mio_pad_sleep_mode_21_we; |
| logic [1:0] mio_pad_sleep_mode_21_qs; |
| logic [1:0] mio_pad_sleep_mode_21_wd; |
| logic mio_pad_sleep_mode_22_we; |
| logic [1:0] mio_pad_sleep_mode_22_qs; |
| logic [1:0] mio_pad_sleep_mode_22_wd; |
| logic mio_pad_sleep_mode_23_we; |
| logic [1:0] mio_pad_sleep_mode_23_qs; |
| logic [1:0] mio_pad_sleep_mode_23_wd; |
| logic mio_pad_sleep_mode_24_we; |
| logic [1:0] mio_pad_sleep_mode_24_qs; |
| logic [1:0] mio_pad_sleep_mode_24_wd; |
| logic mio_pad_sleep_mode_25_we; |
| logic [1:0] mio_pad_sleep_mode_25_qs; |
| logic [1:0] mio_pad_sleep_mode_25_wd; |
| logic mio_pad_sleep_mode_26_we; |
| logic [1:0] mio_pad_sleep_mode_26_qs; |
| logic [1:0] mio_pad_sleep_mode_26_wd; |
| logic mio_pad_sleep_mode_27_we; |
| logic [1:0] mio_pad_sleep_mode_27_qs; |
| logic [1:0] mio_pad_sleep_mode_27_wd; |
| logic mio_pad_sleep_mode_28_we; |
| logic [1:0] mio_pad_sleep_mode_28_qs; |
| logic [1:0] mio_pad_sleep_mode_28_wd; |
| logic mio_pad_sleep_mode_29_we; |
| logic [1:0] mio_pad_sleep_mode_29_qs; |
| logic [1:0] mio_pad_sleep_mode_29_wd; |
| logic mio_pad_sleep_mode_30_we; |
| logic [1:0] mio_pad_sleep_mode_30_qs; |
| logic [1:0] mio_pad_sleep_mode_30_wd; |
| logic mio_pad_sleep_mode_31_we; |
| logic [1:0] mio_pad_sleep_mode_31_qs; |
| logic [1:0] mio_pad_sleep_mode_31_wd; |
| logic dio_pad_sleep_status_we; |
| logic dio_pad_sleep_status_en_0_qs; |
| logic dio_pad_sleep_status_en_0_wd; |
| logic dio_pad_sleep_status_en_1_qs; |
| logic dio_pad_sleep_status_en_1_wd; |
| logic dio_pad_sleep_status_en_2_qs; |
| logic dio_pad_sleep_status_en_2_wd; |
| logic dio_pad_sleep_status_en_3_qs; |
| logic dio_pad_sleep_status_en_3_wd; |
| logic dio_pad_sleep_status_en_4_qs; |
| logic dio_pad_sleep_status_en_4_wd; |
| logic dio_pad_sleep_status_en_5_qs; |
| logic dio_pad_sleep_status_en_5_wd; |
| logic dio_pad_sleep_status_en_6_qs; |
| logic dio_pad_sleep_status_en_6_wd; |
| logic dio_pad_sleep_status_en_7_qs; |
| logic dio_pad_sleep_status_en_7_wd; |
| logic dio_pad_sleep_status_en_8_qs; |
| logic dio_pad_sleep_status_en_8_wd; |
| logic dio_pad_sleep_status_en_9_qs; |
| logic dio_pad_sleep_status_en_9_wd; |
| logic dio_pad_sleep_status_en_10_qs; |
| logic dio_pad_sleep_status_en_10_wd; |
| logic dio_pad_sleep_status_en_11_qs; |
| logic dio_pad_sleep_status_en_11_wd; |
| logic dio_pad_sleep_status_en_12_qs; |
| logic dio_pad_sleep_status_en_12_wd; |
| logic dio_pad_sleep_status_en_13_qs; |
| logic dio_pad_sleep_status_en_13_wd; |
| logic dio_pad_sleep_status_en_14_qs; |
| logic dio_pad_sleep_status_en_14_wd; |
| logic dio_pad_sleep_status_en_15_qs; |
| logic dio_pad_sleep_status_en_15_wd; |
| logic dio_pad_sleep_regwen_0_we; |
| logic dio_pad_sleep_regwen_0_qs; |
| logic dio_pad_sleep_regwen_0_wd; |
| logic dio_pad_sleep_regwen_1_we; |
| logic dio_pad_sleep_regwen_1_qs; |
| logic dio_pad_sleep_regwen_1_wd; |
| logic dio_pad_sleep_regwen_2_we; |
| logic dio_pad_sleep_regwen_2_qs; |
| logic dio_pad_sleep_regwen_2_wd; |
| logic dio_pad_sleep_regwen_3_we; |
| logic dio_pad_sleep_regwen_3_qs; |
| logic dio_pad_sleep_regwen_3_wd; |
| logic dio_pad_sleep_regwen_4_we; |
| logic dio_pad_sleep_regwen_4_qs; |
| logic dio_pad_sleep_regwen_4_wd; |
| logic dio_pad_sleep_regwen_5_we; |
| logic dio_pad_sleep_regwen_5_qs; |
| logic dio_pad_sleep_regwen_5_wd; |
| logic dio_pad_sleep_regwen_6_we; |
| logic dio_pad_sleep_regwen_6_qs; |
| logic dio_pad_sleep_regwen_6_wd; |
| logic dio_pad_sleep_regwen_7_we; |
| logic dio_pad_sleep_regwen_7_qs; |
| logic dio_pad_sleep_regwen_7_wd; |
| logic dio_pad_sleep_regwen_8_we; |
| logic dio_pad_sleep_regwen_8_qs; |
| logic dio_pad_sleep_regwen_8_wd; |
| logic dio_pad_sleep_regwen_9_we; |
| logic dio_pad_sleep_regwen_9_qs; |
| logic dio_pad_sleep_regwen_9_wd; |
| logic dio_pad_sleep_regwen_10_we; |
| logic dio_pad_sleep_regwen_10_qs; |
| logic dio_pad_sleep_regwen_10_wd; |
| logic dio_pad_sleep_regwen_11_we; |
| logic dio_pad_sleep_regwen_11_qs; |
| logic dio_pad_sleep_regwen_11_wd; |
| logic dio_pad_sleep_regwen_12_we; |
| logic dio_pad_sleep_regwen_12_qs; |
| logic dio_pad_sleep_regwen_12_wd; |
| logic dio_pad_sleep_regwen_13_we; |
| logic dio_pad_sleep_regwen_13_qs; |
| logic dio_pad_sleep_regwen_13_wd; |
| logic dio_pad_sleep_regwen_14_we; |
| logic dio_pad_sleep_regwen_14_qs; |
| logic dio_pad_sleep_regwen_14_wd; |
| logic dio_pad_sleep_regwen_15_we; |
| logic dio_pad_sleep_regwen_15_qs; |
| logic dio_pad_sleep_regwen_15_wd; |
| logic dio_pad_sleep_en_0_we; |
| logic dio_pad_sleep_en_0_qs; |
| logic dio_pad_sleep_en_0_wd; |
| logic dio_pad_sleep_en_1_we; |
| logic dio_pad_sleep_en_1_qs; |
| logic dio_pad_sleep_en_1_wd; |
| logic dio_pad_sleep_en_2_we; |
| logic dio_pad_sleep_en_2_qs; |
| logic dio_pad_sleep_en_2_wd; |
| logic dio_pad_sleep_en_3_we; |
| logic dio_pad_sleep_en_3_qs; |
| logic dio_pad_sleep_en_3_wd; |
| logic dio_pad_sleep_en_4_we; |
| logic dio_pad_sleep_en_4_qs; |
| logic dio_pad_sleep_en_4_wd; |
| logic dio_pad_sleep_en_5_we; |
| logic dio_pad_sleep_en_5_qs; |
| logic dio_pad_sleep_en_5_wd; |
| logic dio_pad_sleep_en_6_we; |
| logic dio_pad_sleep_en_6_qs; |
| logic dio_pad_sleep_en_6_wd; |
| logic dio_pad_sleep_en_7_we; |
| logic dio_pad_sleep_en_7_qs; |
| logic dio_pad_sleep_en_7_wd; |
| logic dio_pad_sleep_en_8_we; |
| logic dio_pad_sleep_en_8_qs; |
| logic dio_pad_sleep_en_8_wd; |
| logic dio_pad_sleep_en_9_we; |
| logic dio_pad_sleep_en_9_qs; |
| logic dio_pad_sleep_en_9_wd; |
| logic dio_pad_sleep_en_10_we; |
| logic dio_pad_sleep_en_10_qs; |
| logic dio_pad_sleep_en_10_wd; |
| logic dio_pad_sleep_en_11_we; |
| logic dio_pad_sleep_en_11_qs; |
| logic dio_pad_sleep_en_11_wd; |
| logic dio_pad_sleep_en_12_we; |
| logic dio_pad_sleep_en_12_qs; |
| logic dio_pad_sleep_en_12_wd; |
| logic dio_pad_sleep_en_13_we; |
| logic dio_pad_sleep_en_13_qs; |
| logic dio_pad_sleep_en_13_wd; |
| logic dio_pad_sleep_en_14_we; |
| logic dio_pad_sleep_en_14_qs; |
| logic dio_pad_sleep_en_14_wd; |
| logic dio_pad_sleep_en_15_we; |
| logic dio_pad_sleep_en_15_qs; |
| logic dio_pad_sleep_en_15_wd; |
| logic dio_pad_sleep_mode_0_we; |
| logic [1:0] dio_pad_sleep_mode_0_qs; |
| logic [1:0] dio_pad_sleep_mode_0_wd; |
| logic dio_pad_sleep_mode_1_we; |
| logic [1:0] dio_pad_sleep_mode_1_qs; |
| logic [1:0] dio_pad_sleep_mode_1_wd; |
| logic dio_pad_sleep_mode_2_we; |
| logic [1:0] dio_pad_sleep_mode_2_qs; |
| logic [1:0] dio_pad_sleep_mode_2_wd; |
| logic dio_pad_sleep_mode_3_we; |
| logic [1:0] dio_pad_sleep_mode_3_qs; |
| logic [1:0] dio_pad_sleep_mode_3_wd; |
| logic dio_pad_sleep_mode_4_we; |
| logic [1:0] dio_pad_sleep_mode_4_qs; |
| logic [1:0] dio_pad_sleep_mode_4_wd; |
| logic dio_pad_sleep_mode_5_we; |
| logic [1:0] dio_pad_sleep_mode_5_qs; |
| logic [1:0] dio_pad_sleep_mode_5_wd; |
| logic dio_pad_sleep_mode_6_we; |
| logic [1:0] dio_pad_sleep_mode_6_qs; |
| logic [1:0] dio_pad_sleep_mode_6_wd; |
| logic dio_pad_sleep_mode_7_we; |
| logic [1:0] dio_pad_sleep_mode_7_qs; |
| logic [1:0] dio_pad_sleep_mode_7_wd; |
| logic dio_pad_sleep_mode_8_we; |
| logic [1:0] dio_pad_sleep_mode_8_qs; |
| logic [1:0] dio_pad_sleep_mode_8_wd; |
| logic dio_pad_sleep_mode_9_we; |
| logic [1:0] dio_pad_sleep_mode_9_qs; |
| logic [1:0] dio_pad_sleep_mode_9_wd; |
| logic dio_pad_sleep_mode_10_we; |
| logic [1:0] dio_pad_sleep_mode_10_qs; |
| logic [1:0] dio_pad_sleep_mode_10_wd; |
| logic dio_pad_sleep_mode_11_we; |
| logic [1:0] dio_pad_sleep_mode_11_qs; |
| logic [1:0] dio_pad_sleep_mode_11_wd; |
| logic dio_pad_sleep_mode_12_we; |
| logic [1:0] dio_pad_sleep_mode_12_qs; |
| logic [1:0] dio_pad_sleep_mode_12_wd; |
| logic dio_pad_sleep_mode_13_we; |
| logic [1:0] dio_pad_sleep_mode_13_qs; |
| logic [1:0] dio_pad_sleep_mode_13_wd; |
| logic dio_pad_sleep_mode_14_we; |
| logic [1:0] dio_pad_sleep_mode_14_qs; |
| logic [1:0] dio_pad_sleep_mode_14_wd; |
| logic dio_pad_sleep_mode_15_we; |
| logic [1:0] dio_pad_sleep_mode_15_qs; |
| logic [1:0] dio_pad_sleep_mode_15_wd; |
| logic wkup_detector_regwen_0_we; |
| logic wkup_detector_regwen_0_qs; |
| logic wkup_detector_regwen_0_wd; |
| logic wkup_detector_regwen_1_we; |
| logic wkup_detector_regwen_1_qs; |
| logic wkup_detector_regwen_1_wd; |
| logic wkup_detector_regwen_2_we; |
| logic wkup_detector_regwen_2_qs; |
| logic wkup_detector_regwen_2_wd; |
| logic wkup_detector_regwen_3_we; |
| logic wkup_detector_regwen_3_qs; |
| logic wkup_detector_regwen_3_wd; |
| logic wkup_detector_regwen_4_we; |
| logic wkup_detector_regwen_4_qs; |
| logic wkup_detector_regwen_4_wd; |
| logic wkup_detector_regwen_5_we; |
| logic wkup_detector_regwen_5_qs; |
| logic wkup_detector_regwen_5_wd; |
| logic wkup_detector_regwen_6_we; |
| logic wkup_detector_regwen_6_qs; |
| logic wkup_detector_regwen_6_wd; |
| logic wkup_detector_regwen_7_we; |
| logic wkup_detector_regwen_7_qs; |
| logic wkup_detector_regwen_7_wd; |
| logic wkup_detector_en_0_we; |
| logic [0:0] wkup_detector_en_0_qs; |
| logic wkup_detector_en_0_busy; |
| logic wkup_detector_en_1_we; |
| logic [0:0] wkup_detector_en_1_qs; |
| logic wkup_detector_en_1_busy; |
| logic wkup_detector_en_2_we; |
| logic [0:0] wkup_detector_en_2_qs; |
| logic wkup_detector_en_2_busy; |
| logic wkup_detector_en_3_we; |
| logic [0:0] wkup_detector_en_3_qs; |
| logic wkup_detector_en_3_busy; |
| logic wkup_detector_en_4_we; |
| logic [0:0] wkup_detector_en_4_qs; |
| logic wkup_detector_en_4_busy; |
| logic wkup_detector_en_5_we; |
| logic [0:0] wkup_detector_en_5_qs; |
| logic wkup_detector_en_5_busy; |
| logic wkup_detector_en_6_we; |
| logic [0:0] wkup_detector_en_6_qs; |
| logic wkup_detector_en_6_busy; |
| logic wkup_detector_en_7_we; |
| logic [0:0] wkup_detector_en_7_qs; |
| logic wkup_detector_en_7_busy; |
| logic wkup_detector_0_we; |
| logic [4:0] wkup_detector_0_qs; |
| logic wkup_detector_0_busy; |
| logic wkup_detector_1_we; |
| logic [4:0] wkup_detector_1_qs; |
| logic wkup_detector_1_busy; |
| logic wkup_detector_2_we; |
| logic [4:0] wkup_detector_2_qs; |
| logic wkup_detector_2_busy; |
| logic wkup_detector_3_we; |
| logic [4:0] wkup_detector_3_qs; |
| logic wkup_detector_3_busy; |
| logic wkup_detector_4_we; |
| logic [4:0] wkup_detector_4_qs; |
| logic wkup_detector_4_busy; |
| logic wkup_detector_5_we; |
| logic [4:0] wkup_detector_5_qs; |
| logic wkup_detector_5_busy; |
| logic wkup_detector_6_we; |
| logic [4:0] wkup_detector_6_qs; |
| logic wkup_detector_6_busy; |
| logic wkup_detector_7_we; |
| logic [4:0] wkup_detector_7_qs; |
| logic wkup_detector_7_busy; |
| logic wkup_detector_cnt_th_0_we; |
| logic [7:0] wkup_detector_cnt_th_0_qs; |
| logic wkup_detector_cnt_th_0_busy; |
| logic wkup_detector_cnt_th_1_we; |
| logic [7:0] wkup_detector_cnt_th_1_qs; |
| logic wkup_detector_cnt_th_1_busy; |
| logic wkup_detector_cnt_th_2_we; |
| logic [7:0] wkup_detector_cnt_th_2_qs; |
| logic wkup_detector_cnt_th_2_busy; |
| logic wkup_detector_cnt_th_3_we; |
| logic [7:0] wkup_detector_cnt_th_3_qs; |
| logic wkup_detector_cnt_th_3_busy; |
| logic wkup_detector_cnt_th_4_we; |
| logic [7:0] wkup_detector_cnt_th_4_qs; |
| logic wkup_detector_cnt_th_4_busy; |
| logic wkup_detector_cnt_th_5_we; |
| logic [7:0] wkup_detector_cnt_th_5_qs; |
| logic wkup_detector_cnt_th_5_busy; |
| logic wkup_detector_cnt_th_6_we; |
| logic [7:0] wkup_detector_cnt_th_6_qs; |
| logic wkup_detector_cnt_th_6_busy; |
| logic wkup_detector_cnt_th_7_we; |
| logic [7:0] wkup_detector_cnt_th_7_qs; |
| logic wkup_detector_cnt_th_7_busy; |
| logic wkup_detector_padsel_0_we; |
| logic [5:0] wkup_detector_padsel_0_qs; |
| logic [5:0] wkup_detector_padsel_0_wd; |
| logic wkup_detector_padsel_1_we; |
| logic [5:0] wkup_detector_padsel_1_qs; |
| logic [5:0] wkup_detector_padsel_1_wd; |
| logic wkup_detector_padsel_2_we; |
| logic [5:0] wkup_detector_padsel_2_qs; |
| logic [5:0] wkup_detector_padsel_2_wd; |
| logic wkup_detector_padsel_3_we; |
| logic [5:0] wkup_detector_padsel_3_qs; |
| logic [5:0] wkup_detector_padsel_3_wd; |
| logic wkup_detector_padsel_4_we; |
| logic [5:0] wkup_detector_padsel_4_qs; |
| logic [5:0] wkup_detector_padsel_4_wd; |
| logic wkup_detector_padsel_5_we; |
| logic [5:0] wkup_detector_padsel_5_qs; |
| logic [5:0] wkup_detector_padsel_5_wd; |
| logic wkup_detector_padsel_6_we; |
| logic [5:0] wkup_detector_padsel_6_qs; |
| logic [5:0] wkup_detector_padsel_6_wd; |
| logic wkup_detector_padsel_7_we; |
| logic [5:0] wkup_detector_padsel_7_qs; |
| logic [5:0] wkup_detector_padsel_7_wd; |
| logic wkup_cause_we; |
| logic [7:0] wkup_cause_qs; |
| logic wkup_cause_busy; |
| // Define register CDC handling. |
| // CDC handling is done on a per-reg instead of per-field boundary. |
| |
| logic aon_wkup_detector_en_0_qs_int; |
| logic [0:0] aon_wkup_detector_en_0_qs; |
| logic [0:0] aon_wkup_detector_en_0_wdata; |
| logic aon_wkup_detector_en_0_we; |
| logic unused_aon_wkup_detector_en_0_wdata; |
| logic aon_wkup_detector_en_0_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_0_qs = 1'h0; |
| aon_wkup_detector_en_0_qs = aon_wkup_detector_en_0_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_0_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_0_qs), |
| .src_we_i (wkup_detector_en_0_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_0_busy), |
| .src_qs_o (wkup_detector_en_0_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_0_qs), |
| .dst_we_o (aon_wkup_detector_en_0_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_0_regwen), |
| .dst_wd_o (aon_wkup_detector_en_0_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_0_wdata = |
| ^aon_wkup_detector_en_0_wdata; |
| |
| logic aon_wkup_detector_en_1_qs_int; |
| logic [0:0] aon_wkup_detector_en_1_qs; |
| logic [0:0] aon_wkup_detector_en_1_wdata; |
| logic aon_wkup_detector_en_1_we; |
| logic unused_aon_wkup_detector_en_1_wdata; |
| logic aon_wkup_detector_en_1_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_1_qs = 1'h0; |
| aon_wkup_detector_en_1_qs = aon_wkup_detector_en_1_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_1_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_1_qs), |
| .src_we_i (wkup_detector_en_1_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_1_busy), |
| .src_qs_o (wkup_detector_en_1_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_1_qs), |
| .dst_we_o (aon_wkup_detector_en_1_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_1_regwen), |
| .dst_wd_o (aon_wkup_detector_en_1_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_1_wdata = |
| ^aon_wkup_detector_en_1_wdata; |
| |
| logic aon_wkup_detector_en_2_qs_int; |
| logic [0:0] aon_wkup_detector_en_2_qs; |
| logic [0:0] aon_wkup_detector_en_2_wdata; |
| logic aon_wkup_detector_en_2_we; |
| logic unused_aon_wkup_detector_en_2_wdata; |
| logic aon_wkup_detector_en_2_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_2_qs = 1'h0; |
| aon_wkup_detector_en_2_qs = aon_wkup_detector_en_2_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_2_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_2_qs), |
| .src_we_i (wkup_detector_en_2_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_2_busy), |
| .src_qs_o (wkup_detector_en_2_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_2_qs), |
| .dst_we_o (aon_wkup_detector_en_2_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_2_regwen), |
| .dst_wd_o (aon_wkup_detector_en_2_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_2_wdata = |
| ^aon_wkup_detector_en_2_wdata; |
| |
| logic aon_wkup_detector_en_3_qs_int; |
| logic [0:0] aon_wkup_detector_en_3_qs; |
| logic [0:0] aon_wkup_detector_en_3_wdata; |
| logic aon_wkup_detector_en_3_we; |
| logic unused_aon_wkup_detector_en_3_wdata; |
| logic aon_wkup_detector_en_3_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_3_qs = 1'h0; |
| aon_wkup_detector_en_3_qs = aon_wkup_detector_en_3_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_3_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_3_qs), |
| .src_we_i (wkup_detector_en_3_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_3_busy), |
| .src_qs_o (wkup_detector_en_3_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_3_qs), |
| .dst_we_o (aon_wkup_detector_en_3_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_3_regwen), |
| .dst_wd_o (aon_wkup_detector_en_3_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_3_wdata = |
| ^aon_wkup_detector_en_3_wdata; |
| |
| logic aon_wkup_detector_en_4_qs_int; |
| logic [0:0] aon_wkup_detector_en_4_qs; |
| logic [0:0] aon_wkup_detector_en_4_wdata; |
| logic aon_wkup_detector_en_4_we; |
| logic unused_aon_wkup_detector_en_4_wdata; |
| logic aon_wkup_detector_en_4_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_4_qs = 1'h0; |
| aon_wkup_detector_en_4_qs = aon_wkup_detector_en_4_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_4_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_4_qs), |
| .src_we_i (wkup_detector_en_4_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_4_busy), |
| .src_qs_o (wkup_detector_en_4_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_4_qs), |
| .dst_we_o (aon_wkup_detector_en_4_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_4_regwen), |
| .dst_wd_o (aon_wkup_detector_en_4_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_4_wdata = |
| ^aon_wkup_detector_en_4_wdata; |
| |
| logic aon_wkup_detector_en_5_qs_int; |
| logic [0:0] aon_wkup_detector_en_5_qs; |
| logic [0:0] aon_wkup_detector_en_5_wdata; |
| logic aon_wkup_detector_en_5_we; |
| logic unused_aon_wkup_detector_en_5_wdata; |
| logic aon_wkup_detector_en_5_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_5_qs = 1'h0; |
| aon_wkup_detector_en_5_qs = aon_wkup_detector_en_5_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_5_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_5_qs), |
| .src_we_i (wkup_detector_en_5_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_5_busy), |
| .src_qs_o (wkup_detector_en_5_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_5_qs), |
| .dst_we_o (aon_wkup_detector_en_5_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_5_regwen), |
| .dst_wd_o (aon_wkup_detector_en_5_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_5_wdata = |
| ^aon_wkup_detector_en_5_wdata; |
| |
| logic aon_wkup_detector_en_6_qs_int; |
| logic [0:0] aon_wkup_detector_en_6_qs; |
| logic [0:0] aon_wkup_detector_en_6_wdata; |
| logic aon_wkup_detector_en_6_we; |
| logic unused_aon_wkup_detector_en_6_wdata; |
| logic aon_wkup_detector_en_6_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_6_qs = 1'h0; |
| aon_wkup_detector_en_6_qs = aon_wkup_detector_en_6_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_6_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_6_qs), |
| .src_we_i (wkup_detector_en_6_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_6_busy), |
| .src_qs_o (wkup_detector_en_6_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_6_qs), |
| .dst_we_o (aon_wkup_detector_en_6_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_6_regwen), |
| .dst_wd_o (aon_wkup_detector_en_6_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_6_wdata = |
| ^aon_wkup_detector_en_6_wdata; |
| |
| logic aon_wkup_detector_en_7_qs_int; |
| logic [0:0] aon_wkup_detector_en_7_qs; |
| logic [0:0] aon_wkup_detector_en_7_wdata; |
| logic aon_wkup_detector_en_7_we; |
| logic unused_aon_wkup_detector_en_7_wdata; |
| logic aon_wkup_detector_en_7_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_en_7_qs = 1'h0; |
| aon_wkup_detector_en_7_qs = aon_wkup_detector_en_7_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(1), |
| .ResetVal(1'h0), |
| .BitMask(1'h1), |
| .DstWrReq(0) |
| ) u_wkup_detector_en_7_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_7_qs), |
| .src_we_i (wkup_detector_en_7_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[0:0]), |
| .src_busy_o (wkup_detector_en_7_busy), |
| .src_qs_o (wkup_detector_en_7_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_en_7_qs), |
| .dst_we_o (aon_wkup_detector_en_7_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_en_7_regwen), |
| .dst_wd_o (aon_wkup_detector_en_7_wdata) |
| ); |
| assign unused_aon_wkup_detector_en_7_wdata = |
| ^aon_wkup_detector_en_7_wdata; |
| |
| logic [2:0] aon_wkup_detector_0_mode_0_qs_int; |
| logic aon_wkup_detector_0_filter_0_qs_int; |
| logic aon_wkup_detector_0_miodio_0_qs_int; |
| logic [4:0] aon_wkup_detector_0_qs; |
| logic [4:0] aon_wkup_detector_0_wdata; |
| logic aon_wkup_detector_0_we; |
| logic unused_aon_wkup_detector_0_wdata; |
| logic aon_wkup_detector_0_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_0_qs = 5'h0; |
| aon_wkup_detector_0_qs[2:0] = aon_wkup_detector_0_mode_0_qs_int; |
| aon_wkup_detector_0_qs[3] = aon_wkup_detector_0_filter_0_qs_int; |
| aon_wkup_detector_0_qs[4] = aon_wkup_detector_0_miodio_0_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_0_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_0_qs), |
| .src_we_i (wkup_detector_0_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_0_busy), |
| .src_qs_o (wkup_detector_0_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_0_qs), |
| .dst_we_o (aon_wkup_detector_0_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_0_regwen), |
| .dst_wd_o (aon_wkup_detector_0_wdata) |
| ); |
| assign unused_aon_wkup_detector_0_wdata = |
| ^aon_wkup_detector_0_wdata; |
| |
| logic [2:0] aon_wkup_detector_1_mode_1_qs_int; |
| logic aon_wkup_detector_1_filter_1_qs_int; |
| logic aon_wkup_detector_1_miodio_1_qs_int; |
| logic [4:0] aon_wkup_detector_1_qs; |
| logic [4:0] aon_wkup_detector_1_wdata; |
| logic aon_wkup_detector_1_we; |
| logic unused_aon_wkup_detector_1_wdata; |
| logic aon_wkup_detector_1_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_1_qs = 5'h0; |
| aon_wkup_detector_1_qs[2:0] = aon_wkup_detector_1_mode_1_qs_int; |
| aon_wkup_detector_1_qs[3] = aon_wkup_detector_1_filter_1_qs_int; |
| aon_wkup_detector_1_qs[4] = aon_wkup_detector_1_miodio_1_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_1_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_1_qs), |
| .src_we_i (wkup_detector_1_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_1_busy), |
| .src_qs_o (wkup_detector_1_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_1_qs), |
| .dst_we_o (aon_wkup_detector_1_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_1_regwen), |
| .dst_wd_o (aon_wkup_detector_1_wdata) |
| ); |
| assign unused_aon_wkup_detector_1_wdata = |
| ^aon_wkup_detector_1_wdata; |
| |
| logic [2:0] aon_wkup_detector_2_mode_2_qs_int; |
| logic aon_wkup_detector_2_filter_2_qs_int; |
| logic aon_wkup_detector_2_miodio_2_qs_int; |
| logic [4:0] aon_wkup_detector_2_qs; |
| logic [4:0] aon_wkup_detector_2_wdata; |
| logic aon_wkup_detector_2_we; |
| logic unused_aon_wkup_detector_2_wdata; |
| logic aon_wkup_detector_2_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_2_qs = 5'h0; |
| aon_wkup_detector_2_qs[2:0] = aon_wkup_detector_2_mode_2_qs_int; |
| aon_wkup_detector_2_qs[3] = aon_wkup_detector_2_filter_2_qs_int; |
| aon_wkup_detector_2_qs[4] = aon_wkup_detector_2_miodio_2_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_2_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_2_qs), |
| .src_we_i (wkup_detector_2_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_2_busy), |
| .src_qs_o (wkup_detector_2_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_2_qs), |
| .dst_we_o (aon_wkup_detector_2_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_2_regwen), |
| .dst_wd_o (aon_wkup_detector_2_wdata) |
| ); |
| assign unused_aon_wkup_detector_2_wdata = |
| ^aon_wkup_detector_2_wdata; |
| |
| logic [2:0] aon_wkup_detector_3_mode_3_qs_int; |
| logic aon_wkup_detector_3_filter_3_qs_int; |
| logic aon_wkup_detector_3_miodio_3_qs_int; |
| logic [4:0] aon_wkup_detector_3_qs; |
| logic [4:0] aon_wkup_detector_3_wdata; |
| logic aon_wkup_detector_3_we; |
| logic unused_aon_wkup_detector_3_wdata; |
| logic aon_wkup_detector_3_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_3_qs = 5'h0; |
| aon_wkup_detector_3_qs[2:0] = aon_wkup_detector_3_mode_3_qs_int; |
| aon_wkup_detector_3_qs[3] = aon_wkup_detector_3_filter_3_qs_int; |
| aon_wkup_detector_3_qs[4] = aon_wkup_detector_3_miodio_3_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_3_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_3_qs), |
| .src_we_i (wkup_detector_3_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_3_busy), |
| .src_qs_o (wkup_detector_3_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_3_qs), |
| .dst_we_o (aon_wkup_detector_3_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_3_regwen), |
| .dst_wd_o (aon_wkup_detector_3_wdata) |
| ); |
| assign unused_aon_wkup_detector_3_wdata = |
| ^aon_wkup_detector_3_wdata; |
| |
| logic [2:0] aon_wkup_detector_4_mode_4_qs_int; |
| logic aon_wkup_detector_4_filter_4_qs_int; |
| logic aon_wkup_detector_4_miodio_4_qs_int; |
| logic [4:0] aon_wkup_detector_4_qs; |
| logic [4:0] aon_wkup_detector_4_wdata; |
| logic aon_wkup_detector_4_we; |
| logic unused_aon_wkup_detector_4_wdata; |
| logic aon_wkup_detector_4_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_4_qs = 5'h0; |
| aon_wkup_detector_4_qs[2:0] = aon_wkup_detector_4_mode_4_qs_int; |
| aon_wkup_detector_4_qs[3] = aon_wkup_detector_4_filter_4_qs_int; |
| aon_wkup_detector_4_qs[4] = aon_wkup_detector_4_miodio_4_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_4_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_4_qs), |
| .src_we_i (wkup_detector_4_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_4_busy), |
| .src_qs_o (wkup_detector_4_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_4_qs), |
| .dst_we_o (aon_wkup_detector_4_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_4_regwen), |
| .dst_wd_o (aon_wkup_detector_4_wdata) |
| ); |
| assign unused_aon_wkup_detector_4_wdata = |
| ^aon_wkup_detector_4_wdata; |
| |
| logic [2:0] aon_wkup_detector_5_mode_5_qs_int; |
| logic aon_wkup_detector_5_filter_5_qs_int; |
| logic aon_wkup_detector_5_miodio_5_qs_int; |
| logic [4:0] aon_wkup_detector_5_qs; |
| logic [4:0] aon_wkup_detector_5_wdata; |
| logic aon_wkup_detector_5_we; |
| logic unused_aon_wkup_detector_5_wdata; |
| logic aon_wkup_detector_5_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_5_qs = 5'h0; |
| aon_wkup_detector_5_qs[2:0] = aon_wkup_detector_5_mode_5_qs_int; |
| aon_wkup_detector_5_qs[3] = aon_wkup_detector_5_filter_5_qs_int; |
| aon_wkup_detector_5_qs[4] = aon_wkup_detector_5_miodio_5_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_5_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_5_qs), |
| .src_we_i (wkup_detector_5_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_5_busy), |
| .src_qs_o (wkup_detector_5_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_5_qs), |
| .dst_we_o (aon_wkup_detector_5_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_5_regwen), |
| .dst_wd_o (aon_wkup_detector_5_wdata) |
| ); |
| assign unused_aon_wkup_detector_5_wdata = |
| ^aon_wkup_detector_5_wdata; |
| |
| logic [2:0] aon_wkup_detector_6_mode_6_qs_int; |
| logic aon_wkup_detector_6_filter_6_qs_int; |
| logic aon_wkup_detector_6_miodio_6_qs_int; |
| logic [4:0] aon_wkup_detector_6_qs; |
| logic [4:0] aon_wkup_detector_6_wdata; |
| logic aon_wkup_detector_6_we; |
| logic unused_aon_wkup_detector_6_wdata; |
| logic aon_wkup_detector_6_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_6_qs = 5'h0; |
| aon_wkup_detector_6_qs[2:0] = aon_wkup_detector_6_mode_6_qs_int; |
| aon_wkup_detector_6_qs[3] = aon_wkup_detector_6_filter_6_qs_int; |
| aon_wkup_detector_6_qs[4] = aon_wkup_detector_6_miodio_6_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_6_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_6_qs), |
| .src_we_i (wkup_detector_6_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_6_busy), |
| .src_qs_o (wkup_detector_6_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_6_qs), |
| .dst_we_o (aon_wkup_detector_6_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_6_regwen), |
| .dst_wd_o (aon_wkup_detector_6_wdata) |
| ); |
| assign unused_aon_wkup_detector_6_wdata = |
| ^aon_wkup_detector_6_wdata; |
| |
| logic [2:0] aon_wkup_detector_7_mode_7_qs_int; |
| logic aon_wkup_detector_7_filter_7_qs_int; |
| logic aon_wkup_detector_7_miodio_7_qs_int; |
| logic [4:0] aon_wkup_detector_7_qs; |
| logic [4:0] aon_wkup_detector_7_wdata; |
| logic aon_wkup_detector_7_we; |
| logic unused_aon_wkup_detector_7_wdata; |
| logic aon_wkup_detector_7_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_7_qs = 5'h0; |
| aon_wkup_detector_7_qs[2:0] = aon_wkup_detector_7_mode_7_qs_int; |
| aon_wkup_detector_7_qs[3] = aon_wkup_detector_7_filter_7_qs_int; |
| aon_wkup_detector_7_qs[4] = aon_wkup_detector_7_miodio_7_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(5), |
| .ResetVal(5'h0), |
| .BitMask(5'h1f), |
| .DstWrReq(0) |
| ) u_wkup_detector_7_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_7_qs), |
| .src_we_i (wkup_detector_7_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[4:0]), |
| .src_busy_o (wkup_detector_7_busy), |
| .src_qs_o (wkup_detector_7_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_7_qs), |
| .dst_we_o (aon_wkup_detector_7_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_7_regwen), |
| .dst_wd_o (aon_wkup_detector_7_wdata) |
| ); |
| assign unused_aon_wkup_detector_7_wdata = |
| ^aon_wkup_detector_7_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_0_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_0_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_0_wdata; |
| logic aon_wkup_detector_cnt_th_0_we; |
| logic unused_aon_wkup_detector_cnt_th_0_wdata; |
| logic aon_wkup_detector_cnt_th_0_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_0_qs = 8'h0; |
| aon_wkup_detector_cnt_th_0_qs = aon_wkup_detector_cnt_th_0_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_0_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_0_qs), |
| .src_we_i (wkup_detector_cnt_th_0_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_0_busy), |
| .src_qs_o (wkup_detector_cnt_th_0_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_0_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_0_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_0_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_0_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_0_wdata = |
| ^aon_wkup_detector_cnt_th_0_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_1_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_1_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_1_wdata; |
| logic aon_wkup_detector_cnt_th_1_we; |
| logic unused_aon_wkup_detector_cnt_th_1_wdata; |
| logic aon_wkup_detector_cnt_th_1_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_1_qs = 8'h0; |
| aon_wkup_detector_cnt_th_1_qs = aon_wkup_detector_cnt_th_1_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_1_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_1_qs), |
| .src_we_i (wkup_detector_cnt_th_1_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_1_busy), |
| .src_qs_o (wkup_detector_cnt_th_1_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_1_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_1_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_1_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_1_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_1_wdata = |
| ^aon_wkup_detector_cnt_th_1_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_2_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_2_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_2_wdata; |
| logic aon_wkup_detector_cnt_th_2_we; |
| logic unused_aon_wkup_detector_cnt_th_2_wdata; |
| logic aon_wkup_detector_cnt_th_2_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_2_qs = 8'h0; |
| aon_wkup_detector_cnt_th_2_qs = aon_wkup_detector_cnt_th_2_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_2_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_2_qs), |
| .src_we_i (wkup_detector_cnt_th_2_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_2_busy), |
| .src_qs_o (wkup_detector_cnt_th_2_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_2_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_2_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_2_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_2_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_2_wdata = |
| ^aon_wkup_detector_cnt_th_2_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_3_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_3_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_3_wdata; |
| logic aon_wkup_detector_cnt_th_3_we; |
| logic unused_aon_wkup_detector_cnt_th_3_wdata; |
| logic aon_wkup_detector_cnt_th_3_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_3_qs = 8'h0; |
| aon_wkup_detector_cnt_th_3_qs = aon_wkup_detector_cnt_th_3_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_3_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_3_qs), |
| .src_we_i (wkup_detector_cnt_th_3_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_3_busy), |
| .src_qs_o (wkup_detector_cnt_th_3_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_3_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_3_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_3_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_3_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_3_wdata = |
| ^aon_wkup_detector_cnt_th_3_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_4_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_4_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_4_wdata; |
| logic aon_wkup_detector_cnt_th_4_we; |
| logic unused_aon_wkup_detector_cnt_th_4_wdata; |
| logic aon_wkup_detector_cnt_th_4_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_4_qs = 8'h0; |
| aon_wkup_detector_cnt_th_4_qs = aon_wkup_detector_cnt_th_4_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_4_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_4_qs), |
| .src_we_i (wkup_detector_cnt_th_4_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_4_busy), |
| .src_qs_o (wkup_detector_cnt_th_4_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_4_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_4_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_4_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_4_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_4_wdata = |
| ^aon_wkup_detector_cnt_th_4_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_5_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_5_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_5_wdata; |
| logic aon_wkup_detector_cnt_th_5_we; |
| logic unused_aon_wkup_detector_cnt_th_5_wdata; |
| logic aon_wkup_detector_cnt_th_5_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_5_qs = 8'h0; |
| aon_wkup_detector_cnt_th_5_qs = aon_wkup_detector_cnt_th_5_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_5_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_5_qs), |
| .src_we_i (wkup_detector_cnt_th_5_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_5_busy), |
| .src_qs_o (wkup_detector_cnt_th_5_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_5_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_5_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_5_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_5_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_5_wdata = |
| ^aon_wkup_detector_cnt_th_5_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_6_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_6_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_6_wdata; |
| logic aon_wkup_detector_cnt_th_6_we; |
| logic unused_aon_wkup_detector_cnt_th_6_wdata; |
| logic aon_wkup_detector_cnt_th_6_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_6_qs = 8'h0; |
| aon_wkup_detector_cnt_th_6_qs = aon_wkup_detector_cnt_th_6_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_6_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_6_qs), |
| .src_we_i (wkup_detector_cnt_th_6_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_6_busy), |
| .src_qs_o (wkup_detector_cnt_th_6_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_6_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_6_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_6_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_6_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_6_wdata = |
| ^aon_wkup_detector_cnt_th_6_wdata; |
| |
| logic [7:0] aon_wkup_detector_cnt_th_7_qs_int; |
| logic [7:0] aon_wkup_detector_cnt_th_7_qs; |
| logic [7:0] aon_wkup_detector_cnt_th_7_wdata; |
| logic aon_wkup_detector_cnt_th_7_we; |
| logic unused_aon_wkup_detector_cnt_th_7_wdata; |
| logic aon_wkup_detector_cnt_th_7_regwen; |
| |
| always_comb begin |
| aon_wkup_detector_cnt_th_7_qs = 8'h0; |
| aon_wkup_detector_cnt_th_7_qs = aon_wkup_detector_cnt_th_7_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(0) |
| ) u_wkup_detector_cnt_th_7_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i (wkup_detector_regwen_7_qs), |
| .src_we_i (wkup_detector_cnt_th_7_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_detector_cnt_th_7_busy), |
| .src_qs_o (wkup_detector_cnt_th_7_qs), // for software read back |
| .dst_update_i ('0), |
| .dst_ds_i ('0), |
| .dst_qs_i (aon_wkup_detector_cnt_th_7_qs), |
| .dst_we_o (aon_wkup_detector_cnt_th_7_we), |
| .dst_re_o (), |
| .dst_regwen_o (aon_wkup_detector_cnt_th_7_regwen), |
| .dst_wd_o (aon_wkup_detector_cnt_th_7_wdata) |
| ); |
| assign unused_aon_wkup_detector_cnt_th_7_wdata = |
| ^aon_wkup_detector_cnt_th_7_wdata; |
| |
| logic aon_wkup_cause_cause_0_ds_int; |
| logic aon_wkup_cause_cause_0_qs_int; |
| logic aon_wkup_cause_cause_1_ds_int; |
| logic aon_wkup_cause_cause_1_qs_int; |
| logic aon_wkup_cause_cause_2_ds_int; |
| logic aon_wkup_cause_cause_2_qs_int; |
| logic aon_wkup_cause_cause_3_ds_int; |
| logic aon_wkup_cause_cause_3_qs_int; |
| logic aon_wkup_cause_cause_4_ds_int; |
| logic aon_wkup_cause_cause_4_qs_int; |
| logic aon_wkup_cause_cause_5_ds_int; |
| logic aon_wkup_cause_cause_5_qs_int; |
| logic aon_wkup_cause_cause_6_ds_int; |
| logic aon_wkup_cause_cause_6_qs_int; |
| logic aon_wkup_cause_cause_7_ds_int; |
| logic aon_wkup_cause_cause_7_qs_int; |
| logic [7:0] aon_wkup_cause_ds; |
| logic aon_wkup_cause_qe; |
| logic [7:0] aon_wkup_cause_qs; |
| logic [7:0] aon_wkup_cause_wdata; |
| logic aon_wkup_cause_we; |
| logic unused_aon_wkup_cause_wdata; |
| |
| always_comb begin |
| aon_wkup_cause_qs = 8'h0; |
| aon_wkup_cause_ds = 8'h0; |
| aon_wkup_cause_ds[0] = aon_wkup_cause_cause_0_ds_int; |
| aon_wkup_cause_qs[0] = aon_wkup_cause_cause_0_qs_int; |
| aon_wkup_cause_ds[1] = aon_wkup_cause_cause_1_ds_int; |
| aon_wkup_cause_qs[1] = aon_wkup_cause_cause_1_qs_int; |
| aon_wkup_cause_ds[2] = aon_wkup_cause_cause_2_ds_int; |
| aon_wkup_cause_qs[2] = aon_wkup_cause_cause_2_qs_int; |
| aon_wkup_cause_ds[3] = aon_wkup_cause_cause_3_ds_int; |
| aon_wkup_cause_qs[3] = aon_wkup_cause_cause_3_qs_int; |
| aon_wkup_cause_ds[4] = aon_wkup_cause_cause_4_ds_int; |
| aon_wkup_cause_qs[4] = aon_wkup_cause_cause_4_qs_int; |
| aon_wkup_cause_ds[5] = aon_wkup_cause_cause_5_ds_int; |
| aon_wkup_cause_qs[5] = aon_wkup_cause_cause_5_qs_int; |
| aon_wkup_cause_ds[6] = aon_wkup_cause_cause_6_ds_int; |
| aon_wkup_cause_qs[6] = aon_wkup_cause_cause_6_qs_int; |
| aon_wkup_cause_ds[7] = aon_wkup_cause_cause_7_ds_int; |
| aon_wkup_cause_qs[7] = aon_wkup_cause_cause_7_qs_int; |
| end |
| |
| prim_reg_cdc #( |
| .DataWidth(8), |
| .ResetVal(8'h0), |
| .BitMask(8'hff), |
| .DstWrReq(1) |
| ) u_wkup_cause_cdc ( |
| .clk_src_i (clk_i), |
| .rst_src_ni (rst_ni), |
| .clk_dst_i (clk_aon_i), |
| .rst_dst_ni (rst_aon_ni), |
| .src_regwen_i ('0), |
| .src_we_i (wkup_cause_we), |
| .src_re_i ('0), |
| .src_wd_i (reg_wdata[7:0]), |
| .src_busy_o (wkup_cause_busy), |
| .src_qs_o (wkup_cause_qs), // for software read back |
| .dst_update_i (aon_wkup_cause_qe), |
| .dst_ds_i (aon_wkup_cause_ds), |
| .dst_qs_i (aon_wkup_cause_qs), |
| .dst_we_o (aon_wkup_cause_we), |
| .dst_re_o (), |
| .dst_regwen_o (), |
| .dst_wd_o (aon_wkup_cause_wdata) |
| ); |
| assign unused_aon_wkup_cause_wdata = |
| ^aon_wkup_cause_wdata; |
| |
| // Register instances |
| // R[alert_test]: V(True) |
| logic alert_test_qe; |
| logic [0:0] alert_test_flds_we; |
| assign alert_test_qe = &alert_test_flds_we; |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[0]), |
| .q (reg2hw.alert_test.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.qe = alert_test_qe; |
| |
| |
| // Subregister 0 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_0_we), |
| .wd (mio_periph_insel_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_1_we), |
| .wd (mio_periph_insel_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_2_we), |
| .wd (mio_periph_insel_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_3_we), |
| .wd (mio_periph_insel_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_4_we), |
| .wd (mio_periph_insel_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_5_we), |
| .wd (mio_periph_insel_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_6_we), |
| .wd (mio_periph_insel_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_7_we), |
| .wd (mio_periph_insel_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_8]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_8_we), |
| .wd (mio_periph_insel_regwen_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_9]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_9_we), |
| .wd (mio_periph_insel_regwen_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_10]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_10_we), |
| .wd (mio_periph_insel_regwen_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_11]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_11_we), |
| .wd (mio_periph_insel_regwen_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_12]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_12_we), |
| .wd (mio_periph_insel_regwen_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_13]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_13_we), |
| .wd (mio_periph_insel_regwen_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_14]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_14_we), |
| .wd (mio_periph_insel_regwen_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_15]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_15_we), |
| .wd (mio_periph_insel_regwen_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_16]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_16_we), |
| .wd (mio_periph_insel_regwen_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_17]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_17_we), |
| .wd (mio_periph_insel_regwen_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_18]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_18_we), |
| .wd (mio_periph_insel_regwen_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_19]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_19_we), |
| .wd (mio_periph_insel_regwen_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_20]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_20_we), |
| .wd (mio_periph_insel_regwen_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_21]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_21_we), |
| .wd (mio_periph_insel_regwen_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_22]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_22_we), |
| .wd (mio_periph_insel_regwen_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_23]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_23_we), |
| .wd (mio_periph_insel_regwen_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_24]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_24_we), |
| .wd (mio_periph_insel_regwen_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_25]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_25_we), |
| .wd (mio_periph_insel_regwen_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_26]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_26_we), |
| .wd (mio_periph_insel_regwen_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_27]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_27_we), |
| .wd (mio_periph_insel_regwen_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_28]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_28_we), |
| .wd (mio_periph_insel_regwen_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_29]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_29_we), |
| .wd (mio_periph_insel_regwen_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_30]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_30_we), |
| .wd (mio_periph_insel_regwen_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_31]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_31_we), |
| .wd (mio_periph_insel_regwen_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_31_qs) |
| ); |
| |
| |
| // Subregister 32 of Multireg mio_periph_insel_regwen |
| // R[mio_periph_insel_regwen_32]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_periph_insel_regwen_32 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_regwen_32_we), |
| .wd (mio_periph_insel_regwen_32_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_regwen_32_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_periph_insel |
| // R[mio_periph_insel_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_0_gated_we; |
| assign mio_periph_insel_0_gated_we = mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_0_gated_we), |
| .wd (mio_periph_insel_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_periph_insel |
| // R[mio_periph_insel_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_1_gated_we; |
| assign mio_periph_insel_1_gated_we = mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_1_gated_we), |
| .wd (mio_periph_insel_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_periph_insel |
| // R[mio_periph_insel_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_2_gated_we; |
| assign mio_periph_insel_2_gated_we = mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_2_gated_we), |
| .wd (mio_periph_insel_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_periph_insel |
| // R[mio_periph_insel_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_3_gated_we; |
| assign mio_periph_insel_3_gated_we = mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_3_gated_we), |
| .wd (mio_periph_insel_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_periph_insel |
| // R[mio_periph_insel_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_4_gated_we; |
| assign mio_periph_insel_4_gated_we = mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_4_gated_we), |
| .wd (mio_periph_insel_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_periph_insel |
| // R[mio_periph_insel_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_5_gated_we; |
| assign mio_periph_insel_5_gated_we = mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_5_gated_we), |
| .wd (mio_periph_insel_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_periph_insel |
| // R[mio_periph_insel_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_6_gated_we; |
| assign mio_periph_insel_6_gated_we = mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_6_gated_we), |
| .wd (mio_periph_insel_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_periph_insel |
| // R[mio_periph_insel_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_7_gated_we; |
| assign mio_periph_insel_7_gated_we = mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_7_gated_we), |
| .wd (mio_periph_insel_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_periph_insel |
| // R[mio_periph_insel_8]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_8_gated_we; |
| assign mio_periph_insel_8_gated_we = mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_8_gated_we), |
| .wd (mio_periph_insel_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_periph_insel |
| // R[mio_periph_insel_9]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_9_gated_we; |
| assign mio_periph_insel_9_gated_we = mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_9_gated_we), |
| .wd (mio_periph_insel_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_periph_insel |
| // R[mio_periph_insel_10]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_10_gated_we; |
| assign mio_periph_insel_10_gated_we = mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_10_gated_we), |
| .wd (mio_periph_insel_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_periph_insel |
| // R[mio_periph_insel_11]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_11_gated_we; |
| assign mio_periph_insel_11_gated_we = mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_11_gated_we), |
| .wd (mio_periph_insel_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_periph_insel |
| // R[mio_periph_insel_12]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_12_gated_we; |
| assign mio_periph_insel_12_gated_we = mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_12_gated_we), |
| .wd (mio_periph_insel_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_periph_insel |
| // R[mio_periph_insel_13]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_13_gated_we; |
| assign mio_periph_insel_13_gated_we = mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_13_gated_we), |
| .wd (mio_periph_insel_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_periph_insel |
| // R[mio_periph_insel_14]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_14_gated_we; |
| assign mio_periph_insel_14_gated_we = mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_14_gated_we), |
| .wd (mio_periph_insel_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_periph_insel |
| // R[mio_periph_insel_15]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_15_gated_we; |
| assign mio_periph_insel_15_gated_we = mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_15_gated_we), |
| .wd (mio_periph_insel_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_periph_insel |
| // R[mio_periph_insel_16]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_16_gated_we; |
| assign mio_periph_insel_16_gated_we = mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_16_gated_we), |
| .wd (mio_periph_insel_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_periph_insel |
| // R[mio_periph_insel_17]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_17_gated_we; |
| assign mio_periph_insel_17_gated_we = mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_17_gated_we), |
| .wd (mio_periph_insel_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_periph_insel |
| // R[mio_periph_insel_18]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_18_gated_we; |
| assign mio_periph_insel_18_gated_we = mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_18_gated_we), |
| .wd (mio_periph_insel_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_periph_insel |
| // R[mio_periph_insel_19]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_19_gated_we; |
| assign mio_periph_insel_19_gated_we = mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_19_gated_we), |
| .wd (mio_periph_insel_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_periph_insel |
| // R[mio_periph_insel_20]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_20_gated_we; |
| assign mio_periph_insel_20_gated_we = mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_20_gated_we), |
| .wd (mio_periph_insel_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_periph_insel |
| // R[mio_periph_insel_21]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_21_gated_we; |
| assign mio_periph_insel_21_gated_we = mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_21_gated_we), |
| .wd (mio_periph_insel_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_periph_insel |
| // R[mio_periph_insel_22]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_22_gated_we; |
| assign mio_periph_insel_22_gated_we = mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_22_gated_we), |
| .wd (mio_periph_insel_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_periph_insel |
| // R[mio_periph_insel_23]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_23_gated_we; |
| assign mio_periph_insel_23_gated_we = mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_23_gated_we), |
| .wd (mio_periph_insel_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_periph_insel |
| // R[mio_periph_insel_24]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_24_gated_we; |
| assign mio_periph_insel_24_gated_we = mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_24_gated_we), |
| .wd (mio_periph_insel_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_periph_insel |
| // R[mio_periph_insel_25]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_25_gated_we; |
| assign mio_periph_insel_25_gated_we = mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_25_gated_we), |
| .wd (mio_periph_insel_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_periph_insel |
| // R[mio_periph_insel_26]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_26_gated_we; |
| assign mio_periph_insel_26_gated_we = mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_26_gated_we), |
| .wd (mio_periph_insel_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_periph_insel |
| // R[mio_periph_insel_27]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_27_gated_we; |
| assign mio_periph_insel_27_gated_we = mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_27_gated_we), |
| .wd (mio_periph_insel_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_periph_insel |
| // R[mio_periph_insel_28]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_28_gated_we; |
| assign mio_periph_insel_28_gated_we = mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_28_gated_we), |
| .wd (mio_periph_insel_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_periph_insel |
| // R[mio_periph_insel_29]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_29_gated_we; |
| assign mio_periph_insel_29_gated_we = mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_29_gated_we), |
| .wd (mio_periph_insel_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_periph_insel |
| // R[mio_periph_insel_30]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_30_gated_we; |
| assign mio_periph_insel_30_gated_we = mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_30_gated_we), |
| .wd (mio_periph_insel_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[30].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_periph_insel |
| // R[mio_periph_insel_31]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_31_gated_we; |
| assign mio_periph_insel_31_gated_we = mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_31_gated_we), |
| .wd (mio_periph_insel_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[31].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_31_qs) |
| ); |
| |
| |
| // Subregister 32 of Multireg mio_periph_insel |
| // R[mio_periph_insel_32]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_periph_insel_32_gated_we; |
| assign mio_periph_insel_32_gated_we = mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h0) |
| ) u_mio_periph_insel_32 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_periph_insel_32_gated_we), |
| .wd (mio_periph_insel_32_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_periph_insel[32].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_periph_insel_32_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_0_we), |
| .wd (mio_outsel_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_1_we), |
| .wd (mio_outsel_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_2_we), |
| .wd (mio_outsel_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_3_we), |
| .wd (mio_outsel_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_4_we), |
| .wd (mio_outsel_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_5_we), |
| .wd (mio_outsel_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_6_we), |
| .wd (mio_outsel_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_7_we), |
| .wd (mio_outsel_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_8]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_8_we), |
| .wd (mio_outsel_regwen_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_9]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_9_we), |
| .wd (mio_outsel_regwen_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_10]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_10_we), |
| .wd (mio_outsel_regwen_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_11]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_11_we), |
| .wd (mio_outsel_regwen_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_12]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_12_we), |
| .wd (mio_outsel_regwen_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_13]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_13_we), |
| .wd (mio_outsel_regwen_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_14]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_14_we), |
| .wd (mio_outsel_regwen_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_15]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_15_we), |
| .wd (mio_outsel_regwen_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_16]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_16_we), |
| .wd (mio_outsel_regwen_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_17]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_17_we), |
| .wd (mio_outsel_regwen_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_18]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_18_we), |
| .wd (mio_outsel_regwen_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_19]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_19_we), |
| .wd (mio_outsel_regwen_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_20]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_20_we), |
| .wd (mio_outsel_regwen_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_21]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_21_we), |
| .wd (mio_outsel_regwen_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_22]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_22_we), |
| .wd (mio_outsel_regwen_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_23]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_23_we), |
| .wd (mio_outsel_regwen_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_24]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_24_we), |
| .wd (mio_outsel_regwen_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_25]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_25_we), |
| .wd (mio_outsel_regwen_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_26]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_26_we), |
| .wd (mio_outsel_regwen_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_27]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_27_we), |
| .wd (mio_outsel_regwen_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_28]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_28_we), |
| .wd (mio_outsel_regwen_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_29]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_29_we), |
| .wd (mio_outsel_regwen_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_30]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_30_we), |
| .wd (mio_outsel_regwen_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_outsel_regwen |
| // R[mio_outsel_regwen_31]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_outsel_regwen_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_regwen_31_we), |
| .wd (mio_outsel_regwen_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_regwen_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_outsel |
| // R[mio_outsel_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_0_gated_we; |
| assign mio_outsel_0_gated_we = mio_outsel_0_we & mio_outsel_regwen_0_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_0_gated_we), |
| .wd (mio_outsel_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_outsel |
| // R[mio_outsel_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_1_gated_we; |
| assign mio_outsel_1_gated_we = mio_outsel_1_we & mio_outsel_regwen_1_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_1_gated_we), |
| .wd (mio_outsel_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_outsel |
| // R[mio_outsel_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_2_gated_we; |
| assign mio_outsel_2_gated_we = mio_outsel_2_we & mio_outsel_regwen_2_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_2_gated_we), |
| .wd (mio_outsel_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_outsel |
| // R[mio_outsel_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_3_gated_we; |
| assign mio_outsel_3_gated_we = mio_outsel_3_we & mio_outsel_regwen_3_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_3_gated_we), |
| .wd (mio_outsel_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_outsel |
| // R[mio_outsel_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_4_gated_we; |
| assign mio_outsel_4_gated_we = mio_outsel_4_we & mio_outsel_regwen_4_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_4_gated_we), |
| .wd (mio_outsel_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_outsel |
| // R[mio_outsel_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_5_gated_we; |
| assign mio_outsel_5_gated_we = mio_outsel_5_we & mio_outsel_regwen_5_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_5_gated_we), |
| .wd (mio_outsel_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_outsel |
| // R[mio_outsel_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_6_gated_we; |
| assign mio_outsel_6_gated_we = mio_outsel_6_we & mio_outsel_regwen_6_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_6_gated_we), |
| .wd (mio_outsel_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_outsel |
| // R[mio_outsel_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_7_gated_we; |
| assign mio_outsel_7_gated_we = mio_outsel_7_we & mio_outsel_regwen_7_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_7_gated_we), |
| .wd (mio_outsel_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_outsel |
| // R[mio_outsel_8]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_8_gated_we; |
| assign mio_outsel_8_gated_we = mio_outsel_8_we & mio_outsel_regwen_8_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_8_gated_we), |
| .wd (mio_outsel_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_outsel |
| // R[mio_outsel_9]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_9_gated_we; |
| assign mio_outsel_9_gated_we = mio_outsel_9_we & mio_outsel_regwen_9_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_9_gated_we), |
| .wd (mio_outsel_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_outsel |
| // R[mio_outsel_10]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_10_gated_we; |
| assign mio_outsel_10_gated_we = mio_outsel_10_we & mio_outsel_regwen_10_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_10_gated_we), |
| .wd (mio_outsel_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_outsel |
| // R[mio_outsel_11]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_11_gated_we; |
| assign mio_outsel_11_gated_we = mio_outsel_11_we & mio_outsel_regwen_11_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_11_gated_we), |
| .wd (mio_outsel_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_outsel |
| // R[mio_outsel_12]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_12_gated_we; |
| assign mio_outsel_12_gated_we = mio_outsel_12_we & mio_outsel_regwen_12_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_12_gated_we), |
| .wd (mio_outsel_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_outsel |
| // R[mio_outsel_13]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_13_gated_we; |
| assign mio_outsel_13_gated_we = mio_outsel_13_we & mio_outsel_regwen_13_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_13_gated_we), |
| .wd (mio_outsel_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_outsel |
| // R[mio_outsel_14]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_14_gated_we; |
| assign mio_outsel_14_gated_we = mio_outsel_14_we & mio_outsel_regwen_14_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_14_gated_we), |
| .wd (mio_outsel_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_outsel |
| // R[mio_outsel_15]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_15_gated_we; |
| assign mio_outsel_15_gated_we = mio_outsel_15_we & mio_outsel_regwen_15_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_15_gated_we), |
| .wd (mio_outsel_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_outsel |
| // R[mio_outsel_16]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_16_gated_we; |
| assign mio_outsel_16_gated_we = mio_outsel_16_we & mio_outsel_regwen_16_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_16_gated_we), |
| .wd (mio_outsel_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_outsel |
| // R[mio_outsel_17]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_17_gated_we; |
| assign mio_outsel_17_gated_we = mio_outsel_17_we & mio_outsel_regwen_17_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_17_gated_we), |
| .wd (mio_outsel_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_outsel |
| // R[mio_outsel_18]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_18_gated_we; |
| assign mio_outsel_18_gated_we = mio_outsel_18_we & mio_outsel_regwen_18_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_18_gated_we), |
| .wd (mio_outsel_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_outsel |
| // R[mio_outsel_19]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_19_gated_we; |
| assign mio_outsel_19_gated_we = mio_outsel_19_we & mio_outsel_regwen_19_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_19_gated_we), |
| .wd (mio_outsel_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_outsel |
| // R[mio_outsel_20]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_20_gated_we; |
| assign mio_outsel_20_gated_we = mio_outsel_20_we & mio_outsel_regwen_20_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_20_gated_we), |
| .wd (mio_outsel_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_outsel |
| // R[mio_outsel_21]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_21_gated_we; |
| assign mio_outsel_21_gated_we = mio_outsel_21_we & mio_outsel_regwen_21_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_21_gated_we), |
| .wd (mio_outsel_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_outsel |
| // R[mio_outsel_22]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_22_gated_we; |
| assign mio_outsel_22_gated_we = mio_outsel_22_we & mio_outsel_regwen_22_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_22_gated_we), |
| .wd (mio_outsel_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_outsel |
| // R[mio_outsel_23]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_23_gated_we; |
| assign mio_outsel_23_gated_we = mio_outsel_23_we & mio_outsel_regwen_23_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_23_gated_we), |
| .wd (mio_outsel_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_outsel |
| // R[mio_outsel_24]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_24_gated_we; |
| assign mio_outsel_24_gated_we = mio_outsel_24_we & mio_outsel_regwen_24_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_24_gated_we), |
| .wd (mio_outsel_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_outsel |
| // R[mio_outsel_25]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_25_gated_we; |
| assign mio_outsel_25_gated_we = mio_outsel_25_we & mio_outsel_regwen_25_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_25_gated_we), |
| .wd (mio_outsel_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_outsel |
| // R[mio_outsel_26]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_26_gated_we; |
| assign mio_outsel_26_gated_we = mio_outsel_26_we & mio_outsel_regwen_26_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_26_gated_we), |
| .wd (mio_outsel_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_outsel |
| // R[mio_outsel_27]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_27_gated_we; |
| assign mio_outsel_27_gated_we = mio_outsel_27_we & mio_outsel_regwen_27_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_27_gated_we), |
| .wd (mio_outsel_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_outsel |
| // R[mio_outsel_28]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_28_gated_we; |
| assign mio_outsel_28_gated_we = mio_outsel_28_we & mio_outsel_regwen_28_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_28_gated_we), |
| .wd (mio_outsel_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_outsel |
| // R[mio_outsel_29]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_29_gated_we; |
| assign mio_outsel_29_gated_we = mio_outsel_29_we & mio_outsel_regwen_29_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_29_gated_we), |
| .wd (mio_outsel_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_outsel |
| // R[mio_outsel_30]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_30_gated_we; |
| assign mio_outsel_30_gated_we = mio_outsel_30_we & mio_outsel_regwen_30_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_30_gated_we), |
| .wd (mio_outsel_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[30].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_outsel |
| // R[mio_outsel_31]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_outsel_31_gated_we; |
| assign mio_outsel_31_gated_we = mio_outsel_31_we & mio_outsel_regwen_31_qs; |
| prim_subreg #( |
| .DW (6), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (6'h2) |
| ) u_mio_outsel_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_outsel_31_gated_we), |
| .wd (mio_outsel_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_outsel[31].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_outsel_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_0_we), |
| .wd (mio_pad_attr_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_1_we), |
| .wd (mio_pad_attr_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_2_we), |
| .wd (mio_pad_attr_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_3_we), |
| .wd (mio_pad_attr_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_4_we), |
| .wd (mio_pad_attr_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_5_we), |
| .wd (mio_pad_attr_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_6_we), |
| .wd (mio_pad_attr_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_7_we), |
| .wd (mio_pad_attr_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_8]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_8_we), |
| .wd (mio_pad_attr_regwen_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_9]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_9_we), |
| .wd (mio_pad_attr_regwen_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_10]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_10_we), |
| .wd (mio_pad_attr_regwen_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_11]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_11_we), |
| .wd (mio_pad_attr_regwen_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_12]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_12_we), |
| .wd (mio_pad_attr_regwen_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_13]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_13_we), |
| .wd (mio_pad_attr_regwen_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_14]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_14_we), |
| .wd (mio_pad_attr_regwen_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_15]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_15_we), |
| .wd (mio_pad_attr_regwen_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_16]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_16_we), |
| .wd (mio_pad_attr_regwen_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_17]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_17_we), |
| .wd (mio_pad_attr_regwen_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_18]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_18_we), |
| .wd (mio_pad_attr_regwen_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_19]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_19_we), |
| .wd (mio_pad_attr_regwen_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_20]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_20_we), |
| .wd (mio_pad_attr_regwen_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_21]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_21_we), |
| .wd (mio_pad_attr_regwen_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_22]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_22_we), |
| .wd (mio_pad_attr_regwen_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_23]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_23_we), |
| .wd (mio_pad_attr_regwen_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_24]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_24_we), |
| .wd (mio_pad_attr_regwen_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_25]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_25_we), |
| .wd (mio_pad_attr_regwen_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_26]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_26_we), |
| .wd (mio_pad_attr_regwen_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_27]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_27_we), |
| .wd (mio_pad_attr_regwen_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_28]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_28_we), |
| .wd (mio_pad_attr_regwen_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_29]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_29_we), |
| .wd (mio_pad_attr_regwen_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_30]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_30_we), |
| .wd (mio_pad_attr_regwen_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_pad_attr_regwen |
| // R[mio_pad_attr_regwen_31]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_attr_regwen_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_attr_regwen_31_we), |
| .wd (mio_pad_attr_regwen_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_attr_regwen_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_pad_attr |
| // R[mio_pad_attr_0]: V(True) |
| logic mio_pad_attr_0_qe; |
| logic [8:0] mio_pad_attr_0_flds_we; |
| assign mio_pad_attr_0_qe = &mio_pad_attr_0_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_0_gated_we; |
| assign mio_pad_attr_0_gated_we = mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs; |
| // F[invert_0]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_invert_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_invert_0_wd), |
| .d (hw2reg.mio_pad_attr[0].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[0].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_0_invert_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].invert.qe = mio_pad_attr_0_qe; |
| |
| // F[virtual_od_en_0]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_virtual_od_en_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_virtual_od_en_0_wd), |
| .d (hw2reg.mio_pad_attr[0].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[0].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_0_virtual_od_en_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].virtual_od_en.qe = mio_pad_attr_0_qe; |
| |
| // F[pull_en_0]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_pull_en_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_pull_en_0_wd), |
| .d (hw2reg.mio_pad_attr[0].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[0].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_0_pull_en_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].pull_en.qe = mio_pad_attr_0_qe; |
| |
| // F[pull_select_0]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_pull_select_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_pull_select_0_wd), |
| .d (hw2reg.mio_pad_attr[0].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[0].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_0_pull_select_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].pull_select.qe = mio_pad_attr_0_qe; |
| |
| // F[keeper_en_0]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_keeper_en_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_keeper_en_0_wd), |
| .d (hw2reg.mio_pad_attr[0].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[0].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_0_keeper_en_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].keeper_en.qe = mio_pad_attr_0_qe; |
| |
| // F[schmitt_en_0]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_schmitt_en_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_schmitt_en_0_wd), |
| .d (hw2reg.mio_pad_attr[0].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[0].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_0_schmitt_en_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].schmitt_en.qe = mio_pad_attr_0_qe; |
| |
| // F[od_en_0]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_0_od_en_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_od_en_0_wd), |
| .d (hw2reg.mio_pad_attr[0].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[0].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_0_od_en_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].od_en.qe = mio_pad_attr_0_qe; |
| |
| // F[slew_rate_0]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_0_slew_rate_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_slew_rate_0_wd), |
| .d (hw2reg.mio_pad_attr[0].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[0].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_0_slew_rate_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].slew_rate.qe = mio_pad_attr_0_qe; |
| |
| // F[drive_strength_0]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_0_drive_strength_0 ( |
| .re (mio_pad_attr_0_re), |
| .we (mio_pad_attr_0_gated_we), |
| .wd (mio_pad_attr_0_drive_strength_0_wd), |
| .d (hw2reg.mio_pad_attr[0].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_0_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[0].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_0_drive_strength_0_qs) |
| ); |
| assign reg2hw.mio_pad_attr[0].drive_strength.qe = mio_pad_attr_0_qe; |
| |
| |
| // Subregister 1 of Multireg mio_pad_attr |
| // R[mio_pad_attr_1]: V(True) |
| logic mio_pad_attr_1_qe; |
| logic [8:0] mio_pad_attr_1_flds_we; |
| assign mio_pad_attr_1_qe = &mio_pad_attr_1_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_1_gated_we; |
| assign mio_pad_attr_1_gated_we = mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs; |
| // F[invert_1]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_invert_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_invert_1_wd), |
| .d (hw2reg.mio_pad_attr[1].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[1].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_1_invert_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].invert.qe = mio_pad_attr_1_qe; |
| |
| // F[virtual_od_en_1]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_virtual_od_en_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_virtual_od_en_1_wd), |
| .d (hw2reg.mio_pad_attr[1].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[1].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_1_virtual_od_en_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].virtual_od_en.qe = mio_pad_attr_1_qe; |
| |
| // F[pull_en_1]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_pull_en_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_pull_en_1_wd), |
| .d (hw2reg.mio_pad_attr[1].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[1].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_1_pull_en_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].pull_en.qe = mio_pad_attr_1_qe; |
| |
| // F[pull_select_1]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_pull_select_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_pull_select_1_wd), |
| .d (hw2reg.mio_pad_attr[1].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[1].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_1_pull_select_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].pull_select.qe = mio_pad_attr_1_qe; |
| |
| // F[keeper_en_1]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_keeper_en_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_keeper_en_1_wd), |
| .d (hw2reg.mio_pad_attr[1].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[1].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_1_keeper_en_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].keeper_en.qe = mio_pad_attr_1_qe; |
| |
| // F[schmitt_en_1]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_schmitt_en_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_schmitt_en_1_wd), |
| .d (hw2reg.mio_pad_attr[1].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[1].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_1_schmitt_en_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].schmitt_en.qe = mio_pad_attr_1_qe; |
| |
| // F[od_en_1]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_1_od_en_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_od_en_1_wd), |
| .d (hw2reg.mio_pad_attr[1].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[1].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_1_od_en_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].od_en.qe = mio_pad_attr_1_qe; |
| |
| // F[slew_rate_1]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_1_slew_rate_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_slew_rate_1_wd), |
| .d (hw2reg.mio_pad_attr[1].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[1].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_1_slew_rate_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].slew_rate.qe = mio_pad_attr_1_qe; |
| |
| // F[drive_strength_1]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_1_drive_strength_1 ( |
| .re (mio_pad_attr_1_re), |
| .we (mio_pad_attr_1_gated_we), |
| .wd (mio_pad_attr_1_drive_strength_1_wd), |
| .d (hw2reg.mio_pad_attr[1].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_1_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[1].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_1_drive_strength_1_qs) |
| ); |
| assign reg2hw.mio_pad_attr[1].drive_strength.qe = mio_pad_attr_1_qe; |
| |
| |
| // Subregister 2 of Multireg mio_pad_attr |
| // R[mio_pad_attr_2]: V(True) |
| logic mio_pad_attr_2_qe; |
| logic [8:0] mio_pad_attr_2_flds_we; |
| assign mio_pad_attr_2_qe = &mio_pad_attr_2_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_2_gated_we; |
| assign mio_pad_attr_2_gated_we = mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs; |
| // F[invert_2]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_invert_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_invert_2_wd), |
| .d (hw2reg.mio_pad_attr[2].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[2].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_2_invert_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].invert.qe = mio_pad_attr_2_qe; |
| |
| // F[virtual_od_en_2]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_virtual_od_en_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_virtual_od_en_2_wd), |
| .d (hw2reg.mio_pad_attr[2].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[2].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_2_virtual_od_en_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].virtual_od_en.qe = mio_pad_attr_2_qe; |
| |
| // F[pull_en_2]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_pull_en_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_pull_en_2_wd), |
| .d (hw2reg.mio_pad_attr[2].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[2].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_2_pull_en_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].pull_en.qe = mio_pad_attr_2_qe; |
| |
| // F[pull_select_2]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_pull_select_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_pull_select_2_wd), |
| .d (hw2reg.mio_pad_attr[2].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[2].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_2_pull_select_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].pull_select.qe = mio_pad_attr_2_qe; |
| |
| // F[keeper_en_2]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_keeper_en_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_keeper_en_2_wd), |
| .d (hw2reg.mio_pad_attr[2].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[2].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_2_keeper_en_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].keeper_en.qe = mio_pad_attr_2_qe; |
| |
| // F[schmitt_en_2]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_schmitt_en_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_schmitt_en_2_wd), |
| .d (hw2reg.mio_pad_attr[2].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[2].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_2_schmitt_en_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].schmitt_en.qe = mio_pad_attr_2_qe; |
| |
| // F[od_en_2]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_2_od_en_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_od_en_2_wd), |
| .d (hw2reg.mio_pad_attr[2].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[2].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_2_od_en_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].od_en.qe = mio_pad_attr_2_qe; |
| |
| // F[slew_rate_2]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_2_slew_rate_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_slew_rate_2_wd), |
| .d (hw2reg.mio_pad_attr[2].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[2].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_2_slew_rate_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].slew_rate.qe = mio_pad_attr_2_qe; |
| |
| // F[drive_strength_2]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_2_drive_strength_2 ( |
| .re (mio_pad_attr_2_re), |
| .we (mio_pad_attr_2_gated_we), |
| .wd (mio_pad_attr_2_drive_strength_2_wd), |
| .d (hw2reg.mio_pad_attr[2].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_2_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[2].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_2_drive_strength_2_qs) |
| ); |
| assign reg2hw.mio_pad_attr[2].drive_strength.qe = mio_pad_attr_2_qe; |
| |
| |
| // Subregister 3 of Multireg mio_pad_attr |
| // R[mio_pad_attr_3]: V(True) |
| logic mio_pad_attr_3_qe; |
| logic [8:0] mio_pad_attr_3_flds_we; |
| assign mio_pad_attr_3_qe = &mio_pad_attr_3_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_3_gated_we; |
| assign mio_pad_attr_3_gated_we = mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs; |
| // F[invert_3]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_invert_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_invert_3_wd), |
| .d (hw2reg.mio_pad_attr[3].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[3].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_3_invert_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].invert.qe = mio_pad_attr_3_qe; |
| |
| // F[virtual_od_en_3]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_virtual_od_en_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_virtual_od_en_3_wd), |
| .d (hw2reg.mio_pad_attr[3].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[3].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_3_virtual_od_en_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].virtual_od_en.qe = mio_pad_attr_3_qe; |
| |
| // F[pull_en_3]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_pull_en_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_pull_en_3_wd), |
| .d (hw2reg.mio_pad_attr[3].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[3].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_3_pull_en_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].pull_en.qe = mio_pad_attr_3_qe; |
| |
| // F[pull_select_3]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_pull_select_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_pull_select_3_wd), |
| .d (hw2reg.mio_pad_attr[3].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[3].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_3_pull_select_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].pull_select.qe = mio_pad_attr_3_qe; |
| |
| // F[keeper_en_3]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_keeper_en_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_keeper_en_3_wd), |
| .d (hw2reg.mio_pad_attr[3].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[3].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_3_keeper_en_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].keeper_en.qe = mio_pad_attr_3_qe; |
| |
| // F[schmitt_en_3]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_schmitt_en_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_schmitt_en_3_wd), |
| .d (hw2reg.mio_pad_attr[3].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[3].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_3_schmitt_en_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].schmitt_en.qe = mio_pad_attr_3_qe; |
| |
| // F[od_en_3]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_3_od_en_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_od_en_3_wd), |
| .d (hw2reg.mio_pad_attr[3].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[3].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_3_od_en_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].od_en.qe = mio_pad_attr_3_qe; |
| |
| // F[slew_rate_3]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_3_slew_rate_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_slew_rate_3_wd), |
| .d (hw2reg.mio_pad_attr[3].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[3].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_3_slew_rate_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].slew_rate.qe = mio_pad_attr_3_qe; |
| |
| // F[drive_strength_3]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_3_drive_strength_3 ( |
| .re (mio_pad_attr_3_re), |
| .we (mio_pad_attr_3_gated_we), |
| .wd (mio_pad_attr_3_drive_strength_3_wd), |
| .d (hw2reg.mio_pad_attr[3].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_3_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[3].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_3_drive_strength_3_qs) |
| ); |
| assign reg2hw.mio_pad_attr[3].drive_strength.qe = mio_pad_attr_3_qe; |
| |
| |
| // Subregister 4 of Multireg mio_pad_attr |
| // R[mio_pad_attr_4]: V(True) |
| logic mio_pad_attr_4_qe; |
| logic [8:0] mio_pad_attr_4_flds_we; |
| assign mio_pad_attr_4_qe = &mio_pad_attr_4_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_4_gated_we; |
| assign mio_pad_attr_4_gated_we = mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs; |
| // F[invert_4]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_invert_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_invert_4_wd), |
| .d (hw2reg.mio_pad_attr[4].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[4].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_4_invert_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].invert.qe = mio_pad_attr_4_qe; |
| |
| // F[virtual_od_en_4]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_virtual_od_en_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_virtual_od_en_4_wd), |
| .d (hw2reg.mio_pad_attr[4].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[4].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_4_virtual_od_en_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].virtual_od_en.qe = mio_pad_attr_4_qe; |
| |
| // F[pull_en_4]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_pull_en_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_pull_en_4_wd), |
| .d (hw2reg.mio_pad_attr[4].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[4].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_4_pull_en_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].pull_en.qe = mio_pad_attr_4_qe; |
| |
| // F[pull_select_4]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_pull_select_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_pull_select_4_wd), |
| .d (hw2reg.mio_pad_attr[4].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[4].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_4_pull_select_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].pull_select.qe = mio_pad_attr_4_qe; |
| |
| // F[keeper_en_4]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_keeper_en_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_keeper_en_4_wd), |
| .d (hw2reg.mio_pad_attr[4].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[4].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_4_keeper_en_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].keeper_en.qe = mio_pad_attr_4_qe; |
| |
| // F[schmitt_en_4]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_schmitt_en_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_schmitt_en_4_wd), |
| .d (hw2reg.mio_pad_attr[4].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[4].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_4_schmitt_en_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].schmitt_en.qe = mio_pad_attr_4_qe; |
| |
| // F[od_en_4]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_4_od_en_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_od_en_4_wd), |
| .d (hw2reg.mio_pad_attr[4].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[4].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_4_od_en_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].od_en.qe = mio_pad_attr_4_qe; |
| |
| // F[slew_rate_4]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_4_slew_rate_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_slew_rate_4_wd), |
| .d (hw2reg.mio_pad_attr[4].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[4].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_4_slew_rate_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].slew_rate.qe = mio_pad_attr_4_qe; |
| |
| // F[drive_strength_4]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_4_drive_strength_4 ( |
| .re (mio_pad_attr_4_re), |
| .we (mio_pad_attr_4_gated_we), |
| .wd (mio_pad_attr_4_drive_strength_4_wd), |
| .d (hw2reg.mio_pad_attr[4].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_4_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[4].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_4_drive_strength_4_qs) |
| ); |
| assign reg2hw.mio_pad_attr[4].drive_strength.qe = mio_pad_attr_4_qe; |
| |
| |
| // Subregister 5 of Multireg mio_pad_attr |
| // R[mio_pad_attr_5]: V(True) |
| logic mio_pad_attr_5_qe; |
| logic [8:0] mio_pad_attr_5_flds_we; |
| assign mio_pad_attr_5_qe = &mio_pad_attr_5_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_5_gated_we; |
| assign mio_pad_attr_5_gated_we = mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs; |
| // F[invert_5]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_invert_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_invert_5_wd), |
| .d (hw2reg.mio_pad_attr[5].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[5].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_5_invert_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].invert.qe = mio_pad_attr_5_qe; |
| |
| // F[virtual_od_en_5]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_virtual_od_en_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_virtual_od_en_5_wd), |
| .d (hw2reg.mio_pad_attr[5].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[5].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_5_virtual_od_en_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].virtual_od_en.qe = mio_pad_attr_5_qe; |
| |
| // F[pull_en_5]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_pull_en_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_pull_en_5_wd), |
| .d (hw2reg.mio_pad_attr[5].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[5].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_5_pull_en_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].pull_en.qe = mio_pad_attr_5_qe; |
| |
| // F[pull_select_5]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_pull_select_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_pull_select_5_wd), |
| .d (hw2reg.mio_pad_attr[5].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[5].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_5_pull_select_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].pull_select.qe = mio_pad_attr_5_qe; |
| |
| // F[keeper_en_5]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_keeper_en_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_keeper_en_5_wd), |
| .d (hw2reg.mio_pad_attr[5].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[5].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_5_keeper_en_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].keeper_en.qe = mio_pad_attr_5_qe; |
| |
| // F[schmitt_en_5]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_schmitt_en_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_schmitt_en_5_wd), |
| .d (hw2reg.mio_pad_attr[5].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[5].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_5_schmitt_en_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].schmitt_en.qe = mio_pad_attr_5_qe; |
| |
| // F[od_en_5]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_5_od_en_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_od_en_5_wd), |
| .d (hw2reg.mio_pad_attr[5].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[5].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_5_od_en_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].od_en.qe = mio_pad_attr_5_qe; |
| |
| // F[slew_rate_5]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_5_slew_rate_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_slew_rate_5_wd), |
| .d (hw2reg.mio_pad_attr[5].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[5].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_5_slew_rate_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].slew_rate.qe = mio_pad_attr_5_qe; |
| |
| // F[drive_strength_5]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_5_drive_strength_5 ( |
| .re (mio_pad_attr_5_re), |
| .we (mio_pad_attr_5_gated_we), |
| .wd (mio_pad_attr_5_drive_strength_5_wd), |
| .d (hw2reg.mio_pad_attr[5].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_5_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[5].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_5_drive_strength_5_qs) |
| ); |
| assign reg2hw.mio_pad_attr[5].drive_strength.qe = mio_pad_attr_5_qe; |
| |
| |
| // Subregister 6 of Multireg mio_pad_attr |
| // R[mio_pad_attr_6]: V(True) |
| logic mio_pad_attr_6_qe; |
| logic [8:0] mio_pad_attr_6_flds_we; |
| assign mio_pad_attr_6_qe = &mio_pad_attr_6_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_6_gated_we; |
| assign mio_pad_attr_6_gated_we = mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs; |
| // F[invert_6]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_invert_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_invert_6_wd), |
| .d (hw2reg.mio_pad_attr[6].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[6].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_6_invert_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].invert.qe = mio_pad_attr_6_qe; |
| |
| // F[virtual_od_en_6]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_virtual_od_en_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_virtual_od_en_6_wd), |
| .d (hw2reg.mio_pad_attr[6].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[6].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_6_virtual_od_en_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].virtual_od_en.qe = mio_pad_attr_6_qe; |
| |
| // F[pull_en_6]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_pull_en_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_pull_en_6_wd), |
| .d (hw2reg.mio_pad_attr[6].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[6].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_6_pull_en_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].pull_en.qe = mio_pad_attr_6_qe; |
| |
| // F[pull_select_6]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_pull_select_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_pull_select_6_wd), |
| .d (hw2reg.mio_pad_attr[6].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[6].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_6_pull_select_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].pull_select.qe = mio_pad_attr_6_qe; |
| |
| // F[keeper_en_6]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_keeper_en_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_keeper_en_6_wd), |
| .d (hw2reg.mio_pad_attr[6].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[6].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_6_keeper_en_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].keeper_en.qe = mio_pad_attr_6_qe; |
| |
| // F[schmitt_en_6]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_schmitt_en_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_schmitt_en_6_wd), |
| .d (hw2reg.mio_pad_attr[6].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[6].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_6_schmitt_en_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].schmitt_en.qe = mio_pad_attr_6_qe; |
| |
| // F[od_en_6]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_6_od_en_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_od_en_6_wd), |
| .d (hw2reg.mio_pad_attr[6].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[6].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_6_od_en_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].od_en.qe = mio_pad_attr_6_qe; |
| |
| // F[slew_rate_6]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_6_slew_rate_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_slew_rate_6_wd), |
| .d (hw2reg.mio_pad_attr[6].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[6].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_6_slew_rate_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].slew_rate.qe = mio_pad_attr_6_qe; |
| |
| // F[drive_strength_6]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_6_drive_strength_6 ( |
| .re (mio_pad_attr_6_re), |
| .we (mio_pad_attr_6_gated_we), |
| .wd (mio_pad_attr_6_drive_strength_6_wd), |
| .d (hw2reg.mio_pad_attr[6].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_6_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[6].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_6_drive_strength_6_qs) |
| ); |
| assign reg2hw.mio_pad_attr[6].drive_strength.qe = mio_pad_attr_6_qe; |
| |
| |
| // Subregister 7 of Multireg mio_pad_attr |
| // R[mio_pad_attr_7]: V(True) |
| logic mio_pad_attr_7_qe; |
| logic [8:0] mio_pad_attr_7_flds_we; |
| assign mio_pad_attr_7_qe = &mio_pad_attr_7_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_7_gated_we; |
| assign mio_pad_attr_7_gated_we = mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs; |
| // F[invert_7]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_invert_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_invert_7_wd), |
| .d (hw2reg.mio_pad_attr[7].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[7].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_7_invert_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].invert.qe = mio_pad_attr_7_qe; |
| |
| // F[virtual_od_en_7]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_virtual_od_en_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_virtual_od_en_7_wd), |
| .d (hw2reg.mio_pad_attr[7].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[7].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_7_virtual_od_en_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].virtual_od_en.qe = mio_pad_attr_7_qe; |
| |
| // F[pull_en_7]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_pull_en_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_pull_en_7_wd), |
| .d (hw2reg.mio_pad_attr[7].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[7].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_7_pull_en_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].pull_en.qe = mio_pad_attr_7_qe; |
| |
| // F[pull_select_7]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_pull_select_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_pull_select_7_wd), |
| .d (hw2reg.mio_pad_attr[7].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[7].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_7_pull_select_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].pull_select.qe = mio_pad_attr_7_qe; |
| |
| // F[keeper_en_7]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_keeper_en_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_keeper_en_7_wd), |
| .d (hw2reg.mio_pad_attr[7].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[7].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_7_keeper_en_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].keeper_en.qe = mio_pad_attr_7_qe; |
| |
| // F[schmitt_en_7]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_schmitt_en_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_schmitt_en_7_wd), |
| .d (hw2reg.mio_pad_attr[7].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[7].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_7_schmitt_en_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].schmitt_en.qe = mio_pad_attr_7_qe; |
| |
| // F[od_en_7]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_7_od_en_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_od_en_7_wd), |
| .d (hw2reg.mio_pad_attr[7].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[7].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_7_od_en_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].od_en.qe = mio_pad_attr_7_qe; |
| |
| // F[slew_rate_7]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_7_slew_rate_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_slew_rate_7_wd), |
| .d (hw2reg.mio_pad_attr[7].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[7].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_7_slew_rate_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].slew_rate.qe = mio_pad_attr_7_qe; |
| |
| // F[drive_strength_7]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_7_drive_strength_7 ( |
| .re (mio_pad_attr_7_re), |
| .we (mio_pad_attr_7_gated_we), |
| .wd (mio_pad_attr_7_drive_strength_7_wd), |
| .d (hw2reg.mio_pad_attr[7].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_7_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[7].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_7_drive_strength_7_qs) |
| ); |
| assign reg2hw.mio_pad_attr[7].drive_strength.qe = mio_pad_attr_7_qe; |
| |
| |
| // Subregister 8 of Multireg mio_pad_attr |
| // R[mio_pad_attr_8]: V(True) |
| logic mio_pad_attr_8_qe; |
| logic [8:0] mio_pad_attr_8_flds_we; |
| assign mio_pad_attr_8_qe = &mio_pad_attr_8_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_8_gated_we; |
| assign mio_pad_attr_8_gated_we = mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs; |
| // F[invert_8]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_invert_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_invert_8_wd), |
| .d (hw2reg.mio_pad_attr[8].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[8].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_8_invert_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].invert.qe = mio_pad_attr_8_qe; |
| |
| // F[virtual_od_en_8]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_virtual_od_en_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_virtual_od_en_8_wd), |
| .d (hw2reg.mio_pad_attr[8].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[8].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_8_virtual_od_en_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].virtual_od_en.qe = mio_pad_attr_8_qe; |
| |
| // F[pull_en_8]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_pull_en_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_pull_en_8_wd), |
| .d (hw2reg.mio_pad_attr[8].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[8].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_8_pull_en_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].pull_en.qe = mio_pad_attr_8_qe; |
| |
| // F[pull_select_8]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_pull_select_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_pull_select_8_wd), |
| .d (hw2reg.mio_pad_attr[8].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[8].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_8_pull_select_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].pull_select.qe = mio_pad_attr_8_qe; |
| |
| // F[keeper_en_8]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_keeper_en_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_keeper_en_8_wd), |
| .d (hw2reg.mio_pad_attr[8].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[8].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_8_keeper_en_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].keeper_en.qe = mio_pad_attr_8_qe; |
| |
| // F[schmitt_en_8]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_schmitt_en_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_schmitt_en_8_wd), |
| .d (hw2reg.mio_pad_attr[8].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[8].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_8_schmitt_en_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].schmitt_en.qe = mio_pad_attr_8_qe; |
| |
| // F[od_en_8]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_8_od_en_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_od_en_8_wd), |
| .d (hw2reg.mio_pad_attr[8].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[8].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_8_od_en_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].od_en.qe = mio_pad_attr_8_qe; |
| |
| // F[slew_rate_8]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_8_slew_rate_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_slew_rate_8_wd), |
| .d (hw2reg.mio_pad_attr[8].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[8].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_8_slew_rate_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].slew_rate.qe = mio_pad_attr_8_qe; |
| |
| // F[drive_strength_8]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_8_drive_strength_8 ( |
| .re (mio_pad_attr_8_re), |
| .we (mio_pad_attr_8_gated_we), |
| .wd (mio_pad_attr_8_drive_strength_8_wd), |
| .d (hw2reg.mio_pad_attr[8].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_8_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[8].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_8_drive_strength_8_qs) |
| ); |
| assign reg2hw.mio_pad_attr[8].drive_strength.qe = mio_pad_attr_8_qe; |
| |
| |
| // Subregister 9 of Multireg mio_pad_attr |
| // R[mio_pad_attr_9]: V(True) |
| logic mio_pad_attr_9_qe; |
| logic [8:0] mio_pad_attr_9_flds_we; |
| assign mio_pad_attr_9_qe = &mio_pad_attr_9_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_9_gated_we; |
| assign mio_pad_attr_9_gated_we = mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs; |
| // F[invert_9]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_invert_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_invert_9_wd), |
| .d (hw2reg.mio_pad_attr[9].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[9].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_9_invert_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].invert.qe = mio_pad_attr_9_qe; |
| |
| // F[virtual_od_en_9]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_virtual_od_en_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_virtual_od_en_9_wd), |
| .d (hw2reg.mio_pad_attr[9].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[9].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_9_virtual_od_en_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].virtual_od_en.qe = mio_pad_attr_9_qe; |
| |
| // F[pull_en_9]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_pull_en_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_pull_en_9_wd), |
| .d (hw2reg.mio_pad_attr[9].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[9].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_9_pull_en_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].pull_en.qe = mio_pad_attr_9_qe; |
| |
| // F[pull_select_9]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_pull_select_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_pull_select_9_wd), |
| .d (hw2reg.mio_pad_attr[9].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[9].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_9_pull_select_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].pull_select.qe = mio_pad_attr_9_qe; |
| |
| // F[keeper_en_9]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_keeper_en_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_keeper_en_9_wd), |
| .d (hw2reg.mio_pad_attr[9].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[9].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_9_keeper_en_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].keeper_en.qe = mio_pad_attr_9_qe; |
| |
| // F[schmitt_en_9]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_schmitt_en_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_schmitt_en_9_wd), |
| .d (hw2reg.mio_pad_attr[9].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[9].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_9_schmitt_en_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].schmitt_en.qe = mio_pad_attr_9_qe; |
| |
| // F[od_en_9]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_9_od_en_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_od_en_9_wd), |
| .d (hw2reg.mio_pad_attr[9].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[9].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_9_od_en_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].od_en.qe = mio_pad_attr_9_qe; |
| |
| // F[slew_rate_9]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_9_slew_rate_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_slew_rate_9_wd), |
| .d (hw2reg.mio_pad_attr[9].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[9].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_9_slew_rate_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].slew_rate.qe = mio_pad_attr_9_qe; |
| |
| // F[drive_strength_9]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_9_drive_strength_9 ( |
| .re (mio_pad_attr_9_re), |
| .we (mio_pad_attr_9_gated_we), |
| .wd (mio_pad_attr_9_drive_strength_9_wd), |
| .d (hw2reg.mio_pad_attr[9].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_9_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[9].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_9_drive_strength_9_qs) |
| ); |
| assign reg2hw.mio_pad_attr[9].drive_strength.qe = mio_pad_attr_9_qe; |
| |
| |
| // Subregister 10 of Multireg mio_pad_attr |
| // R[mio_pad_attr_10]: V(True) |
| logic mio_pad_attr_10_qe; |
| logic [8:0] mio_pad_attr_10_flds_we; |
| assign mio_pad_attr_10_qe = &mio_pad_attr_10_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_10_gated_we; |
| assign mio_pad_attr_10_gated_we = mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs; |
| // F[invert_10]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_invert_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_invert_10_wd), |
| .d (hw2reg.mio_pad_attr[10].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[10].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_10_invert_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].invert.qe = mio_pad_attr_10_qe; |
| |
| // F[virtual_od_en_10]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_virtual_od_en_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_virtual_od_en_10_wd), |
| .d (hw2reg.mio_pad_attr[10].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[10].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_10_virtual_od_en_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].virtual_od_en.qe = mio_pad_attr_10_qe; |
| |
| // F[pull_en_10]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_pull_en_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_pull_en_10_wd), |
| .d (hw2reg.mio_pad_attr[10].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[10].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_10_pull_en_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].pull_en.qe = mio_pad_attr_10_qe; |
| |
| // F[pull_select_10]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_pull_select_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_pull_select_10_wd), |
| .d (hw2reg.mio_pad_attr[10].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[10].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_10_pull_select_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].pull_select.qe = mio_pad_attr_10_qe; |
| |
| // F[keeper_en_10]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_keeper_en_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_keeper_en_10_wd), |
| .d (hw2reg.mio_pad_attr[10].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[10].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_10_keeper_en_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].keeper_en.qe = mio_pad_attr_10_qe; |
| |
| // F[schmitt_en_10]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_schmitt_en_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_schmitt_en_10_wd), |
| .d (hw2reg.mio_pad_attr[10].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[10].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_10_schmitt_en_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].schmitt_en.qe = mio_pad_attr_10_qe; |
| |
| // F[od_en_10]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_10_od_en_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_od_en_10_wd), |
| .d (hw2reg.mio_pad_attr[10].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[10].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_10_od_en_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].od_en.qe = mio_pad_attr_10_qe; |
| |
| // F[slew_rate_10]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_10_slew_rate_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_slew_rate_10_wd), |
| .d (hw2reg.mio_pad_attr[10].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[10].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_10_slew_rate_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].slew_rate.qe = mio_pad_attr_10_qe; |
| |
| // F[drive_strength_10]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_10_drive_strength_10 ( |
| .re (mio_pad_attr_10_re), |
| .we (mio_pad_attr_10_gated_we), |
| .wd (mio_pad_attr_10_drive_strength_10_wd), |
| .d (hw2reg.mio_pad_attr[10].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_10_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[10].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_10_drive_strength_10_qs) |
| ); |
| assign reg2hw.mio_pad_attr[10].drive_strength.qe = mio_pad_attr_10_qe; |
| |
| |
| // Subregister 11 of Multireg mio_pad_attr |
| // R[mio_pad_attr_11]: V(True) |
| logic mio_pad_attr_11_qe; |
| logic [8:0] mio_pad_attr_11_flds_we; |
| assign mio_pad_attr_11_qe = &mio_pad_attr_11_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_11_gated_we; |
| assign mio_pad_attr_11_gated_we = mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs; |
| // F[invert_11]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_invert_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_invert_11_wd), |
| .d (hw2reg.mio_pad_attr[11].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[11].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_11_invert_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].invert.qe = mio_pad_attr_11_qe; |
| |
| // F[virtual_od_en_11]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_virtual_od_en_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_virtual_od_en_11_wd), |
| .d (hw2reg.mio_pad_attr[11].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[11].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_11_virtual_od_en_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].virtual_od_en.qe = mio_pad_attr_11_qe; |
| |
| // F[pull_en_11]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_pull_en_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_pull_en_11_wd), |
| .d (hw2reg.mio_pad_attr[11].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[11].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_11_pull_en_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].pull_en.qe = mio_pad_attr_11_qe; |
| |
| // F[pull_select_11]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_pull_select_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_pull_select_11_wd), |
| .d (hw2reg.mio_pad_attr[11].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[11].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_11_pull_select_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].pull_select.qe = mio_pad_attr_11_qe; |
| |
| // F[keeper_en_11]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_keeper_en_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_keeper_en_11_wd), |
| .d (hw2reg.mio_pad_attr[11].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[11].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_11_keeper_en_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].keeper_en.qe = mio_pad_attr_11_qe; |
| |
| // F[schmitt_en_11]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_schmitt_en_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_schmitt_en_11_wd), |
| .d (hw2reg.mio_pad_attr[11].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[11].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_11_schmitt_en_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].schmitt_en.qe = mio_pad_attr_11_qe; |
| |
| // F[od_en_11]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_11_od_en_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_od_en_11_wd), |
| .d (hw2reg.mio_pad_attr[11].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[11].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_11_od_en_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].od_en.qe = mio_pad_attr_11_qe; |
| |
| // F[slew_rate_11]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_11_slew_rate_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_slew_rate_11_wd), |
| .d (hw2reg.mio_pad_attr[11].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[11].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_11_slew_rate_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].slew_rate.qe = mio_pad_attr_11_qe; |
| |
| // F[drive_strength_11]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_11_drive_strength_11 ( |
| .re (mio_pad_attr_11_re), |
| .we (mio_pad_attr_11_gated_we), |
| .wd (mio_pad_attr_11_drive_strength_11_wd), |
| .d (hw2reg.mio_pad_attr[11].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_11_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[11].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_11_drive_strength_11_qs) |
| ); |
| assign reg2hw.mio_pad_attr[11].drive_strength.qe = mio_pad_attr_11_qe; |
| |
| |
| // Subregister 12 of Multireg mio_pad_attr |
| // R[mio_pad_attr_12]: V(True) |
| logic mio_pad_attr_12_qe; |
| logic [8:0] mio_pad_attr_12_flds_we; |
| assign mio_pad_attr_12_qe = &mio_pad_attr_12_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_12_gated_we; |
| assign mio_pad_attr_12_gated_we = mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs; |
| // F[invert_12]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_invert_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_invert_12_wd), |
| .d (hw2reg.mio_pad_attr[12].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[12].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_12_invert_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].invert.qe = mio_pad_attr_12_qe; |
| |
| // F[virtual_od_en_12]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_virtual_od_en_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_virtual_od_en_12_wd), |
| .d (hw2reg.mio_pad_attr[12].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[12].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_12_virtual_od_en_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].virtual_od_en.qe = mio_pad_attr_12_qe; |
| |
| // F[pull_en_12]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_pull_en_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_pull_en_12_wd), |
| .d (hw2reg.mio_pad_attr[12].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[12].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_12_pull_en_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].pull_en.qe = mio_pad_attr_12_qe; |
| |
| // F[pull_select_12]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_pull_select_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_pull_select_12_wd), |
| .d (hw2reg.mio_pad_attr[12].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[12].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_12_pull_select_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].pull_select.qe = mio_pad_attr_12_qe; |
| |
| // F[keeper_en_12]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_keeper_en_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_keeper_en_12_wd), |
| .d (hw2reg.mio_pad_attr[12].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[12].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_12_keeper_en_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].keeper_en.qe = mio_pad_attr_12_qe; |
| |
| // F[schmitt_en_12]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_schmitt_en_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_schmitt_en_12_wd), |
| .d (hw2reg.mio_pad_attr[12].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[12].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_12_schmitt_en_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].schmitt_en.qe = mio_pad_attr_12_qe; |
| |
| // F[od_en_12]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_12_od_en_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_od_en_12_wd), |
| .d (hw2reg.mio_pad_attr[12].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[12].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_12_od_en_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].od_en.qe = mio_pad_attr_12_qe; |
| |
| // F[slew_rate_12]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_12_slew_rate_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_slew_rate_12_wd), |
| .d (hw2reg.mio_pad_attr[12].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[12].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_12_slew_rate_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].slew_rate.qe = mio_pad_attr_12_qe; |
| |
| // F[drive_strength_12]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_12_drive_strength_12 ( |
| .re (mio_pad_attr_12_re), |
| .we (mio_pad_attr_12_gated_we), |
| .wd (mio_pad_attr_12_drive_strength_12_wd), |
| .d (hw2reg.mio_pad_attr[12].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_12_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[12].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_12_drive_strength_12_qs) |
| ); |
| assign reg2hw.mio_pad_attr[12].drive_strength.qe = mio_pad_attr_12_qe; |
| |
| |
| // Subregister 13 of Multireg mio_pad_attr |
| // R[mio_pad_attr_13]: V(True) |
| logic mio_pad_attr_13_qe; |
| logic [8:0] mio_pad_attr_13_flds_we; |
| assign mio_pad_attr_13_qe = &mio_pad_attr_13_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_13_gated_we; |
| assign mio_pad_attr_13_gated_we = mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs; |
| // F[invert_13]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_invert_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_invert_13_wd), |
| .d (hw2reg.mio_pad_attr[13].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[13].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_13_invert_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].invert.qe = mio_pad_attr_13_qe; |
| |
| // F[virtual_od_en_13]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_virtual_od_en_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_virtual_od_en_13_wd), |
| .d (hw2reg.mio_pad_attr[13].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[13].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_13_virtual_od_en_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].virtual_od_en.qe = mio_pad_attr_13_qe; |
| |
| // F[pull_en_13]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_pull_en_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_pull_en_13_wd), |
| .d (hw2reg.mio_pad_attr[13].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[13].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_13_pull_en_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].pull_en.qe = mio_pad_attr_13_qe; |
| |
| // F[pull_select_13]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_pull_select_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_pull_select_13_wd), |
| .d (hw2reg.mio_pad_attr[13].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[13].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_13_pull_select_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].pull_select.qe = mio_pad_attr_13_qe; |
| |
| // F[keeper_en_13]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_keeper_en_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_keeper_en_13_wd), |
| .d (hw2reg.mio_pad_attr[13].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[13].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_13_keeper_en_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].keeper_en.qe = mio_pad_attr_13_qe; |
| |
| // F[schmitt_en_13]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_schmitt_en_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_schmitt_en_13_wd), |
| .d (hw2reg.mio_pad_attr[13].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[13].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_13_schmitt_en_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].schmitt_en.qe = mio_pad_attr_13_qe; |
| |
| // F[od_en_13]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_13_od_en_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_od_en_13_wd), |
| .d (hw2reg.mio_pad_attr[13].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[13].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_13_od_en_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].od_en.qe = mio_pad_attr_13_qe; |
| |
| // F[slew_rate_13]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_13_slew_rate_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_slew_rate_13_wd), |
| .d (hw2reg.mio_pad_attr[13].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[13].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_13_slew_rate_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].slew_rate.qe = mio_pad_attr_13_qe; |
| |
| // F[drive_strength_13]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_13_drive_strength_13 ( |
| .re (mio_pad_attr_13_re), |
| .we (mio_pad_attr_13_gated_we), |
| .wd (mio_pad_attr_13_drive_strength_13_wd), |
| .d (hw2reg.mio_pad_attr[13].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_13_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[13].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_13_drive_strength_13_qs) |
| ); |
| assign reg2hw.mio_pad_attr[13].drive_strength.qe = mio_pad_attr_13_qe; |
| |
| |
| // Subregister 14 of Multireg mio_pad_attr |
| // R[mio_pad_attr_14]: V(True) |
| logic mio_pad_attr_14_qe; |
| logic [8:0] mio_pad_attr_14_flds_we; |
| assign mio_pad_attr_14_qe = &mio_pad_attr_14_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_14_gated_we; |
| assign mio_pad_attr_14_gated_we = mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs; |
| // F[invert_14]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_invert_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_invert_14_wd), |
| .d (hw2reg.mio_pad_attr[14].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[14].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_14_invert_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].invert.qe = mio_pad_attr_14_qe; |
| |
| // F[virtual_od_en_14]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_virtual_od_en_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_virtual_od_en_14_wd), |
| .d (hw2reg.mio_pad_attr[14].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[14].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_14_virtual_od_en_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].virtual_od_en.qe = mio_pad_attr_14_qe; |
| |
| // F[pull_en_14]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_pull_en_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_pull_en_14_wd), |
| .d (hw2reg.mio_pad_attr[14].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[14].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_14_pull_en_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].pull_en.qe = mio_pad_attr_14_qe; |
| |
| // F[pull_select_14]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_pull_select_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_pull_select_14_wd), |
| .d (hw2reg.mio_pad_attr[14].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[14].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_14_pull_select_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].pull_select.qe = mio_pad_attr_14_qe; |
| |
| // F[keeper_en_14]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_keeper_en_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_keeper_en_14_wd), |
| .d (hw2reg.mio_pad_attr[14].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[14].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_14_keeper_en_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].keeper_en.qe = mio_pad_attr_14_qe; |
| |
| // F[schmitt_en_14]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_schmitt_en_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_schmitt_en_14_wd), |
| .d (hw2reg.mio_pad_attr[14].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[14].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_14_schmitt_en_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].schmitt_en.qe = mio_pad_attr_14_qe; |
| |
| // F[od_en_14]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_14_od_en_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_od_en_14_wd), |
| .d (hw2reg.mio_pad_attr[14].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[14].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_14_od_en_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].od_en.qe = mio_pad_attr_14_qe; |
| |
| // F[slew_rate_14]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_14_slew_rate_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_slew_rate_14_wd), |
| .d (hw2reg.mio_pad_attr[14].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[14].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_14_slew_rate_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].slew_rate.qe = mio_pad_attr_14_qe; |
| |
| // F[drive_strength_14]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_14_drive_strength_14 ( |
| .re (mio_pad_attr_14_re), |
| .we (mio_pad_attr_14_gated_we), |
| .wd (mio_pad_attr_14_drive_strength_14_wd), |
| .d (hw2reg.mio_pad_attr[14].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_14_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[14].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_14_drive_strength_14_qs) |
| ); |
| assign reg2hw.mio_pad_attr[14].drive_strength.qe = mio_pad_attr_14_qe; |
| |
| |
| // Subregister 15 of Multireg mio_pad_attr |
| // R[mio_pad_attr_15]: V(True) |
| logic mio_pad_attr_15_qe; |
| logic [8:0] mio_pad_attr_15_flds_we; |
| assign mio_pad_attr_15_qe = &mio_pad_attr_15_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_15_gated_we; |
| assign mio_pad_attr_15_gated_we = mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs; |
| // F[invert_15]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_invert_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_invert_15_wd), |
| .d (hw2reg.mio_pad_attr[15].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[15].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_15_invert_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].invert.qe = mio_pad_attr_15_qe; |
| |
| // F[virtual_od_en_15]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_virtual_od_en_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_virtual_od_en_15_wd), |
| .d (hw2reg.mio_pad_attr[15].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[15].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_15_virtual_od_en_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].virtual_od_en.qe = mio_pad_attr_15_qe; |
| |
| // F[pull_en_15]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_pull_en_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_pull_en_15_wd), |
| .d (hw2reg.mio_pad_attr[15].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[15].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_15_pull_en_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].pull_en.qe = mio_pad_attr_15_qe; |
| |
| // F[pull_select_15]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_pull_select_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_pull_select_15_wd), |
| .d (hw2reg.mio_pad_attr[15].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[15].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_15_pull_select_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].pull_select.qe = mio_pad_attr_15_qe; |
| |
| // F[keeper_en_15]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_keeper_en_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_keeper_en_15_wd), |
| .d (hw2reg.mio_pad_attr[15].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[15].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_15_keeper_en_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].keeper_en.qe = mio_pad_attr_15_qe; |
| |
| // F[schmitt_en_15]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_schmitt_en_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_schmitt_en_15_wd), |
| .d (hw2reg.mio_pad_attr[15].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[15].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_15_schmitt_en_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].schmitt_en.qe = mio_pad_attr_15_qe; |
| |
| // F[od_en_15]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_15_od_en_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_od_en_15_wd), |
| .d (hw2reg.mio_pad_attr[15].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[15].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_15_od_en_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].od_en.qe = mio_pad_attr_15_qe; |
| |
| // F[slew_rate_15]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_15_slew_rate_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_slew_rate_15_wd), |
| .d (hw2reg.mio_pad_attr[15].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[15].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_15_slew_rate_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].slew_rate.qe = mio_pad_attr_15_qe; |
| |
| // F[drive_strength_15]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_15_drive_strength_15 ( |
| .re (mio_pad_attr_15_re), |
| .we (mio_pad_attr_15_gated_we), |
| .wd (mio_pad_attr_15_drive_strength_15_wd), |
| .d (hw2reg.mio_pad_attr[15].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_15_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[15].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_15_drive_strength_15_qs) |
| ); |
| assign reg2hw.mio_pad_attr[15].drive_strength.qe = mio_pad_attr_15_qe; |
| |
| |
| // Subregister 16 of Multireg mio_pad_attr |
| // R[mio_pad_attr_16]: V(True) |
| logic mio_pad_attr_16_qe; |
| logic [8:0] mio_pad_attr_16_flds_we; |
| assign mio_pad_attr_16_qe = &mio_pad_attr_16_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_16_gated_we; |
| assign mio_pad_attr_16_gated_we = mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs; |
| // F[invert_16]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_invert_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_invert_16_wd), |
| .d (hw2reg.mio_pad_attr[16].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[16].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_16_invert_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].invert.qe = mio_pad_attr_16_qe; |
| |
| // F[virtual_od_en_16]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_virtual_od_en_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_virtual_od_en_16_wd), |
| .d (hw2reg.mio_pad_attr[16].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[16].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_16_virtual_od_en_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].virtual_od_en.qe = mio_pad_attr_16_qe; |
| |
| // F[pull_en_16]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_pull_en_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_pull_en_16_wd), |
| .d (hw2reg.mio_pad_attr[16].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[16].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_16_pull_en_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].pull_en.qe = mio_pad_attr_16_qe; |
| |
| // F[pull_select_16]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_pull_select_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_pull_select_16_wd), |
| .d (hw2reg.mio_pad_attr[16].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[16].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_16_pull_select_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].pull_select.qe = mio_pad_attr_16_qe; |
| |
| // F[keeper_en_16]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_keeper_en_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_keeper_en_16_wd), |
| .d (hw2reg.mio_pad_attr[16].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[16].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_16_keeper_en_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].keeper_en.qe = mio_pad_attr_16_qe; |
| |
| // F[schmitt_en_16]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_schmitt_en_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_schmitt_en_16_wd), |
| .d (hw2reg.mio_pad_attr[16].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[16].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_16_schmitt_en_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].schmitt_en.qe = mio_pad_attr_16_qe; |
| |
| // F[od_en_16]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_16_od_en_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_od_en_16_wd), |
| .d (hw2reg.mio_pad_attr[16].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[16].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_16_od_en_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].od_en.qe = mio_pad_attr_16_qe; |
| |
| // F[slew_rate_16]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_16_slew_rate_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_slew_rate_16_wd), |
| .d (hw2reg.mio_pad_attr[16].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[16].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_16_slew_rate_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].slew_rate.qe = mio_pad_attr_16_qe; |
| |
| // F[drive_strength_16]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_16_drive_strength_16 ( |
| .re (mio_pad_attr_16_re), |
| .we (mio_pad_attr_16_gated_we), |
| .wd (mio_pad_attr_16_drive_strength_16_wd), |
| .d (hw2reg.mio_pad_attr[16].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_16_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[16].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_16_drive_strength_16_qs) |
| ); |
| assign reg2hw.mio_pad_attr[16].drive_strength.qe = mio_pad_attr_16_qe; |
| |
| |
| // Subregister 17 of Multireg mio_pad_attr |
| // R[mio_pad_attr_17]: V(True) |
| logic mio_pad_attr_17_qe; |
| logic [8:0] mio_pad_attr_17_flds_we; |
| assign mio_pad_attr_17_qe = &mio_pad_attr_17_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_17_gated_we; |
| assign mio_pad_attr_17_gated_we = mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs; |
| // F[invert_17]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_invert_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_invert_17_wd), |
| .d (hw2reg.mio_pad_attr[17].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[17].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_17_invert_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].invert.qe = mio_pad_attr_17_qe; |
| |
| // F[virtual_od_en_17]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_virtual_od_en_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_virtual_od_en_17_wd), |
| .d (hw2reg.mio_pad_attr[17].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[17].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_17_virtual_od_en_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].virtual_od_en.qe = mio_pad_attr_17_qe; |
| |
| // F[pull_en_17]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_pull_en_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_pull_en_17_wd), |
| .d (hw2reg.mio_pad_attr[17].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[17].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_17_pull_en_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].pull_en.qe = mio_pad_attr_17_qe; |
| |
| // F[pull_select_17]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_pull_select_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_pull_select_17_wd), |
| .d (hw2reg.mio_pad_attr[17].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[17].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_17_pull_select_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].pull_select.qe = mio_pad_attr_17_qe; |
| |
| // F[keeper_en_17]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_keeper_en_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_keeper_en_17_wd), |
| .d (hw2reg.mio_pad_attr[17].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[17].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_17_keeper_en_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].keeper_en.qe = mio_pad_attr_17_qe; |
| |
| // F[schmitt_en_17]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_schmitt_en_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_schmitt_en_17_wd), |
| .d (hw2reg.mio_pad_attr[17].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[17].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_17_schmitt_en_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].schmitt_en.qe = mio_pad_attr_17_qe; |
| |
| // F[od_en_17]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_17_od_en_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_od_en_17_wd), |
| .d (hw2reg.mio_pad_attr[17].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[17].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_17_od_en_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].od_en.qe = mio_pad_attr_17_qe; |
| |
| // F[slew_rate_17]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_17_slew_rate_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_slew_rate_17_wd), |
| .d (hw2reg.mio_pad_attr[17].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[17].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_17_slew_rate_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].slew_rate.qe = mio_pad_attr_17_qe; |
| |
| // F[drive_strength_17]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_17_drive_strength_17 ( |
| .re (mio_pad_attr_17_re), |
| .we (mio_pad_attr_17_gated_we), |
| .wd (mio_pad_attr_17_drive_strength_17_wd), |
| .d (hw2reg.mio_pad_attr[17].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_17_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[17].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_17_drive_strength_17_qs) |
| ); |
| assign reg2hw.mio_pad_attr[17].drive_strength.qe = mio_pad_attr_17_qe; |
| |
| |
| // Subregister 18 of Multireg mio_pad_attr |
| // R[mio_pad_attr_18]: V(True) |
| logic mio_pad_attr_18_qe; |
| logic [8:0] mio_pad_attr_18_flds_we; |
| assign mio_pad_attr_18_qe = &mio_pad_attr_18_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_18_gated_we; |
| assign mio_pad_attr_18_gated_we = mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs; |
| // F[invert_18]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_invert_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_invert_18_wd), |
| .d (hw2reg.mio_pad_attr[18].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[18].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_18_invert_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].invert.qe = mio_pad_attr_18_qe; |
| |
| // F[virtual_od_en_18]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_virtual_od_en_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_virtual_od_en_18_wd), |
| .d (hw2reg.mio_pad_attr[18].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[18].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_18_virtual_od_en_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].virtual_od_en.qe = mio_pad_attr_18_qe; |
| |
| // F[pull_en_18]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_pull_en_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_pull_en_18_wd), |
| .d (hw2reg.mio_pad_attr[18].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[18].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_18_pull_en_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].pull_en.qe = mio_pad_attr_18_qe; |
| |
| // F[pull_select_18]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_pull_select_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_pull_select_18_wd), |
| .d (hw2reg.mio_pad_attr[18].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[18].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_18_pull_select_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].pull_select.qe = mio_pad_attr_18_qe; |
| |
| // F[keeper_en_18]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_keeper_en_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_keeper_en_18_wd), |
| .d (hw2reg.mio_pad_attr[18].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[18].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_18_keeper_en_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].keeper_en.qe = mio_pad_attr_18_qe; |
| |
| // F[schmitt_en_18]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_schmitt_en_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_schmitt_en_18_wd), |
| .d (hw2reg.mio_pad_attr[18].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[18].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_18_schmitt_en_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].schmitt_en.qe = mio_pad_attr_18_qe; |
| |
| // F[od_en_18]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_18_od_en_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_od_en_18_wd), |
| .d (hw2reg.mio_pad_attr[18].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[18].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_18_od_en_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].od_en.qe = mio_pad_attr_18_qe; |
| |
| // F[slew_rate_18]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_18_slew_rate_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_slew_rate_18_wd), |
| .d (hw2reg.mio_pad_attr[18].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[18].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_18_slew_rate_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].slew_rate.qe = mio_pad_attr_18_qe; |
| |
| // F[drive_strength_18]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_18_drive_strength_18 ( |
| .re (mio_pad_attr_18_re), |
| .we (mio_pad_attr_18_gated_we), |
| .wd (mio_pad_attr_18_drive_strength_18_wd), |
| .d (hw2reg.mio_pad_attr[18].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_18_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[18].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_18_drive_strength_18_qs) |
| ); |
| assign reg2hw.mio_pad_attr[18].drive_strength.qe = mio_pad_attr_18_qe; |
| |
| |
| // Subregister 19 of Multireg mio_pad_attr |
| // R[mio_pad_attr_19]: V(True) |
| logic mio_pad_attr_19_qe; |
| logic [8:0] mio_pad_attr_19_flds_we; |
| assign mio_pad_attr_19_qe = &mio_pad_attr_19_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_19_gated_we; |
| assign mio_pad_attr_19_gated_we = mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs; |
| // F[invert_19]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_invert_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_invert_19_wd), |
| .d (hw2reg.mio_pad_attr[19].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[19].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_19_invert_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].invert.qe = mio_pad_attr_19_qe; |
| |
| // F[virtual_od_en_19]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_virtual_od_en_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_virtual_od_en_19_wd), |
| .d (hw2reg.mio_pad_attr[19].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[19].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_19_virtual_od_en_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].virtual_od_en.qe = mio_pad_attr_19_qe; |
| |
| // F[pull_en_19]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_pull_en_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_pull_en_19_wd), |
| .d (hw2reg.mio_pad_attr[19].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[19].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_19_pull_en_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].pull_en.qe = mio_pad_attr_19_qe; |
| |
| // F[pull_select_19]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_pull_select_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_pull_select_19_wd), |
| .d (hw2reg.mio_pad_attr[19].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[19].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_19_pull_select_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].pull_select.qe = mio_pad_attr_19_qe; |
| |
| // F[keeper_en_19]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_keeper_en_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_keeper_en_19_wd), |
| .d (hw2reg.mio_pad_attr[19].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[19].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_19_keeper_en_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].keeper_en.qe = mio_pad_attr_19_qe; |
| |
| // F[schmitt_en_19]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_schmitt_en_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_schmitt_en_19_wd), |
| .d (hw2reg.mio_pad_attr[19].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[19].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_19_schmitt_en_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].schmitt_en.qe = mio_pad_attr_19_qe; |
| |
| // F[od_en_19]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_19_od_en_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_od_en_19_wd), |
| .d (hw2reg.mio_pad_attr[19].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[19].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_19_od_en_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].od_en.qe = mio_pad_attr_19_qe; |
| |
| // F[slew_rate_19]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_19_slew_rate_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_slew_rate_19_wd), |
| .d (hw2reg.mio_pad_attr[19].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[19].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_19_slew_rate_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].slew_rate.qe = mio_pad_attr_19_qe; |
| |
| // F[drive_strength_19]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_19_drive_strength_19 ( |
| .re (mio_pad_attr_19_re), |
| .we (mio_pad_attr_19_gated_we), |
| .wd (mio_pad_attr_19_drive_strength_19_wd), |
| .d (hw2reg.mio_pad_attr[19].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_19_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[19].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_19_drive_strength_19_qs) |
| ); |
| assign reg2hw.mio_pad_attr[19].drive_strength.qe = mio_pad_attr_19_qe; |
| |
| |
| // Subregister 20 of Multireg mio_pad_attr |
| // R[mio_pad_attr_20]: V(True) |
| logic mio_pad_attr_20_qe; |
| logic [8:0] mio_pad_attr_20_flds_we; |
| assign mio_pad_attr_20_qe = &mio_pad_attr_20_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_20_gated_we; |
| assign mio_pad_attr_20_gated_we = mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs; |
| // F[invert_20]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_invert_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_invert_20_wd), |
| .d (hw2reg.mio_pad_attr[20].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[20].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_20_invert_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].invert.qe = mio_pad_attr_20_qe; |
| |
| // F[virtual_od_en_20]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_virtual_od_en_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_virtual_od_en_20_wd), |
| .d (hw2reg.mio_pad_attr[20].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[20].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_20_virtual_od_en_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].virtual_od_en.qe = mio_pad_attr_20_qe; |
| |
| // F[pull_en_20]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_pull_en_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_pull_en_20_wd), |
| .d (hw2reg.mio_pad_attr[20].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[20].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_20_pull_en_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].pull_en.qe = mio_pad_attr_20_qe; |
| |
| // F[pull_select_20]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_pull_select_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_pull_select_20_wd), |
| .d (hw2reg.mio_pad_attr[20].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[20].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_20_pull_select_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].pull_select.qe = mio_pad_attr_20_qe; |
| |
| // F[keeper_en_20]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_keeper_en_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_keeper_en_20_wd), |
| .d (hw2reg.mio_pad_attr[20].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[20].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_20_keeper_en_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].keeper_en.qe = mio_pad_attr_20_qe; |
| |
| // F[schmitt_en_20]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_schmitt_en_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_schmitt_en_20_wd), |
| .d (hw2reg.mio_pad_attr[20].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[20].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_20_schmitt_en_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].schmitt_en.qe = mio_pad_attr_20_qe; |
| |
| // F[od_en_20]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_20_od_en_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_od_en_20_wd), |
| .d (hw2reg.mio_pad_attr[20].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[20].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_20_od_en_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].od_en.qe = mio_pad_attr_20_qe; |
| |
| // F[slew_rate_20]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_20_slew_rate_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_slew_rate_20_wd), |
| .d (hw2reg.mio_pad_attr[20].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[20].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_20_slew_rate_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].slew_rate.qe = mio_pad_attr_20_qe; |
| |
| // F[drive_strength_20]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_20_drive_strength_20 ( |
| .re (mio_pad_attr_20_re), |
| .we (mio_pad_attr_20_gated_we), |
| .wd (mio_pad_attr_20_drive_strength_20_wd), |
| .d (hw2reg.mio_pad_attr[20].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_20_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[20].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_20_drive_strength_20_qs) |
| ); |
| assign reg2hw.mio_pad_attr[20].drive_strength.qe = mio_pad_attr_20_qe; |
| |
| |
| // Subregister 21 of Multireg mio_pad_attr |
| // R[mio_pad_attr_21]: V(True) |
| logic mio_pad_attr_21_qe; |
| logic [8:0] mio_pad_attr_21_flds_we; |
| assign mio_pad_attr_21_qe = &mio_pad_attr_21_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_21_gated_we; |
| assign mio_pad_attr_21_gated_we = mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs; |
| // F[invert_21]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_invert_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_invert_21_wd), |
| .d (hw2reg.mio_pad_attr[21].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[21].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_21_invert_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].invert.qe = mio_pad_attr_21_qe; |
| |
| // F[virtual_od_en_21]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_virtual_od_en_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_virtual_od_en_21_wd), |
| .d (hw2reg.mio_pad_attr[21].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[21].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_21_virtual_od_en_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].virtual_od_en.qe = mio_pad_attr_21_qe; |
| |
| // F[pull_en_21]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_pull_en_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_pull_en_21_wd), |
| .d (hw2reg.mio_pad_attr[21].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[21].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_21_pull_en_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].pull_en.qe = mio_pad_attr_21_qe; |
| |
| // F[pull_select_21]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_pull_select_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_pull_select_21_wd), |
| .d (hw2reg.mio_pad_attr[21].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[21].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_21_pull_select_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].pull_select.qe = mio_pad_attr_21_qe; |
| |
| // F[keeper_en_21]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_keeper_en_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_keeper_en_21_wd), |
| .d (hw2reg.mio_pad_attr[21].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[21].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_21_keeper_en_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].keeper_en.qe = mio_pad_attr_21_qe; |
| |
| // F[schmitt_en_21]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_schmitt_en_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_schmitt_en_21_wd), |
| .d (hw2reg.mio_pad_attr[21].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[21].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_21_schmitt_en_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].schmitt_en.qe = mio_pad_attr_21_qe; |
| |
| // F[od_en_21]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_21_od_en_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_od_en_21_wd), |
| .d (hw2reg.mio_pad_attr[21].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[21].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_21_od_en_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].od_en.qe = mio_pad_attr_21_qe; |
| |
| // F[slew_rate_21]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_21_slew_rate_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_slew_rate_21_wd), |
| .d (hw2reg.mio_pad_attr[21].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[21].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_21_slew_rate_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].slew_rate.qe = mio_pad_attr_21_qe; |
| |
| // F[drive_strength_21]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_21_drive_strength_21 ( |
| .re (mio_pad_attr_21_re), |
| .we (mio_pad_attr_21_gated_we), |
| .wd (mio_pad_attr_21_drive_strength_21_wd), |
| .d (hw2reg.mio_pad_attr[21].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_21_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[21].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_21_drive_strength_21_qs) |
| ); |
| assign reg2hw.mio_pad_attr[21].drive_strength.qe = mio_pad_attr_21_qe; |
| |
| |
| // Subregister 22 of Multireg mio_pad_attr |
| // R[mio_pad_attr_22]: V(True) |
| logic mio_pad_attr_22_qe; |
| logic [8:0] mio_pad_attr_22_flds_we; |
| assign mio_pad_attr_22_qe = &mio_pad_attr_22_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_22_gated_we; |
| assign mio_pad_attr_22_gated_we = mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs; |
| // F[invert_22]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_invert_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_invert_22_wd), |
| .d (hw2reg.mio_pad_attr[22].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[22].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_22_invert_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].invert.qe = mio_pad_attr_22_qe; |
| |
| // F[virtual_od_en_22]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_virtual_od_en_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_virtual_od_en_22_wd), |
| .d (hw2reg.mio_pad_attr[22].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[22].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_22_virtual_od_en_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].virtual_od_en.qe = mio_pad_attr_22_qe; |
| |
| // F[pull_en_22]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_pull_en_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_pull_en_22_wd), |
| .d (hw2reg.mio_pad_attr[22].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[22].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_22_pull_en_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].pull_en.qe = mio_pad_attr_22_qe; |
| |
| // F[pull_select_22]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_pull_select_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_pull_select_22_wd), |
| .d (hw2reg.mio_pad_attr[22].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[22].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_22_pull_select_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].pull_select.qe = mio_pad_attr_22_qe; |
| |
| // F[keeper_en_22]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_keeper_en_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_keeper_en_22_wd), |
| .d (hw2reg.mio_pad_attr[22].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[22].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_22_keeper_en_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].keeper_en.qe = mio_pad_attr_22_qe; |
| |
| // F[schmitt_en_22]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_schmitt_en_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_schmitt_en_22_wd), |
| .d (hw2reg.mio_pad_attr[22].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[22].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_22_schmitt_en_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].schmitt_en.qe = mio_pad_attr_22_qe; |
| |
| // F[od_en_22]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_22_od_en_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_od_en_22_wd), |
| .d (hw2reg.mio_pad_attr[22].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[22].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_22_od_en_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].od_en.qe = mio_pad_attr_22_qe; |
| |
| // F[slew_rate_22]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_22_slew_rate_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_slew_rate_22_wd), |
| .d (hw2reg.mio_pad_attr[22].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[22].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_22_slew_rate_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].slew_rate.qe = mio_pad_attr_22_qe; |
| |
| // F[drive_strength_22]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_22_drive_strength_22 ( |
| .re (mio_pad_attr_22_re), |
| .we (mio_pad_attr_22_gated_we), |
| .wd (mio_pad_attr_22_drive_strength_22_wd), |
| .d (hw2reg.mio_pad_attr[22].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_22_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[22].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_22_drive_strength_22_qs) |
| ); |
| assign reg2hw.mio_pad_attr[22].drive_strength.qe = mio_pad_attr_22_qe; |
| |
| |
| // Subregister 23 of Multireg mio_pad_attr |
| // R[mio_pad_attr_23]: V(True) |
| logic mio_pad_attr_23_qe; |
| logic [8:0] mio_pad_attr_23_flds_we; |
| assign mio_pad_attr_23_qe = &mio_pad_attr_23_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_23_gated_we; |
| assign mio_pad_attr_23_gated_we = mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs; |
| // F[invert_23]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_invert_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_invert_23_wd), |
| .d (hw2reg.mio_pad_attr[23].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[23].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_23_invert_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].invert.qe = mio_pad_attr_23_qe; |
| |
| // F[virtual_od_en_23]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_virtual_od_en_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_virtual_od_en_23_wd), |
| .d (hw2reg.mio_pad_attr[23].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[23].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_23_virtual_od_en_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].virtual_od_en.qe = mio_pad_attr_23_qe; |
| |
| // F[pull_en_23]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_pull_en_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_pull_en_23_wd), |
| .d (hw2reg.mio_pad_attr[23].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[23].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_23_pull_en_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].pull_en.qe = mio_pad_attr_23_qe; |
| |
| // F[pull_select_23]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_pull_select_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_pull_select_23_wd), |
| .d (hw2reg.mio_pad_attr[23].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[23].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_23_pull_select_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].pull_select.qe = mio_pad_attr_23_qe; |
| |
| // F[keeper_en_23]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_keeper_en_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_keeper_en_23_wd), |
| .d (hw2reg.mio_pad_attr[23].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[23].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_23_keeper_en_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].keeper_en.qe = mio_pad_attr_23_qe; |
| |
| // F[schmitt_en_23]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_schmitt_en_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_schmitt_en_23_wd), |
| .d (hw2reg.mio_pad_attr[23].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[23].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_23_schmitt_en_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].schmitt_en.qe = mio_pad_attr_23_qe; |
| |
| // F[od_en_23]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_23_od_en_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_od_en_23_wd), |
| .d (hw2reg.mio_pad_attr[23].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[23].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_23_od_en_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].od_en.qe = mio_pad_attr_23_qe; |
| |
| // F[slew_rate_23]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_23_slew_rate_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_slew_rate_23_wd), |
| .d (hw2reg.mio_pad_attr[23].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[23].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_23_slew_rate_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].slew_rate.qe = mio_pad_attr_23_qe; |
| |
| // F[drive_strength_23]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_23_drive_strength_23 ( |
| .re (mio_pad_attr_23_re), |
| .we (mio_pad_attr_23_gated_we), |
| .wd (mio_pad_attr_23_drive_strength_23_wd), |
| .d (hw2reg.mio_pad_attr[23].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_23_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[23].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_23_drive_strength_23_qs) |
| ); |
| assign reg2hw.mio_pad_attr[23].drive_strength.qe = mio_pad_attr_23_qe; |
| |
| |
| // Subregister 24 of Multireg mio_pad_attr |
| // R[mio_pad_attr_24]: V(True) |
| logic mio_pad_attr_24_qe; |
| logic [8:0] mio_pad_attr_24_flds_we; |
| assign mio_pad_attr_24_qe = &mio_pad_attr_24_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_24_gated_we; |
| assign mio_pad_attr_24_gated_we = mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs; |
| // F[invert_24]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_invert_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_invert_24_wd), |
| .d (hw2reg.mio_pad_attr[24].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[24].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_24_invert_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].invert.qe = mio_pad_attr_24_qe; |
| |
| // F[virtual_od_en_24]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_virtual_od_en_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_virtual_od_en_24_wd), |
| .d (hw2reg.mio_pad_attr[24].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[24].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_24_virtual_od_en_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].virtual_od_en.qe = mio_pad_attr_24_qe; |
| |
| // F[pull_en_24]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_pull_en_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_pull_en_24_wd), |
| .d (hw2reg.mio_pad_attr[24].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[24].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_24_pull_en_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].pull_en.qe = mio_pad_attr_24_qe; |
| |
| // F[pull_select_24]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_pull_select_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_pull_select_24_wd), |
| .d (hw2reg.mio_pad_attr[24].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[24].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_24_pull_select_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].pull_select.qe = mio_pad_attr_24_qe; |
| |
| // F[keeper_en_24]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_keeper_en_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_keeper_en_24_wd), |
| .d (hw2reg.mio_pad_attr[24].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[24].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_24_keeper_en_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].keeper_en.qe = mio_pad_attr_24_qe; |
| |
| // F[schmitt_en_24]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_schmitt_en_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_schmitt_en_24_wd), |
| .d (hw2reg.mio_pad_attr[24].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[24].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_24_schmitt_en_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].schmitt_en.qe = mio_pad_attr_24_qe; |
| |
| // F[od_en_24]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_24_od_en_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_od_en_24_wd), |
| .d (hw2reg.mio_pad_attr[24].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[24].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_24_od_en_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].od_en.qe = mio_pad_attr_24_qe; |
| |
| // F[slew_rate_24]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_24_slew_rate_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_slew_rate_24_wd), |
| .d (hw2reg.mio_pad_attr[24].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[24].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_24_slew_rate_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].slew_rate.qe = mio_pad_attr_24_qe; |
| |
| // F[drive_strength_24]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_24_drive_strength_24 ( |
| .re (mio_pad_attr_24_re), |
| .we (mio_pad_attr_24_gated_we), |
| .wd (mio_pad_attr_24_drive_strength_24_wd), |
| .d (hw2reg.mio_pad_attr[24].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_24_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[24].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_24_drive_strength_24_qs) |
| ); |
| assign reg2hw.mio_pad_attr[24].drive_strength.qe = mio_pad_attr_24_qe; |
| |
| |
| // Subregister 25 of Multireg mio_pad_attr |
| // R[mio_pad_attr_25]: V(True) |
| logic mio_pad_attr_25_qe; |
| logic [8:0] mio_pad_attr_25_flds_we; |
| assign mio_pad_attr_25_qe = &mio_pad_attr_25_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_25_gated_we; |
| assign mio_pad_attr_25_gated_we = mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs; |
| // F[invert_25]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_invert_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_invert_25_wd), |
| .d (hw2reg.mio_pad_attr[25].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[25].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_25_invert_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].invert.qe = mio_pad_attr_25_qe; |
| |
| // F[virtual_od_en_25]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_virtual_od_en_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_virtual_od_en_25_wd), |
| .d (hw2reg.mio_pad_attr[25].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[25].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_25_virtual_od_en_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].virtual_od_en.qe = mio_pad_attr_25_qe; |
| |
| // F[pull_en_25]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_pull_en_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_pull_en_25_wd), |
| .d (hw2reg.mio_pad_attr[25].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[25].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_25_pull_en_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].pull_en.qe = mio_pad_attr_25_qe; |
| |
| // F[pull_select_25]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_pull_select_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_pull_select_25_wd), |
| .d (hw2reg.mio_pad_attr[25].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[25].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_25_pull_select_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].pull_select.qe = mio_pad_attr_25_qe; |
| |
| // F[keeper_en_25]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_keeper_en_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_keeper_en_25_wd), |
| .d (hw2reg.mio_pad_attr[25].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[25].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_25_keeper_en_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].keeper_en.qe = mio_pad_attr_25_qe; |
| |
| // F[schmitt_en_25]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_schmitt_en_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_schmitt_en_25_wd), |
| .d (hw2reg.mio_pad_attr[25].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[25].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_25_schmitt_en_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].schmitt_en.qe = mio_pad_attr_25_qe; |
| |
| // F[od_en_25]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_25_od_en_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_od_en_25_wd), |
| .d (hw2reg.mio_pad_attr[25].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[25].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_25_od_en_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].od_en.qe = mio_pad_attr_25_qe; |
| |
| // F[slew_rate_25]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_25_slew_rate_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_slew_rate_25_wd), |
| .d (hw2reg.mio_pad_attr[25].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[25].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_25_slew_rate_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].slew_rate.qe = mio_pad_attr_25_qe; |
| |
| // F[drive_strength_25]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_25_drive_strength_25 ( |
| .re (mio_pad_attr_25_re), |
| .we (mio_pad_attr_25_gated_we), |
| .wd (mio_pad_attr_25_drive_strength_25_wd), |
| .d (hw2reg.mio_pad_attr[25].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_25_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[25].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_25_drive_strength_25_qs) |
| ); |
| assign reg2hw.mio_pad_attr[25].drive_strength.qe = mio_pad_attr_25_qe; |
| |
| |
| // Subregister 26 of Multireg mio_pad_attr |
| // R[mio_pad_attr_26]: V(True) |
| logic mio_pad_attr_26_qe; |
| logic [8:0] mio_pad_attr_26_flds_we; |
| assign mio_pad_attr_26_qe = &mio_pad_attr_26_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_26_gated_we; |
| assign mio_pad_attr_26_gated_we = mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs; |
| // F[invert_26]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_invert_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_invert_26_wd), |
| .d (hw2reg.mio_pad_attr[26].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[26].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_26_invert_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].invert.qe = mio_pad_attr_26_qe; |
| |
| // F[virtual_od_en_26]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_virtual_od_en_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_virtual_od_en_26_wd), |
| .d (hw2reg.mio_pad_attr[26].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[26].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_26_virtual_od_en_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].virtual_od_en.qe = mio_pad_attr_26_qe; |
| |
| // F[pull_en_26]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_pull_en_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_pull_en_26_wd), |
| .d (hw2reg.mio_pad_attr[26].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[26].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_26_pull_en_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].pull_en.qe = mio_pad_attr_26_qe; |
| |
| // F[pull_select_26]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_pull_select_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_pull_select_26_wd), |
| .d (hw2reg.mio_pad_attr[26].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[26].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_26_pull_select_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].pull_select.qe = mio_pad_attr_26_qe; |
| |
| // F[keeper_en_26]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_keeper_en_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_keeper_en_26_wd), |
| .d (hw2reg.mio_pad_attr[26].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[26].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_26_keeper_en_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].keeper_en.qe = mio_pad_attr_26_qe; |
| |
| // F[schmitt_en_26]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_schmitt_en_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_schmitt_en_26_wd), |
| .d (hw2reg.mio_pad_attr[26].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[26].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_26_schmitt_en_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].schmitt_en.qe = mio_pad_attr_26_qe; |
| |
| // F[od_en_26]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_26_od_en_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_od_en_26_wd), |
| .d (hw2reg.mio_pad_attr[26].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[26].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_26_od_en_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].od_en.qe = mio_pad_attr_26_qe; |
| |
| // F[slew_rate_26]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_26_slew_rate_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_slew_rate_26_wd), |
| .d (hw2reg.mio_pad_attr[26].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[26].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_26_slew_rate_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].slew_rate.qe = mio_pad_attr_26_qe; |
| |
| // F[drive_strength_26]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_26_drive_strength_26 ( |
| .re (mio_pad_attr_26_re), |
| .we (mio_pad_attr_26_gated_we), |
| .wd (mio_pad_attr_26_drive_strength_26_wd), |
| .d (hw2reg.mio_pad_attr[26].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_26_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[26].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_26_drive_strength_26_qs) |
| ); |
| assign reg2hw.mio_pad_attr[26].drive_strength.qe = mio_pad_attr_26_qe; |
| |
| |
| // Subregister 27 of Multireg mio_pad_attr |
| // R[mio_pad_attr_27]: V(True) |
| logic mio_pad_attr_27_qe; |
| logic [8:0] mio_pad_attr_27_flds_we; |
| assign mio_pad_attr_27_qe = &mio_pad_attr_27_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_27_gated_we; |
| assign mio_pad_attr_27_gated_we = mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs; |
| // F[invert_27]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_invert_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_invert_27_wd), |
| .d (hw2reg.mio_pad_attr[27].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[27].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_27_invert_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].invert.qe = mio_pad_attr_27_qe; |
| |
| // F[virtual_od_en_27]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_virtual_od_en_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_virtual_od_en_27_wd), |
| .d (hw2reg.mio_pad_attr[27].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[27].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_27_virtual_od_en_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].virtual_od_en.qe = mio_pad_attr_27_qe; |
| |
| // F[pull_en_27]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_pull_en_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_pull_en_27_wd), |
| .d (hw2reg.mio_pad_attr[27].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[27].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_27_pull_en_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].pull_en.qe = mio_pad_attr_27_qe; |
| |
| // F[pull_select_27]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_pull_select_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_pull_select_27_wd), |
| .d (hw2reg.mio_pad_attr[27].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[27].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_27_pull_select_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].pull_select.qe = mio_pad_attr_27_qe; |
| |
| // F[keeper_en_27]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_keeper_en_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_keeper_en_27_wd), |
| .d (hw2reg.mio_pad_attr[27].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[27].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_27_keeper_en_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].keeper_en.qe = mio_pad_attr_27_qe; |
| |
| // F[schmitt_en_27]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_schmitt_en_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_schmitt_en_27_wd), |
| .d (hw2reg.mio_pad_attr[27].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[27].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_27_schmitt_en_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].schmitt_en.qe = mio_pad_attr_27_qe; |
| |
| // F[od_en_27]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_27_od_en_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_od_en_27_wd), |
| .d (hw2reg.mio_pad_attr[27].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[27].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_27_od_en_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].od_en.qe = mio_pad_attr_27_qe; |
| |
| // F[slew_rate_27]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_27_slew_rate_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_slew_rate_27_wd), |
| .d (hw2reg.mio_pad_attr[27].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[27].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_27_slew_rate_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].slew_rate.qe = mio_pad_attr_27_qe; |
| |
| // F[drive_strength_27]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_27_drive_strength_27 ( |
| .re (mio_pad_attr_27_re), |
| .we (mio_pad_attr_27_gated_we), |
| .wd (mio_pad_attr_27_drive_strength_27_wd), |
| .d (hw2reg.mio_pad_attr[27].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_27_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[27].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_27_drive_strength_27_qs) |
| ); |
| assign reg2hw.mio_pad_attr[27].drive_strength.qe = mio_pad_attr_27_qe; |
| |
| |
| // Subregister 28 of Multireg mio_pad_attr |
| // R[mio_pad_attr_28]: V(True) |
| logic mio_pad_attr_28_qe; |
| logic [8:0] mio_pad_attr_28_flds_we; |
| assign mio_pad_attr_28_qe = &mio_pad_attr_28_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_28_gated_we; |
| assign mio_pad_attr_28_gated_we = mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs; |
| // F[invert_28]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_invert_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_invert_28_wd), |
| .d (hw2reg.mio_pad_attr[28].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[28].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_28_invert_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].invert.qe = mio_pad_attr_28_qe; |
| |
| // F[virtual_od_en_28]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_virtual_od_en_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_virtual_od_en_28_wd), |
| .d (hw2reg.mio_pad_attr[28].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[28].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_28_virtual_od_en_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].virtual_od_en.qe = mio_pad_attr_28_qe; |
| |
| // F[pull_en_28]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_pull_en_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_pull_en_28_wd), |
| .d (hw2reg.mio_pad_attr[28].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[28].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_28_pull_en_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].pull_en.qe = mio_pad_attr_28_qe; |
| |
| // F[pull_select_28]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_pull_select_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_pull_select_28_wd), |
| .d (hw2reg.mio_pad_attr[28].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[28].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_28_pull_select_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].pull_select.qe = mio_pad_attr_28_qe; |
| |
| // F[keeper_en_28]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_keeper_en_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_keeper_en_28_wd), |
| .d (hw2reg.mio_pad_attr[28].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[28].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_28_keeper_en_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].keeper_en.qe = mio_pad_attr_28_qe; |
| |
| // F[schmitt_en_28]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_schmitt_en_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_schmitt_en_28_wd), |
| .d (hw2reg.mio_pad_attr[28].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[28].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_28_schmitt_en_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].schmitt_en.qe = mio_pad_attr_28_qe; |
| |
| // F[od_en_28]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_28_od_en_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_od_en_28_wd), |
| .d (hw2reg.mio_pad_attr[28].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[28].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_28_od_en_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].od_en.qe = mio_pad_attr_28_qe; |
| |
| // F[slew_rate_28]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_28_slew_rate_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_slew_rate_28_wd), |
| .d (hw2reg.mio_pad_attr[28].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[28].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_28_slew_rate_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].slew_rate.qe = mio_pad_attr_28_qe; |
| |
| // F[drive_strength_28]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_28_drive_strength_28 ( |
| .re (mio_pad_attr_28_re), |
| .we (mio_pad_attr_28_gated_we), |
| .wd (mio_pad_attr_28_drive_strength_28_wd), |
| .d (hw2reg.mio_pad_attr[28].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_28_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[28].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_28_drive_strength_28_qs) |
| ); |
| assign reg2hw.mio_pad_attr[28].drive_strength.qe = mio_pad_attr_28_qe; |
| |
| |
| // Subregister 29 of Multireg mio_pad_attr |
| // R[mio_pad_attr_29]: V(True) |
| logic mio_pad_attr_29_qe; |
| logic [8:0] mio_pad_attr_29_flds_we; |
| assign mio_pad_attr_29_qe = &mio_pad_attr_29_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_29_gated_we; |
| assign mio_pad_attr_29_gated_we = mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs; |
| // F[invert_29]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_invert_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_invert_29_wd), |
| .d (hw2reg.mio_pad_attr[29].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[29].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_29_invert_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].invert.qe = mio_pad_attr_29_qe; |
| |
| // F[virtual_od_en_29]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_virtual_od_en_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_virtual_od_en_29_wd), |
| .d (hw2reg.mio_pad_attr[29].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[29].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_29_virtual_od_en_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].virtual_od_en.qe = mio_pad_attr_29_qe; |
| |
| // F[pull_en_29]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_pull_en_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_pull_en_29_wd), |
| .d (hw2reg.mio_pad_attr[29].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[29].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_29_pull_en_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].pull_en.qe = mio_pad_attr_29_qe; |
| |
| // F[pull_select_29]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_pull_select_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_pull_select_29_wd), |
| .d (hw2reg.mio_pad_attr[29].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[29].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_29_pull_select_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].pull_select.qe = mio_pad_attr_29_qe; |
| |
| // F[keeper_en_29]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_keeper_en_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_keeper_en_29_wd), |
| .d (hw2reg.mio_pad_attr[29].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[29].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_29_keeper_en_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].keeper_en.qe = mio_pad_attr_29_qe; |
| |
| // F[schmitt_en_29]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_schmitt_en_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_schmitt_en_29_wd), |
| .d (hw2reg.mio_pad_attr[29].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[29].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_29_schmitt_en_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].schmitt_en.qe = mio_pad_attr_29_qe; |
| |
| // F[od_en_29]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_29_od_en_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_od_en_29_wd), |
| .d (hw2reg.mio_pad_attr[29].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[29].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_29_od_en_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].od_en.qe = mio_pad_attr_29_qe; |
| |
| // F[slew_rate_29]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_29_slew_rate_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_slew_rate_29_wd), |
| .d (hw2reg.mio_pad_attr[29].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[29].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_29_slew_rate_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].slew_rate.qe = mio_pad_attr_29_qe; |
| |
| // F[drive_strength_29]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_29_drive_strength_29 ( |
| .re (mio_pad_attr_29_re), |
| .we (mio_pad_attr_29_gated_we), |
| .wd (mio_pad_attr_29_drive_strength_29_wd), |
| .d (hw2reg.mio_pad_attr[29].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_29_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[29].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_29_drive_strength_29_qs) |
| ); |
| assign reg2hw.mio_pad_attr[29].drive_strength.qe = mio_pad_attr_29_qe; |
| |
| |
| // Subregister 30 of Multireg mio_pad_attr |
| // R[mio_pad_attr_30]: V(True) |
| logic mio_pad_attr_30_qe; |
| logic [8:0] mio_pad_attr_30_flds_we; |
| assign mio_pad_attr_30_qe = &mio_pad_attr_30_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_30_gated_we; |
| assign mio_pad_attr_30_gated_we = mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs; |
| // F[invert_30]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_invert_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_invert_30_wd), |
| .d (hw2reg.mio_pad_attr[30].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[30].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_30_invert_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].invert.qe = mio_pad_attr_30_qe; |
| |
| // F[virtual_od_en_30]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_virtual_od_en_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_virtual_od_en_30_wd), |
| .d (hw2reg.mio_pad_attr[30].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[30].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_30_virtual_od_en_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].virtual_od_en.qe = mio_pad_attr_30_qe; |
| |
| // F[pull_en_30]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_pull_en_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_pull_en_30_wd), |
| .d (hw2reg.mio_pad_attr[30].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[30].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_30_pull_en_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].pull_en.qe = mio_pad_attr_30_qe; |
| |
| // F[pull_select_30]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_pull_select_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_pull_select_30_wd), |
| .d (hw2reg.mio_pad_attr[30].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[30].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_30_pull_select_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].pull_select.qe = mio_pad_attr_30_qe; |
| |
| // F[keeper_en_30]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_keeper_en_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_keeper_en_30_wd), |
| .d (hw2reg.mio_pad_attr[30].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[30].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_30_keeper_en_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].keeper_en.qe = mio_pad_attr_30_qe; |
| |
| // F[schmitt_en_30]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_schmitt_en_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_schmitt_en_30_wd), |
| .d (hw2reg.mio_pad_attr[30].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[30].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_30_schmitt_en_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].schmitt_en.qe = mio_pad_attr_30_qe; |
| |
| // F[od_en_30]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_30_od_en_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_od_en_30_wd), |
| .d (hw2reg.mio_pad_attr[30].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[30].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_30_od_en_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].od_en.qe = mio_pad_attr_30_qe; |
| |
| // F[slew_rate_30]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_30_slew_rate_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_slew_rate_30_wd), |
| .d (hw2reg.mio_pad_attr[30].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[30].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_30_slew_rate_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].slew_rate.qe = mio_pad_attr_30_qe; |
| |
| // F[drive_strength_30]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_30_drive_strength_30 ( |
| .re (mio_pad_attr_30_re), |
| .we (mio_pad_attr_30_gated_we), |
| .wd (mio_pad_attr_30_drive_strength_30_wd), |
| .d (hw2reg.mio_pad_attr[30].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_30_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[30].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_30_drive_strength_30_qs) |
| ); |
| assign reg2hw.mio_pad_attr[30].drive_strength.qe = mio_pad_attr_30_qe; |
| |
| |
| // Subregister 31 of Multireg mio_pad_attr |
| // R[mio_pad_attr_31]: V(True) |
| logic mio_pad_attr_31_qe; |
| logic [8:0] mio_pad_attr_31_flds_we; |
| assign mio_pad_attr_31_qe = &mio_pad_attr_31_flds_we; |
| // Create REGWEN-gated WE signal |
| logic mio_pad_attr_31_gated_we; |
| assign mio_pad_attr_31_gated_we = mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs; |
| // F[invert_31]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_invert_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_invert_31_wd), |
| .d (hw2reg.mio_pad_attr[31].invert.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[0]), |
| .q (reg2hw.mio_pad_attr[31].invert.q), |
| .ds (), |
| .qs (mio_pad_attr_31_invert_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].invert.qe = mio_pad_attr_31_qe; |
| |
| // F[virtual_od_en_31]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_virtual_od_en_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_virtual_od_en_31_wd), |
| .d (hw2reg.mio_pad_attr[31].virtual_od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[1]), |
| .q (reg2hw.mio_pad_attr[31].virtual_od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_31_virtual_od_en_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].virtual_od_en.qe = mio_pad_attr_31_qe; |
| |
| // F[pull_en_31]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_pull_en_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_pull_en_31_wd), |
| .d (hw2reg.mio_pad_attr[31].pull_en.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[2]), |
| .q (reg2hw.mio_pad_attr[31].pull_en.q), |
| .ds (), |
| .qs (mio_pad_attr_31_pull_en_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].pull_en.qe = mio_pad_attr_31_qe; |
| |
| // F[pull_select_31]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_pull_select_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_pull_select_31_wd), |
| .d (hw2reg.mio_pad_attr[31].pull_select.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[3]), |
| .q (reg2hw.mio_pad_attr[31].pull_select.q), |
| .ds (), |
| .qs (mio_pad_attr_31_pull_select_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].pull_select.qe = mio_pad_attr_31_qe; |
| |
| // F[keeper_en_31]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_keeper_en_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_keeper_en_31_wd), |
| .d (hw2reg.mio_pad_attr[31].keeper_en.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[4]), |
| .q (reg2hw.mio_pad_attr[31].keeper_en.q), |
| .ds (), |
| .qs (mio_pad_attr_31_keeper_en_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].keeper_en.qe = mio_pad_attr_31_qe; |
| |
| // F[schmitt_en_31]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_schmitt_en_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_schmitt_en_31_wd), |
| .d (hw2reg.mio_pad_attr[31].schmitt_en.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[5]), |
| .q (reg2hw.mio_pad_attr[31].schmitt_en.q), |
| .ds (), |
| .qs (mio_pad_attr_31_schmitt_en_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].schmitt_en.qe = mio_pad_attr_31_qe; |
| |
| // F[od_en_31]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_mio_pad_attr_31_od_en_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_od_en_31_wd), |
| .d (hw2reg.mio_pad_attr[31].od_en.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[6]), |
| .q (reg2hw.mio_pad_attr[31].od_en.q), |
| .ds (), |
| .qs (mio_pad_attr_31_od_en_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].od_en.qe = mio_pad_attr_31_qe; |
| |
| // F[slew_rate_31]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_mio_pad_attr_31_slew_rate_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_slew_rate_31_wd), |
| .d (hw2reg.mio_pad_attr[31].slew_rate.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[7]), |
| .q (reg2hw.mio_pad_attr[31].slew_rate.q), |
| .ds (), |
| .qs (mio_pad_attr_31_slew_rate_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].slew_rate.qe = mio_pad_attr_31_qe; |
| |
| // F[drive_strength_31]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_mio_pad_attr_31_drive_strength_31 ( |
| .re (mio_pad_attr_31_re), |
| .we (mio_pad_attr_31_gated_we), |
| .wd (mio_pad_attr_31_drive_strength_31_wd), |
| .d (hw2reg.mio_pad_attr[31].drive_strength.d), |
| .qre (), |
| .qe (mio_pad_attr_31_flds_we[8]), |
| .q (reg2hw.mio_pad_attr[31].drive_strength.q), |
| .ds (), |
| .qs (mio_pad_attr_31_drive_strength_31_qs) |
| ); |
| assign reg2hw.mio_pad_attr[31].drive_strength.qe = mio_pad_attr_31_qe; |
| |
| |
| // Subregister 0 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_0_we), |
| .wd (dio_pad_attr_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_1_we), |
| .wd (dio_pad_attr_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_2_we), |
| .wd (dio_pad_attr_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_3_we), |
| .wd (dio_pad_attr_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_4_we), |
| .wd (dio_pad_attr_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_5_we), |
| .wd (dio_pad_attr_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_6_we), |
| .wd (dio_pad_attr_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_7_we), |
| .wd (dio_pad_attr_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_8]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_8_we), |
| .wd (dio_pad_attr_regwen_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_9]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_9_we), |
| .wd (dio_pad_attr_regwen_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_10]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_10_we), |
| .wd (dio_pad_attr_regwen_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_11]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_11_we), |
| .wd (dio_pad_attr_regwen_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_12]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_12_we), |
| .wd (dio_pad_attr_regwen_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_13]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_13_we), |
| .wd (dio_pad_attr_regwen_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_14]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_14_we), |
| .wd (dio_pad_attr_regwen_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg dio_pad_attr_regwen |
| // R[dio_pad_attr_regwen_15]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_attr_regwen_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_attr_regwen_15_we), |
| .wd (dio_pad_attr_regwen_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_attr_regwen_15_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg dio_pad_attr |
| // R[dio_pad_attr_0]: V(True) |
| logic dio_pad_attr_0_qe; |
| logic [8:0] dio_pad_attr_0_flds_we; |
| assign dio_pad_attr_0_qe = &dio_pad_attr_0_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_0_gated_we; |
| assign dio_pad_attr_0_gated_we = dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs; |
| // F[invert_0]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_invert_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_invert_0_wd), |
| .d (hw2reg.dio_pad_attr[0].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[0].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_0_invert_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].invert.qe = dio_pad_attr_0_qe; |
| |
| // F[virtual_od_en_0]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_virtual_od_en_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_virtual_od_en_0_wd), |
| .d (hw2reg.dio_pad_attr[0].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[0].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_0_virtual_od_en_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].virtual_od_en.qe = dio_pad_attr_0_qe; |
| |
| // F[pull_en_0]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_pull_en_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_pull_en_0_wd), |
| .d (hw2reg.dio_pad_attr[0].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[0].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_0_pull_en_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].pull_en.qe = dio_pad_attr_0_qe; |
| |
| // F[pull_select_0]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_pull_select_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_pull_select_0_wd), |
| .d (hw2reg.dio_pad_attr[0].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[0].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_0_pull_select_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].pull_select.qe = dio_pad_attr_0_qe; |
| |
| // F[keeper_en_0]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_keeper_en_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_keeper_en_0_wd), |
| .d (hw2reg.dio_pad_attr[0].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[0].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_0_keeper_en_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].keeper_en.qe = dio_pad_attr_0_qe; |
| |
| // F[schmitt_en_0]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_schmitt_en_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_schmitt_en_0_wd), |
| .d (hw2reg.dio_pad_attr[0].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[0].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_0_schmitt_en_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].schmitt_en.qe = dio_pad_attr_0_qe; |
| |
| // F[od_en_0]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_0_od_en_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_od_en_0_wd), |
| .d (hw2reg.dio_pad_attr[0].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[0].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_0_od_en_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].od_en.qe = dio_pad_attr_0_qe; |
| |
| // F[slew_rate_0]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_0_slew_rate_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_slew_rate_0_wd), |
| .d (hw2reg.dio_pad_attr[0].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[0].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_0_slew_rate_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].slew_rate.qe = dio_pad_attr_0_qe; |
| |
| // F[drive_strength_0]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_0_drive_strength_0 ( |
| .re (dio_pad_attr_0_re), |
| .we (dio_pad_attr_0_gated_we), |
| .wd (dio_pad_attr_0_drive_strength_0_wd), |
| .d (hw2reg.dio_pad_attr[0].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_0_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[0].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_0_drive_strength_0_qs) |
| ); |
| assign reg2hw.dio_pad_attr[0].drive_strength.qe = dio_pad_attr_0_qe; |
| |
| |
| // Subregister 1 of Multireg dio_pad_attr |
| // R[dio_pad_attr_1]: V(True) |
| logic dio_pad_attr_1_qe; |
| logic [8:0] dio_pad_attr_1_flds_we; |
| assign dio_pad_attr_1_qe = &dio_pad_attr_1_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_1_gated_we; |
| assign dio_pad_attr_1_gated_we = dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs; |
| // F[invert_1]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_invert_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_invert_1_wd), |
| .d (hw2reg.dio_pad_attr[1].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[1].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_1_invert_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].invert.qe = dio_pad_attr_1_qe; |
| |
| // F[virtual_od_en_1]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_virtual_od_en_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_virtual_od_en_1_wd), |
| .d (hw2reg.dio_pad_attr[1].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[1].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_1_virtual_od_en_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].virtual_od_en.qe = dio_pad_attr_1_qe; |
| |
| // F[pull_en_1]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_pull_en_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_pull_en_1_wd), |
| .d (hw2reg.dio_pad_attr[1].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[1].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_1_pull_en_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].pull_en.qe = dio_pad_attr_1_qe; |
| |
| // F[pull_select_1]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_pull_select_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_pull_select_1_wd), |
| .d (hw2reg.dio_pad_attr[1].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[1].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_1_pull_select_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].pull_select.qe = dio_pad_attr_1_qe; |
| |
| // F[keeper_en_1]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_keeper_en_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_keeper_en_1_wd), |
| .d (hw2reg.dio_pad_attr[1].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[1].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_1_keeper_en_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].keeper_en.qe = dio_pad_attr_1_qe; |
| |
| // F[schmitt_en_1]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_schmitt_en_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_schmitt_en_1_wd), |
| .d (hw2reg.dio_pad_attr[1].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[1].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_1_schmitt_en_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].schmitt_en.qe = dio_pad_attr_1_qe; |
| |
| // F[od_en_1]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_1_od_en_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_od_en_1_wd), |
| .d (hw2reg.dio_pad_attr[1].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[1].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_1_od_en_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].od_en.qe = dio_pad_attr_1_qe; |
| |
| // F[slew_rate_1]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_1_slew_rate_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_slew_rate_1_wd), |
| .d (hw2reg.dio_pad_attr[1].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[1].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_1_slew_rate_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].slew_rate.qe = dio_pad_attr_1_qe; |
| |
| // F[drive_strength_1]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_1_drive_strength_1 ( |
| .re (dio_pad_attr_1_re), |
| .we (dio_pad_attr_1_gated_we), |
| .wd (dio_pad_attr_1_drive_strength_1_wd), |
| .d (hw2reg.dio_pad_attr[1].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_1_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[1].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_1_drive_strength_1_qs) |
| ); |
| assign reg2hw.dio_pad_attr[1].drive_strength.qe = dio_pad_attr_1_qe; |
| |
| |
| // Subregister 2 of Multireg dio_pad_attr |
| // R[dio_pad_attr_2]: V(True) |
| logic dio_pad_attr_2_qe; |
| logic [8:0] dio_pad_attr_2_flds_we; |
| assign dio_pad_attr_2_qe = &dio_pad_attr_2_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_2_gated_we; |
| assign dio_pad_attr_2_gated_we = dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs; |
| // F[invert_2]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_invert_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_invert_2_wd), |
| .d (hw2reg.dio_pad_attr[2].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[2].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_2_invert_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].invert.qe = dio_pad_attr_2_qe; |
| |
| // F[virtual_od_en_2]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_virtual_od_en_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_virtual_od_en_2_wd), |
| .d (hw2reg.dio_pad_attr[2].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[2].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_2_virtual_od_en_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].virtual_od_en.qe = dio_pad_attr_2_qe; |
| |
| // F[pull_en_2]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_pull_en_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_pull_en_2_wd), |
| .d (hw2reg.dio_pad_attr[2].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[2].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_2_pull_en_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].pull_en.qe = dio_pad_attr_2_qe; |
| |
| // F[pull_select_2]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_pull_select_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_pull_select_2_wd), |
| .d (hw2reg.dio_pad_attr[2].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[2].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_2_pull_select_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].pull_select.qe = dio_pad_attr_2_qe; |
| |
| // F[keeper_en_2]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_keeper_en_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_keeper_en_2_wd), |
| .d (hw2reg.dio_pad_attr[2].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[2].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_2_keeper_en_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].keeper_en.qe = dio_pad_attr_2_qe; |
| |
| // F[schmitt_en_2]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_schmitt_en_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_schmitt_en_2_wd), |
| .d (hw2reg.dio_pad_attr[2].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[2].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_2_schmitt_en_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].schmitt_en.qe = dio_pad_attr_2_qe; |
| |
| // F[od_en_2]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_2_od_en_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_od_en_2_wd), |
| .d (hw2reg.dio_pad_attr[2].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[2].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_2_od_en_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].od_en.qe = dio_pad_attr_2_qe; |
| |
| // F[slew_rate_2]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_2_slew_rate_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_slew_rate_2_wd), |
| .d (hw2reg.dio_pad_attr[2].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[2].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_2_slew_rate_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].slew_rate.qe = dio_pad_attr_2_qe; |
| |
| // F[drive_strength_2]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_2_drive_strength_2 ( |
| .re (dio_pad_attr_2_re), |
| .we (dio_pad_attr_2_gated_we), |
| .wd (dio_pad_attr_2_drive_strength_2_wd), |
| .d (hw2reg.dio_pad_attr[2].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_2_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[2].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_2_drive_strength_2_qs) |
| ); |
| assign reg2hw.dio_pad_attr[2].drive_strength.qe = dio_pad_attr_2_qe; |
| |
| |
| // Subregister 3 of Multireg dio_pad_attr |
| // R[dio_pad_attr_3]: V(True) |
| logic dio_pad_attr_3_qe; |
| logic [8:0] dio_pad_attr_3_flds_we; |
| assign dio_pad_attr_3_qe = &dio_pad_attr_3_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_3_gated_we; |
| assign dio_pad_attr_3_gated_we = dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs; |
| // F[invert_3]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_invert_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_invert_3_wd), |
| .d (hw2reg.dio_pad_attr[3].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[3].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_3_invert_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].invert.qe = dio_pad_attr_3_qe; |
| |
| // F[virtual_od_en_3]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_virtual_od_en_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_virtual_od_en_3_wd), |
| .d (hw2reg.dio_pad_attr[3].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[3].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_3_virtual_od_en_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].virtual_od_en.qe = dio_pad_attr_3_qe; |
| |
| // F[pull_en_3]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_pull_en_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_pull_en_3_wd), |
| .d (hw2reg.dio_pad_attr[3].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[3].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_3_pull_en_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].pull_en.qe = dio_pad_attr_3_qe; |
| |
| // F[pull_select_3]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_pull_select_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_pull_select_3_wd), |
| .d (hw2reg.dio_pad_attr[3].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[3].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_3_pull_select_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].pull_select.qe = dio_pad_attr_3_qe; |
| |
| // F[keeper_en_3]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_keeper_en_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_keeper_en_3_wd), |
| .d (hw2reg.dio_pad_attr[3].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[3].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_3_keeper_en_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].keeper_en.qe = dio_pad_attr_3_qe; |
| |
| // F[schmitt_en_3]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_schmitt_en_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_schmitt_en_3_wd), |
| .d (hw2reg.dio_pad_attr[3].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[3].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_3_schmitt_en_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].schmitt_en.qe = dio_pad_attr_3_qe; |
| |
| // F[od_en_3]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_3_od_en_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_od_en_3_wd), |
| .d (hw2reg.dio_pad_attr[3].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[3].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_3_od_en_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].od_en.qe = dio_pad_attr_3_qe; |
| |
| // F[slew_rate_3]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_3_slew_rate_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_slew_rate_3_wd), |
| .d (hw2reg.dio_pad_attr[3].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[3].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_3_slew_rate_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].slew_rate.qe = dio_pad_attr_3_qe; |
| |
| // F[drive_strength_3]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_3_drive_strength_3 ( |
| .re (dio_pad_attr_3_re), |
| .we (dio_pad_attr_3_gated_we), |
| .wd (dio_pad_attr_3_drive_strength_3_wd), |
| .d (hw2reg.dio_pad_attr[3].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_3_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[3].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_3_drive_strength_3_qs) |
| ); |
| assign reg2hw.dio_pad_attr[3].drive_strength.qe = dio_pad_attr_3_qe; |
| |
| |
| // Subregister 4 of Multireg dio_pad_attr |
| // R[dio_pad_attr_4]: V(True) |
| logic dio_pad_attr_4_qe; |
| logic [8:0] dio_pad_attr_4_flds_we; |
| assign dio_pad_attr_4_qe = &dio_pad_attr_4_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_4_gated_we; |
| assign dio_pad_attr_4_gated_we = dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs; |
| // F[invert_4]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_invert_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_invert_4_wd), |
| .d (hw2reg.dio_pad_attr[4].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[4].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_4_invert_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].invert.qe = dio_pad_attr_4_qe; |
| |
| // F[virtual_od_en_4]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_virtual_od_en_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_virtual_od_en_4_wd), |
| .d (hw2reg.dio_pad_attr[4].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[4].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_4_virtual_od_en_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].virtual_od_en.qe = dio_pad_attr_4_qe; |
| |
| // F[pull_en_4]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_pull_en_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_pull_en_4_wd), |
| .d (hw2reg.dio_pad_attr[4].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[4].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_4_pull_en_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].pull_en.qe = dio_pad_attr_4_qe; |
| |
| // F[pull_select_4]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_pull_select_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_pull_select_4_wd), |
| .d (hw2reg.dio_pad_attr[4].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[4].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_4_pull_select_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].pull_select.qe = dio_pad_attr_4_qe; |
| |
| // F[keeper_en_4]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_keeper_en_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_keeper_en_4_wd), |
| .d (hw2reg.dio_pad_attr[4].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[4].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_4_keeper_en_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].keeper_en.qe = dio_pad_attr_4_qe; |
| |
| // F[schmitt_en_4]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_schmitt_en_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_schmitt_en_4_wd), |
| .d (hw2reg.dio_pad_attr[4].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[4].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_4_schmitt_en_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].schmitt_en.qe = dio_pad_attr_4_qe; |
| |
| // F[od_en_4]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_4_od_en_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_od_en_4_wd), |
| .d (hw2reg.dio_pad_attr[4].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[4].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_4_od_en_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].od_en.qe = dio_pad_attr_4_qe; |
| |
| // F[slew_rate_4]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_4_slew_rate_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_slew_rate_4_wd), |
| .d (hw2reg.dio_pad_attr[4].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[4].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_4_slew_rate_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].slew_rate.qe = dio_pad_attr_4_qe; |
| |
| // F[drive_strength_4]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_4_drive_strength_4 ( |
| .re (dio_pad_attr_4_re), |
| .we (dio_pad_attr_4_gated_we), |
| .wd (dio_pad_attr_4_drive_strength_4_wd), |
| .d (hw2reg.dio_pad_attr[4].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_4_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[4].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_4_drive_strength_4_qs) |
| ); |
| assign reg2hw.dio_pad_attr[4].drive_strength.qe = dio_pad_attr_4_qe; |
| |
| |
| // Subregister 5 of Multireg dio_pad_attr |
| // R[dio_pad_attr_5]: V(True) |
| logic dio_pad_attr_5_qe; |
| logic [8:0] dio_pad_attr_5_flds_we; |
| assign dio_pad_attr_5_qe = &dio_pad_attr_5_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_5_gated_we; |
| assign dio_pad_attr_5_gated_we = dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs; |
| // F[invert_5]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_invert_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_invert_5_wd), |
| .d (hw2reg.dio_pad_attr[5].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[5].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_5_invert_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].invert.qe = dio_pad_attr_5_qe; |
| |
| // F[virtual_od_en_5]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_virtual_od_en_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_virtual_od_en_5_wd), |
| .d (hw2reg.dio_pad_attr[5].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[5].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_5_virtual_od_en_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].virtual_od_en.qe = dio_pad_attr_5_qe; |
| |
| // F[pull_en_5]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_pull_en_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_pull_en_5_wd), |
| .d (hw2reg.dio_pad_attr[5].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[5].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_5_pull_en_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].pull_en.qe = dio_pad_attr_5_qe; |
| |
| // F[pull_select_5]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_pull_select_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_pull_select_5_wd), |
| .d (hw2reg.dio_pad_attr[5].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[5].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_5_pull_select_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].pull_select.qe = dio_pad_attr_5_qe; |
| |
| // F[keeper_en_5]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_keeper_en_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_keeper_en_5_wd), |
| .d (hw2reg.dio_pad_attr[5].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[5].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_5_keeper_en_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].keeper_en.qe = dio_pad_attr_5_qe; |
| |
| // F[schmitt_en_5]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_schmitt_en_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_schmitt_en_5_wd), |
| .d (hw2reg.dio_pad_attr[5].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[5].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_5_schmitt_en_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].schmitt_en.qe = dio_pad_attr_5_qe; |
| |
| // F[od_en_5]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_5_od_en_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_od_en_5_wd), |
| .d (hw2reg.dio_pad_attr[5].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[5].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_5_od_en_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].od_en.qe = dio_pad_attr_5_qe; |
| |
| // F[slew_rate_5]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_5_slew_rate_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_slew_rate_5_wd), |
| .d (hw2reg.dio_pad_attr[5].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[5].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_5_slew_rate_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].slew_rate.qe = dio_pad_attr_5_qe; |
| |
| // F[drive_strength_5]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_5_drive_strength_5 ( |
| .re (dio_pad_attr_5_re), |
| .we (dio_pad_attr_5_gated_we), |
| .wd (dio_pad_attr_5_drive_strength_5_wd), |
| .d (hw2reg.dio_pad_attr[5].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_5_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[5].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_5_drive_strength_5_qs) |
| ); |
| assign reg2hw.dio_pad_attr[5].drive_strength.qe = dio_pad_attr_5_qe; |
| |
| |
| // Subregister 6 of Multireg dio_pad_attr |
| // R[dio_pad_attr_6]: V(True) |
| logic dio_pad_attr_6_qe; |
| logic [8:0] dio_pad_attr_6_flds_we; |
| assign dio_pad_attr_6_qe = &dio_pad_attr_6_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_6_gated_we; |
| assign dio_pad_attr_6_gated_we = dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs; |
| // F[invert_6]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_invert_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_invert_6_wd), |
| .d (hw2reg.dio_pad_attr[6].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[6].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_6_invert_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].invert.qe = dio_pad_attr_6_qe; |
| |
| // F[virtual_od_en_6]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_virtual_od_en_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_virtual_od_en_6_wd), |
| .d (hw2reg.dio_pad_attr[6].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[6].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_6_virtual_od_en_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].virtual_od_en.qe = dio_pad_attr_6_qe; |
| |
| // F[pull_en_6]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_pull_en_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_pull_en_6_wd), |
| .d (hw2reg.dio_pad_attr[6].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[6].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_6_pull_en_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].pull_en.qe = dio_pad_attr_6_qe; |
| |
| // F[pull_select_6]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_pull_select_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_pull_select_6_wd), |
| .d (hw2reg.dio_pad_attr[6].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[6].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_6_pull_select_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].pull_select.qe = dio_pad_attr_6_qe; |
| |
| // F[keeper_en_6]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_keeper_en_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_keeper_en_6_wd), |
| .d (hw2reg.dio_pad_attr[6].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[6].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_6_keeper_en_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].keeper_en.qe = dio_pad_attr_6_qe; |
| |
| // F[schmitt_en_6]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_schmitt_en_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_schmitt_en_6_wd), |
| .d (hw2reg.dio_pad_attr[6].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[6].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_6_schmitt_en_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].schmitt_en.qe = dio_pad_attr_6_qe; |
| |
| // F[od_en_6]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_6_od_en_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_od_en_6_wd), |
| .d (hw2reg.dio_pad_attr[6].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[6].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_6_od_en_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].od_en.qe = dio_pad_attr_6_qe; |
| |
| // F[slew_rate_6]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_6_slew_rate_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_slew_rate_6_wd), |
| .d (hw2reg.dio_pad_attr[6].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[6].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_6_slew_rate_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].slew_rate.qe = dio_pad_attr_6_qe; |
| |
| // F[drive_strength_6]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_6_drive_strength_6 ( |
| .re (dio_pad_attr_6_re), |
| .we (dio_pad_attr_6_gated_we), |
| .wd (dio_pad_attr_6_drive_strength_6_wd), |
| .d (hw2reg.dio_pad_attr[6].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_6_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[6].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_6_drive_strength_6_qs) |
| ); |
| assign reg2hw.dio_pad_attr[6].drive_strength.qe = dio_pad_attr_6_qe; |
| |
| |
| // Subregister 7 of Multireg dio_pad_attr |
| // R[dio_pad_attr_7]: V(True) |
| logic dio_pad_attr_7_qe; |
| logic [8:0] dio_pad_attr_7_flds_we; |
| assign dio_pad_attr_7_qe = &dio_pad_attr_7_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_7_gated_we; |
| assign dio_pad_attr_7_gated_we = dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs; |
| // F[invert_7]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_invert_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_invert_7_wd), |
| .d (hw2reg.dio_pad_attr[7].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[7].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_7_invert_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].invert.qe = dio_pad_attr_7_qe; |
| |
| // F[virtual_od_en_7]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_virtual_od_en_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_virtual_od_en_7_wd), |
| .d (hw2reg.dio_pad_attr[7].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[7].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_7_virtual_od_en_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].virtual_od_en.qe = dio_pad_attr_7_qe; |
| |
| // F[pull_en_7]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_pull_en_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_pull_en_7_wd), |
| .d (hw2reg.dio_pad_attr[7].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[7].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_7_pull_en_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].pull_en.qe = dio_pad_attr_7_qe; |
| |
| // F[pull_select_7]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_pull_select_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_pull_select_7_wd), |
| .d (hw2reg.dio_pad_attr[7].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[7].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_7_pull_select_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].pull_select.qe = dio_pad_attr_7_qe; |
| |
| // F[keeper_en_7]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_keeper_en_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_keeper_en_7_wd), |
| .d (hw2reg.dio_pad_attr[7].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[7].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_7_keeper_en_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].keeper_en.qe = dio_pad_attr_7_qe; |
| |
| // F[schmitt_en_7]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_schmitt_en_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_schmitt_en_7_wd), |
| .d (hw2reg.dio_pad_attr[7].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[7].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_7_schmitt_en_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].schmitt_en.qe = dio_pad_attr_7_qe; |
| |
| // F[od_en_7]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_7_od_en_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_od_en_7_wd), |
| .d (hw2reg.dio_pad_attr[7].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[7].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_7_od_en_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].od_en.qe = dio_pad_attr_7_qe; |
| |
| // F[slew_rate_7]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_7_slew_rate_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_slew_rate_7_wd), |
| .d (hw2reg.dio_pad_attr[7].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[7].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_7_slew_rate_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].slew_rate.qe = dio_pad_attr_7_qe; |
| |
| // F[drive_strength_7]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_7_drive_strength_7 ( |
| .re (dio_pad_attr_7_re), |
| .we (dio_pad_attr_7_gated_we), |
| .wd (dio_pad_attr_7_drive_strength_7_wd), |
| .d (hw2reg.dio_pad_attr[7].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_7_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[7].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_7_drive_strength_7_qs) |
| ); |
| assign reg2hw.dio_pad_attr[7].drive_strength.qe = dio_pad_attr_7_qe; |
| |
| |
| // Subregister 8 of Multireg dio_pad_attr |
| // R[dio_pad_attr_8]: V(True) |
| logic dio_pad_attr_8_qe; |
| logic [8:0] dio_pad_attr_8_flds_we; |
| assign dio_pad_attr_8_qe = &dio_pad_attr_8_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_8_gated_we; |
| assign dio_pad_attr_8_gated_we = dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs; |
| // F[invert_8]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_invert_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_invert_8_wd), |
| .d (hw2reg.dio_pad_attr[8].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[8].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_8_invert_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].invert.qe = dio_pad_attr_8_qe; |
| |
| // F[virtual_od_en_8]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_virtual_od_en_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_virtual_od_en_8_wd), |
| .d (hw2reg.dio_pad_attr[8].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[8].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_8_virtual_od_en_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].virtual_od_en.qe = dio_pad_attr_8_qe; |
| |
| // F[pull_en_8]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_pull_en_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_pull_en_8_wd), |
| .d (hw2reg.dio_pad_attr[8].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[8].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_8_pull_en_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].pull_en.qe = dio_pad_attr_8_qe; |
| |
| // F[pull_select_8]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_pull_select_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_pull_select_8_wd), |
| .d (hw2reg.dio_pad_attr[8].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[8].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_8_pull_select_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].pull_select.qe = dio_pad_attr_8_qe; |
| |
| // F[keeper_en_8]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_keeper_en_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_keeper_en_8_wd), |
| .d (hw2reg.dio_pad_attr[8].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[8].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_8_keeper_en_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].keeper_en.qe = dio_pad_attr_8_qe; |
| |
| // F[schmitt_en_8]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_schmitt_en_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_schmitt_en_8_wd), |
| .d (hw2reg.dio_pad_attr[8].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[8].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_8_schmitt_en_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].schmitt_en.qe = dio_pad_attr_8_qe; |
| |
| // F[od_en_8]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_8_od_en_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_od_en_8_wd), |
| .d (hw2reg.dio_pad_attr[8].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[8].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_8_od_en_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].od_en.qe = dio_pad_attr_8_qe; |
| |
| // F[slew_rate_8]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_8_slew_rate_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_slew_rate_8_wd), |
| .d (hw2reg.dio_pad_attr[8].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[8].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_8_slew_rate_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].slew_rate.qe = dio_pad_attr_8_qe; |
| |
| // F[drive_strength_8]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_8_drive_strength_8 ( |
| .re (dio_pad_attr_8_re), |
| .we (dio_pad_attr_8_gated_we), |
| .wd (dio_pad_attr_8_drive_strength_8_wd), |
| .d (hw2reg.dio_pad_attr[8].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_8_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[8].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_8_drive_strength_8_qs) |
| ); |
| assign reg2hw.dio_pad_attr[8].drive_strength.qe = dio_pad_attr_8_qe; |
| |
| |
| // Subregister 9 of Multireg dio_pad_attr |
| // R[dio_pad_attr_9]: V(True) |
| logic dio_pad_attr_9_qe; |
| logic [8:0] dio_pad_attr_9_flds_we; |
| assign dio_pad_attr_9_qe = &dio_pad_attr_9_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_9_gated_we; |
| assign dio_pad_attr_9_gated_we = dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs; |
| // F[invert_9]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_invert_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_invert_9_wd), |
| .d (hw2reg.dio_pad_attr[9].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[9].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_9_invert_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].invert.qe = dio_pad_attr_9_qe; |
| |
| // F[virtual_od_en_9]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_virtual_od_en_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_virtual_od_en_9_wd), |
| .d (hw2reg.dio_pad_attr[9].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[9].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_9_virtual_od_en_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].virtual_od_en.qe = dio_pad_attr_9_qe; |
| |
| // F[pull_en_9]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_pull_en_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_pull_en_9_wd), |
| .d (hw2reg.dio_pad_attr[9].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[9].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_9_pull_en_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].pull_en.qe = dio_pad_attr_9_qe; |
| |
| // F[pull_select_9]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_pull_select_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_pull_select_9_wd), |
| .d (hw2reg.dio_pad_attr[9].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[9].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_9_pull_select_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].pull_select.qe = dio_pad_attr_9_qe; |
| |
| // F[keeper_en_9]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_keeper_en_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_keeper_en_9_wd), |
| .d (hw2reg.dio_pad_attr[9].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[9].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_9_keeper_en_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].keeper_en.qe = dio_pad_attr_9_qe; |
| |
| // F[schmitt_en_9]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_schmitt_en_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_schmitt_en_9_wd), |
| .d (hw2reg.dio_pad_attr[9].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[9].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_9_schmitt_en_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].schmitt_en.qe = dio_pad_attr_9_qe; |
| |
| // F[od_en_9]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_9_od_en_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_od_en_9_wd), |
| .d (hw2reg.dio_pad_attr[9].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[9].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_9_od_en_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].od_en.qe = dio_pad_attr_9_qe; |
| |
| // F[slew_rate_9]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_9_slew_rate_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_slew_rate_9_wd), |
| .d (hw2reg.dio_pad_attr[9].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[9].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_9_slew_rate_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].slew_rate.qe = dio_pad_attr_9_qe; |
| |
| // F[drive_strength_9]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_9_drive_strength_9 ( |
| .re (dio_pad_attr_9_re), |
| .we (dio_pad_attr_9_gated_we), |
| .wd (dio_pad_attr_9_drive_strength_9_wd), |
| .d (hw2reg.dio_pad_attr[9].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_9_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[9].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_9_drive_strength_9_qs) |
| ); |
| assign reg2hw.dio_pad_attr[9].drive_strength.qe = dio_pad_attr_9_qe; |
| |
| |
| // Subregister 10 of Multireg dio_pad_attr |
| // R[dio_pad_attr_10]: V(True) |
| logic dio_pad_attr_10_qe; |
| logic [8:0] dio_pad_attr_10_flds_we; |
| assign dio_pad_attr_10_qe = &dio_pad_attr_10_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_10_gated_we; |
| assign dio_pad_attr_10_gated_we = dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs; |
| // F[invert_10]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_invert_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_invert_10_wd), |
| .d (hw2reg.dio_pad_attr[10].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[10].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_10_invert_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].invert.qe = dio_pad_attr_10_qe; |
| |
| // F[virtual_od_en_10]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_virtual_od_en_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_virtual_od_en_10_wd), |
| .d (hw2reg.dio_pad_attr[10].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[10].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_10_virtual_od_en_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].virtual_od_en.qe = dio_pad_attr_10_qe; |
| |
| // F[pull_en_10]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_pull_en_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_pull_en_10_wd), |
| .d (hw2reg.dio_pad_attr[10].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[10].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_10_pull_en_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].pull_en.qe = dio_pad_attr_10_qe; |
| |
| // F[pull_select_10]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_pull_select_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_pull_select_10_wd), |
| .d (hw2reg.dio_pad_attr[10].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[10].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_10_pull_select_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].pull_select.qe = dio_pad_attr_10_qe; |
| |
| // F[keeper_en_10]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_keeper_en_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_keeper_en_10_wd), |
| .d (hw2reg.dio_pad_attr[10].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[10].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_10_keeper_en_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].keeper_en.qe = dio_pad_attr_10_qe; |
| |
| // F[schmitt_en_10]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_schmitt_en_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_schmitt_en_10_wd), |
| .d (hw2reg.dio_pad_attr[10].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[10].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_10_schmitt_en_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].schmitt_en.qe = dio_pad_attr_10_qe; |
| |
| // F[od_en_10]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_10_od_en_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_od_en_10_wd), |
| .d (hw2reg.dio_pad_attr[10].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[10].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_10_od_en_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].od_en.qe = dio_pad_attr_10_qe; |
| |
| // F[slew_rate_10]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_10_slew_rate_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_slew_rate_10_wd), |
| .d (hw2reg.dio_pad_attr[10].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[10].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_10_slew_rate_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].slew_rate.qe = dio_pad_attr_10_qe; |
| |
| // F[drive_strength_10]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_10_drive_strength_10 ( |
| .re (dio_pad_attr_10_re), |
| .we (dio_pad_attr_10_gated_we), |
| .wd (dio_pad_attr_10_drive_strength_10_wd), |
| .d (hw2reg.dio_pad_attr[10].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_10_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[10].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_10_drive_strength_10_qs) |
| ); |
| assign reg2hw.dio_pad_attr[10].drive_strength.qe = dio_pad_attr_10_qe; |
| |
| |
| // Subregister 11 of Multireg dio_pad_attr |
| // R[dio_pad_attr_11]: V(True) |
| logic dio_pad_attr_11_qe; |
| logic [8:0] dio_pad_attr_11_flds_we; |
| assign dio_pad_attr_11_qe = &dio_pad_attr_11_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_11_gated_we; |
| assign dio_pad_attr_11_gated_we = dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs; |
| // F[invert_11]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_invert_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_invert_11_wd), |
| .d (hw2reg.dio_pad_attr[11].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[11].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_11_invert_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].invert.qe = dio_pad_attr_11_qe; |
| |
| // F[virtual_od_en_11]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_virtual_od_en_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_virtual_od_en_11_wd), |
| .d (hw2reg.dio_pad_attr[11].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[11].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_11_virtual_od_en_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].virtual_od_en.qe = dio_pad_attr_11_qe; |
| |
| // F[pull_en_11]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_pull_en_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_pull_en_11_wd), |
| .d (hw2reg.dio_pad_attr[11].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[11].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_11_pull_en_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].pull_en.qe = dio_pad_attr_11_qe; |
| |
| // F[pull_select_11]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_pull_select_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_pull_select_11_wd), |
| .d (hw2reg.dio_pad_attr[11].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[11].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_11_pull_select_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].pull_select.qe = dio_pad_attr_11_qe; |
| |
| // F[keeper_en_11]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_keeper_en_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_keeper_en_11_wd), |
| .d (hw2reg.dio_pad_attr[11].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[11].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_11_keeper_en_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].keeper_en.qe = dio_pad_attr_11_qe; |
| |
| // F[schmitt_en_11]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_schmitt_en_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_schmitt_en_11_wd), |
| .d (hw2reg.dio_pad_attr[11].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[11].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_11_schmitt_en_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].schmitt_en.qe = dio_pad_attr_11_qe; |
| |
| // F[od_en_11]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_11_od_en_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_od_en_11_wd), |
| .d (hw2reg.dio_pad_attr[11].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[11].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_11_od_en_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].od_en.qe = dio_pad_attr_11_qe; |
| |
| // F[slew_rate_11]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_11_slew_rate_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_slew_rate_11_wd), |
| .d (hw2reg.dio_pad_attr[11].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[11].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_11_slew_rate_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].slew_rate.qe = dio_pad_attr_11_qe; |
| |
| // F[drive_strength_11]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_11_drive_strength_11 ( |
| .re (dio_pad_attr_11_re), |
| .we (dio_pad_attr_11_gated_we), |
| .wd (dio_pad_attr_11_drive_strength_11_wd), |
| .d (hw2reg.dio_pad_attr[11].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_11_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[11].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_11_drive_strength_11_qs) |
| ); |
| assign reg2hw.dio_pad_attr[11].drive_strength.qe = dio_pad_attr_11_qe; |
| |
| |
| // Subregister 12 of Multireg dio_pad_attr |
| // R[dio_pad_attr_12]: V(True) |
| logic dio_pad_attr_12_qe; |
| logic [8:0] dio_pad_attr_12_flds_we; |
| assign dio_pad_attr_12_qe = &dio_pad_attr_12_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_12_gated_we; |
| assign dio_pad_attr_12_gated_we = dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs; |
| // F[invert_12]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_invert_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_invert_12_wd), |
| .d (hw2reg.dio_pad_attr[12].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[12].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_12_invert_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].invert.qe = dio_pad_attr_12_qe; |
| |
| // F[virtual_od_en_12]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_virtual_od_en_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_virtual_od_en_12_wd), |
| .d (hw2reg.dio_pad_attr[12].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[12].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_12_virtual_od_en_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].virtual_od_en.qe = dio_pad_attr_12_qe; |
| |
| // F[pull_en_12]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_pull_en_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_pull_en_12_wd), |
| .d (hw2reg.dio_pad_attr[12].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[12].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_12_pull_en_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].pull_en.qe = dio_pad_attr_12_qe; |
| |
| // F[pull_select_12]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_pull_select_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_pull_select_12_wd), |
| .d (hw2reg.dio_pad_attr[12].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[12].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_12_pull_select_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].pull_select.qe = dio_pad_attr_12_qe; |
| |
| // F[keeper_en_12]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_keeper_en_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_keeper_en_12_wd), |
| .d (hw2reg.dio_pad_attr[12].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[12].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_12_keeper_en_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].keeper_en.qe = dio_pad_attr_12_qe; |
| |
| // F[schmitt_en_12]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_schmitt_en_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_schmitt_en_12_wd), |
| .d (hw2reg.dio_pad_attr[12].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[12].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_12_schmitt_en_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].schmitt_en.qe = dio_pad_attr_12_qe; |
| |
| // F[od_en_12]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_12_od_en_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_od_en_12_wd), |
| .d (hw2reg.dio_pad_attr[12].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[12].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_12_od_en_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].od_en.qe = dio_pad_attr_12_qe; |
| |
| // F[slew_rate_12]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_12_slew_rate_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_slew_rate_12_wd), |
| .d (hw2reg.dio_pad_attr[12].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[12].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_12_slew_rate_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].slew_rate.qe = dio_pad_attr_12_qe; |
| |
| // F[drive_strength_12]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_12_drive_strength_12 ( |
| .re (dio_pad_attr_12_re), |
| .we (dio_pad_attr_12_gated_we), |
| .wd (dio_pad_attr_12_drive_strength_12_wd), |
| .d (hw2reg.dio_pad_attr[12].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_12_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[12].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_12_drive_strength_12_qs) |
| ); |
| assign reg2hw.dio_pad_attr[12].drive_strength.qe = dio_pad_attr_12_qe; |
| |
| |
| // Subregister 13 of Multireg dio_pad_attr |
| // R[dio_pad_attr_13]: V(True) |
| logic dio_pad_attr_13_qe; |
| logic [8:0] dio_pad_attr_13_flds_we; |
| assign dio_pad_attr_13_qe = &dio_pad_attr_13_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_13_gated_we; |
| assign dio_pad_attr_13_gated_we = dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs; |
| // F[invert_13]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_invert_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_invert_13_wd), |
| .d (hw2reg.dio_pad_attr[13].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[13].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_13_invert_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].invert.qe = dio_pad_attr_13_qe; |
| |
| // F[virtual_od_en_13]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_virtual_od_en_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_virtual_od_en_13_wd), |
| .d (hw2reg.dio_pad_attr[13].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[13].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_13_virtual_od_en_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].virtual_od_en.qe = dio_pad_attr_13_qe; |
| |
| // F[pull_en_13]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_pull_en_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_pull_en_13_wd), |
| .d (hw2reg.dio_pad_attr[13].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[13].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_13_pull_en_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].pull_en.qe = dio_pad_attr_13_qe; |
| |
| // F[pull_select_13]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_pull_select_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_pull_select_13_wd), |
| .d (hw2reg.dio_pad_attr[13].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[13].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_13_pull_select_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].pull_select.qe = dio_pad_attr_13_qe; |
| |
| // F[keeper_en_13]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_keeper_en_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_keeper_en_13_wd), |
| .d (hw2reg.dio_pad_attr[13].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[13].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_13_keeper_en_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].keeper_en.qe = dio_pad_attr_13_qe; |
| |
| // F[schmitt_en_13]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_schmitt_en_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_schmitt_en_13_wd), |
| .d (hw2reg.dio_pad_attr[13].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[13].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_13_schmitt_en_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].schmitt_en.qe = dio_pad_attr_13_qe; |
| |
| // F[od_en_13]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_13_od_en_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_od_en_13_wd), |
| .d (hw2reg.dio_pad_attr[13].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[13].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_13_od_en_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].od_en.qe = dio_pad_attr_13_qe; |
| |
| // F[slew_rate_13]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_13_slew_rate_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_slew_rate_13_wd), |
| .d (hw2reg.dio_pad_attr[13].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[13].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_13_slew_rate_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].slew_rate.qe = dio_pad_attr_13_qe; |
| |
| // F[drive_strength_13]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_13_drive_strength_13 ( |
| .re (dio_pad_attr_13_re), |
| .we (dio_pad_attr_13_gated_we), |
| .wd (dio_pad_attr_13_drive_strength_13_wd), |
| .d (hw2reg.dio_pad_attr[13].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_13_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[13].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_13_drive_strength_13_qs) |
| ); |
| assign reg2hw.dio_pad_attr[13].drive_strength.qe = dio_pad_attr_13_qe; |
| |
| |
| // Subregister 14 of Multireg dio_pad_attr |
| // R[dio_pad_attr_14]: V(True) |
| logic dio_pad_attr_14_qe; |
| logic [8:0] dio_pad_attr_14_flds_we; |
| assign dio_pad_attr_14_qe = &dio_pad_attr_14_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_14_gated_we; |
| assign dio_pad_attr_14_gated_we = dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs; |
| // F[invert_14]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_invert_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_invert_14_wd), |
| .d (hw2reg.dio_pad_attr[14].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[14].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_14_invert_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].invert.qe = dio_pad_attr_14_qe; |
| |
| // F[virtual_od_en_14]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_virtual_od_en_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_virtual_od_en_14_wd), |
| .d (hw2reg.dio_pad_attr[14].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[14].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_14_virtual_od_en_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].virtual_od_en.qe = dio_pad_attr_14_qe; |
| |
| // F[pull_en_14]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_pull_en_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_pull_en_14_wd), |
| .d (hw2reg.dio_pad_attr[14].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[14].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_14_pull_en_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].pull_en.qe = dio_pad_attr_14_qe; |
| |
| // F[pull_select_14]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_pull_select_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_pull_select_14_wd), |
| .d (hw2reg.dio_pad_attr[14].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[14].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_14_pull_select_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].pull_select.qe = dio_pad_attr_14_qe; |
| |
| // F[keeper_en_14]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_keeper_en_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_keeper_en_14_wd), |
| .d (hw2reg.dio_pad_attr[14].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[14].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_14_keeper_en_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].keeper_en.qe = dio_pad_attr_14_qe; |
| |
| // F[schmitt_en_14]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_schmitt_en_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_schmitt_en_14_wd), |
| .d (hw2reg.dio_pad_attr[14].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[14].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_14_schmitt_en_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].schmitt_en.qe = dio_pad_attr_14_qe; |
| |
| // F[od_en_14]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_14_od_en_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_od_en_14_wd), |
| .d (hw2reg.dio_pad_attr[14].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[14].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_14_od_en_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].od_en.qe = dio_pad_attr_14_qe; |
| |
| // F[slew_rate_14]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_14_slew_rate_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_slew_rate_14_wd), |
| .d (hw2reg.dio_pad_attr[14].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[14].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_14_slew_rate_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].slew_rate.qe = dio_pad_attr_14_qe; |
| |
| // F[drive_strength_14]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_14_drive_strength_14 ( |
| .re (dio_pad_attr_14_re), |
| .we (dio_pad_attr_14_gated_we), |
| .wd (dio_pad_attr_14_drive_strength_14_wd), |
| .d (hw2reg.dio_pad_attr[14].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_14_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[14].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_14_drive_strength_14_qs) |
| ); |
| assign reg2hw.dio_pad_attr[14].drive_strength.qe = dio_pad_attr_14_qe; |
| |
| |
| // Subregister 15 of Multireg dio_pad_attr |
| // R[dio_pad_attr_15]: V(True) |
| logic dio_pad_attr_15_qe; |
| logic [8:0] dio_pad_attr_15_flds_we; |
| assign dio_pad_attr_15_qe = &dio_pad_attr_15_flds_we; |
| // Create REGWEN-gated WE signal |
| logic dio_pad_attr_15_gated_we; |
| assign dio_pad_attr_15_gated_we = dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs; |
| // F[invert_15]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_invert_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_invert_15_wd), |
| .d (hw2reg.dio_pad_attr[15].invert.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[0]), |
| .q (reg2hw.dio_pad_attr[15].invert.q), |
| .ds (), |
| .qs (dio_pad_attr_15_invert_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].invert.qe = dio_pad_attr_15_qe; |
| |
| // F[virtual_od_en_15]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_virtual_od_en_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_virtual_od_en_15_wd), |
| .d (hw2reg.dio_pad_attr[15].virtual_od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[1]), |
| .q (reg2hw.dio_pad_attr[15].virtual_od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_15_virtual_od_en_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].virtual_od_en.qe = dio_pad_attr_15_qe; |
| |
| // F[pull_en_15]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_pull_en_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_pull_en_15_wd), |
| .d (hw2reg.dio_pad_attr[15].pull_en.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[2]), |
| .q (reg2hw.dio_pad_attr[15].pull_en.q), |
| .ds (), |
| .qs (dio_pad_attr_15_pull_en_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].pull_en.qe = dio_pad_attr_15_qe; |
| |
| // F[pull_select_15]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_pull_select_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_pull_select_15_wd), |
| .d (hw2reg.dio_pad_attr[15].pull_select.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[3]), |
| .q (reg2hw.dio_pad_attr[15].pull_select.q), |
| .ds (), |
| .qs (dio_pad_attr_15_pull_select_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].pull_select.qe = dio_pad_attr_15_qe; |
| |
| // F[keeper_en_15]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_keeper_en_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_keeper_en_15_wd), |
| .d (hw2reg.dio_pad_attr[15].keeper_en.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[4]), |
| .q (reg2hw.dio_pad_attr[15].keeper_en.q), |
| .ds (), |
| .qs (dio_pad_attr_15_keeper_en_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].keeper_en.qe = dio_pad_attr_15_qe; |
| |
| // F[schmitt_en_15]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_schmitt_en_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_schmitt_en_15_wd), |
| .d (hw2reg.dio_pad_attr[15].schmitt_en.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[5]), |
| .q (reg2hw.dio_pad_attr[15].schmitt_en.q), |
| .ds (), |
| .qs (dio_pad_attr_15_schmitt_en_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].schmitt_en.qe = dio_pad_attr_15_qe; |
| |
| // F[od_en_15]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_dio_pad_attr_15_od_en_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_od_en_15_wd), |
| .d (hw2reg.dio_pad_attr[15].od_en.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[6]), |
| .q (reg2hw.dio_pad_attr[15].od_en.q), |
| .ds (), |
| .qs (dio_pad_attr_15_od_en_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].od_en.qe = dio_pad_attr_15_qe; |
| |
| // F[slew_rate_15]: 17:16 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_dio_pad_attr_15_slew_rate_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_slew_rate_15_wd), |
| .d (hw2reg.dio_pad_attr[15].slew_rate.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[7]), |
| .q (reg2hw.dio_pad_attr[15].slew_rate.q), |
| .ds (), |
| .qs (dio_pad_attr_15_slew_rate_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].slew_rate.qe = dio_pad_attr_15_qe; |
| |
| // F[drive_strength_15]: 23:20 |
| prim_subreg_ext #( |
| .DW (4) |
| ) u_dio_pad_attr_15_drive_strength_15 ( |
| .re (dio_pad_attr_15_re), |
| .we (dio_pad_attr_15_gated_we), |
| .wd (dio_pad_attr_15_drive_strength_15_wd), |
| .d (hw2reg.dio_pad_attr[15].drive_strength.d), |
| .qre (), |
| .qe (dio_pad_attr_15_flds_we[8]), |
| .q (reg2hw.dio_pad_attr[15].drive_strength.q), |
| .ds (), |
| .qs (dio_pad_attr_15_drive_strength_15_qs) |
| ); |
| assign reg2hw.dio_pad_attr[15].drive_strength.qe = dio_pad_attr_15_qe; |
| |
| |
| // Subregister 0 of Multireg mio_pad_sleep_status |
| // R[mio_pad_sleep_status]: V(False) |
| // F[en_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_0_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[0].de), |
| .d (hw2reg.mio_pad_sleep_status[0].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_0_qs) |
| ); |
| |
| // F[en_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_1_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[1].de), |
| .d (hw2reg.mio_pad_sleep_status[1].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_1_qs) |
| ); |
| |
| // F[en_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_2_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[2].de), |
| .d (hw2reg.mio_pad_sleep_status[2].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_2_qs) |
| ); |
| |
| // F[en_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_3_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[3].de), |
| .d (hw2reg.mio_pad_sleep_status[3].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_3_qs) |
| ); |
| |
| // F[en_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_4_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[4].de), |
| .d (hw2reg.mio_pad_sleep_status[4].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_4_qs) |
| ); |
| |
| // F[en_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_5_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[5].de), |
| .d (hw2reg.mio_pad_sleep_status[5].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_5_qs) |
| ); |
| |
| // F[en_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_6_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[6].de), |
| .d (hw2reg.mio_pad_sleep_status[6].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_6_qs) |
| ); |
| |
| // F[en_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_7_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[7].de), |
| .d (hw2reg.mio_pad_sleep_status[7].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_7_qs) |
| ); |
| |
| // F[en_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_8_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[8].de), |
| .d (hw2reg.mio_pad_sleep_status[8].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_8_qs) |
| ); |
| |
| // F[en_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_9_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[9].de), |
| .d (hw2reg.mio_pad_sleep_status[9].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_9_qs) |
| ); |
| |
| // F[en_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_10_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[10].de), |
| .d (hw2reg.mio_pad_sleep_status[10].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_10_qs) |
| ); |
| |
| // F[en_11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_11_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[11].de), |
| .d (hw2reg.mio_pad_sleep_status[11].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_11_qs) |
| ); |
| |
| // F[en_12]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_12_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[12].de), |
| .d (hw2reg.mio_pad_sleep_status[12].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_12_qs) |
| ); |
| |
| // F[en_13]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_13_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[13].de), |
| .d (hw2reg.mio_pad_sleep_status[13].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_13_qs) |
| ); |
| |
| // F[en_14]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_14_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[14].de), |
| .d (hw2reg.mio_pad_sleep_status[14].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_14_qs) |
| ); |
| |
| // F[en_15]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_15_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[15].de), |
| .d (hw2reg.mio_pad_sleep_status[15].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_15_qs) |
| ); |
| |
| // F[en_16]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_16_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[16].de), |
| .d (hw2reg.mio_pad_sleep_status[16].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_16_qs) |
| ); |
| |
| // F[en_17]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_17_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[17].de), |
| .d (hw2reg.mio_pad_sleep_status[17].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_17_qs) |
| ); |
| |
| // F[en_18]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_18_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[18].de), |
| .d (hw2reg.mio_pad_sleep_status[18].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_18_qs) |
| ); |
| |
| // F[en_19]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_19_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[19].de), |
| .d (hw2reg.mio_pad_sleep_status[19].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_19_qs) |
| ); |
| |
| // F[en_20]: 20:20 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_20_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[20].de), |
| .d (hw2reg.mio_pad_sleep_status[20].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_20_qs) |
| ); |
| |
| // F[en_21]: 21:21 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_21_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[21].de), |
| .d (hw2reg.mio_pad_sleep_status[21].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_21_qs) |
| ); |
| |
| // F[en_22]: 22:22 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_22_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[22].de), |
| .d (hw2reg.mio_pad_sleep_status[22].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_22_qs) |
| ); |
| |
| // F[en_23]: 23:23 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_23_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[23].de), |
| .d (hw2reg.mio_pad_sleep_status[23].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_23_qs) |
| ); |
| |
| // F[en_24]: 24:24 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_24_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[24].de), |
| .d (hw2reg.mio_pad_sleep_status[24].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_24_qs) |
| ); |
| |
| // F[en_25]: 25:25 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_25_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[25].de), |
| .d (hw2reg.mio_pad_sleep_status[25].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_25_qs) |
| ); |
| |
| // F[en_26]: 26:26 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_26_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[26].de), |
| .d (hw2reg.mio_pad_sleep_status[26].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_26_qs) |
| ); |
| |
| // F[en_27]: 27:27 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_27_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[27].de), |
| .d (hw2reg.mio_pad_sleep_status[27].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_27_qs) |
| ); |
| |
| // F[en_28]: 28:28 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_28_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[28].de), |
| .d (hw2reg.mio_pad_sleep_status[28].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_28_qs) |
| ); |
| |
| // F[en_29]: 29:29 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_29_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[29].de), |
| .d (hw2reg.mio_pad_sleep_status[29].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_29_qs) |
| ); |
| |
| // F[en_30]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_30_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[30].de), |
| .d (hw2reg.mio_pad_sleep_status[30].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[30].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_30_qs) |
| ); |
| |
| // F[en_31]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_status_en_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_status_we), |
| .wd (mio_pad_sleep_status_en_31_wd), |
| |
| // from internal hardware |
| .de (hw2reg.mio_pad_sleep_status[31].de), |
| .d (hw2reg.mio_pad_sleep_status[31].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_status[31].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_status_en_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_0_we), |
| .wd (mio_pad_sleep_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_1_we), |
| .wd (mio_pad_sleep_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_2_we), |
| .wd (mio_pad_sleep_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_3_we), |
| .wd (mio_pad_sleep_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_4_we), |
| .wd (mio_pad_sleep_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_5_we), |
| .wd (mio_pad_sleep_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_6_we), |
| .wd (mio_pad_sleep_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_7_we), |
| .wd (mio_pad_sleep_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_8]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_8_we), |
| .wd (mio_pad_sleep_regwen_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_9]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_9_we), |
| .wd (mio_pad_sleep_regwen_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_10]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_10_we), |
| .wd (mio_pad_sleep_regwen_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_11]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_11_we), |
| .wd (mio_pad_sleep_regwen_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_12]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_12_we), |
| .wd (mio_pad_sleep_regwen_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_13]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_13_we), |
| .wd (mio_pad_sleep_regwen_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_14]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_14_we), |
| .wd (mio_pad_sleep_regwen_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_15]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_15_we), |
| .wd (mio_pad_sleep_regwen_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_16]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_16_we), |
| .wd (mio_pad_sleep_regwen_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_17]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_17_we), |
| .wd (mio_pad_sleep_regwen_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_18]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_18_we), |
| .wd (mio_pad_sleep_regwen_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_19]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_19_we), |
| .wd (mio_pad_sleep_regwen_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_20]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_20_we), |
| .wd (mio_pad_sleep_regwen_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_21]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_21_we), |
| .wd (mio_pad_sleep_regwen_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_22]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_22_we), |
| .wd (mio_pad_sleep_regwen_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_23]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_23_we), |
| .wd (mio_pad_sleep_regwen_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_24]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_24_we), |
| .wd (mio_pad_sleep_regwen_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_25]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_25_we), |
| .wd (mio_pad_sleep_regwen_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_26]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_26_we), |
| .wd (mio_pad_sleep_regwen_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_27]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_27_we), |
| .wd (mio_pad_sleep_regwen_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_28]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_28_we), |
| .wd (mio_pad_sleep_regwen_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_29]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_29_we), |
| .wd (mio_pad_sleep_regwen_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_30]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_30_we), |
| .wd (mio_pad_sleep_regwen_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_pad_sleep_regwen |
| // R[mio_pad_sleep_regwen_31]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_mio_pad_sleep_regwen_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_regwen_31_we), |
| .wd (mio_pad_sleep_regwen_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_regwen_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_0_gated_we; |
| assign mio_pad_sleep_en_0_gated_we = mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_0_gated_we), |
| .wd (mio_pad_sleep_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_1_gated_we; |
| assign mio_pad_sleep_en_1_gated_we = mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_1_gated_we), |
| .wd (mio_pad_sleep_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_2_gated_we; |
| assign mio_pad_sleep_en_2_gated_we = mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_2_gated_we), |
| .wd (mio_pad_sleep_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_3_gated_we; |
| assign mio_pad_sleep_en_3_gated_we = mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_3_gated_we), |
| .wd (mio_pad_sleep_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_4_gated_we; |
| assign mio_pad_sleep_en_4_gated_we = mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_4_gated_we), |
| .wd (mio_pad_sleep_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_5_gated_we; |
| assign mio_pad_sleep_en_5_gated_we = mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_5_gated_we), |
| .wd (mio_pad_sleep_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_6_gated_we; |
| assign mio_pad_sleep_en_6_gated_we = mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_6_gated_we), |
| .wd (mio_pad_sleep_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_7_gated_we; |
| assign mio_pad_sleep_en_7_gated_we = mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_7_gated_we), |
| .wd (mio_pad_sleep_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_8]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_8_gated_we; |
| assign mio_pad_sleep_en_8_gated_we = mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_8_gated_we), |
| .wd (mio_pad_sleep_en_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_9]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_9_gated_we; |
| assign mio_pad_sleep_en_9_gated_we = mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_9_gated_we), |
| .wd (mio_pad_sleep_en_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_10]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_10_gated_we; |
| assign mio_pad_sleep_en_10_gated_we = mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_10_gated_we), |
| .wd (mio_pad_sleep_en_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_11]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_11_gated_we; |
| assign mio_pad_sleep_en_11_gated_we = mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_11_gated_we), |
| .wd (mio_pad_sleep_en_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_12]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_12_gated_we; |
| assign mio_pad_sleep_en_12_gated_we = mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_12_gated_we), |
| .wd (mio_pad_sleep_en_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_13]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_13_gated_we; |
| assign mio_pad_sleep_en_13_gated_we = mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_13_gated_we), |
| .wd (mio_pad_sleep_en_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_14]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_14_gated_we; |
| assign mio_pad_sleep_en_14_gated_we = mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_14_gated_we), |
| .wd (mio_pad_sleep_en_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_15]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_15_gated_we; |
| assign mio_pad_sleep_en_15_gated_we = mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_15_gated_we), |
| .wd (mio_pad_sleep_en_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_16]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_16_gated_we; |
| assign mio_pad_sleep_en_16_gated_we = mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_16_gated_we), |
| .wd (mio_pad_sleep_en_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_17]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_17_gated_we; |
| assign mio_pad_sleep_en_17_gated_we = mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_17_gated_we), |
| .wd (mio_pad_sleep_en_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_18]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_18_gated_we; |
| assign mio_pad_sleep_en_18_gated_we = mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_18_gated_we), |
| .wd (mio_pad_sleep_en_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_19]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_19_gated_we; |
| assign mio_pad_sleep_en_19_gated_we = mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_19_gated_we), |
| .wd (mio_pad_sleep_en_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_20]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_20_gated_we; |
| assign mio_pad_sleep_en_20_gated_we = mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_20_gated_we), |
| .wd (mio_pad_sleep_en_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_21]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_21_gated_we; |
| assign mio_pad_sleep_en_21_gated_we = mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_21_gated_we), |
| .wd (mio_pad_sleep_en_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_22]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_22_gated_we; |
| assign mio_pad_sleep_en_22_gated_we = mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_22_gated_we), |
| .wd (mio_pad_sleep_en_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_23]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_23_gated_we; |
| assign mio_pad_sleep_en_23_gated_we = mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_23_gated_we), |
| .wd (mio_pad_sleep_en_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_24]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_24_gated_we; |
| assign mio_pad_sleep_en_24_gated_we = mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_24_gated_we), |
| .wd (mio_pad_sleep_en_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_25]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_25_gated_we; |
| assign mio_pad_sleep_en_25_gated_we = mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_25_gated_we), |
| .wd (mio_pad_sleep_en_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_26]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_26_gated_we; |
| assign mio_pad_sleep_en_26_gated_we = mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_26_gated_we), |
| .wd (mio_pad_sleep_en_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_27]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_27_gated_we; |
| assign mio_pad_sleep_en_27_gated_we = mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_27_gated_we), |
| .wd (mio_pad_sleep_en_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_28]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_28_gated_we; |
| assign mio_pad_sleep_en_28_gated_we = mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_28_gated_we), |
| .wd (mio_pad_sleep_en_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_29]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_29_gated_we; |
| assign mio_pad_sleep_en_29_gated_we = mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_29_gated_we), |
| .wd (mio_pad_sleep_en_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_30]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_30_gated_we; |
| assign mio_pad_sleep_en_30_gated_we = mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_30_gated_we), |
| .wd (mio_pad_sleep_en_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[30].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_pad_sleep_en |
| // R[mio_pad_sleep_en_31]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_en_31_gated_we; |
| assign mio_pad_sleep_en_31_gated_we = mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_mio_pad_sleep_en_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_en_31_gated_we), |
| .wd (mio_pad_sleep_en_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_en[31].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_en_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_0_gated_we; |
| assign mio_pad_sleep_mode_0_gated_we = mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_0_gated_we), |
| .wd (mio_pad_sleep_mode_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_1_gated_we; |
| assign mio_pad_sleep_mode_1_gated_we = mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_1_gated_we), |
| .wd (mio_pad_sleep_mode_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_2_gated_we; |
| assign mio_pad_sleep_mode_2_gated_we = mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_2_gated_we), |
| .wd (mio_pad_sleep_mode_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_3_gated_we; |
| assign mio_pad_sleep_mode_3_gated_we = mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_3_gated_we), |
| .wd (mio_pad_sleep_mode_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_4_gated_we; |
| assign mio_pad_sleep_mode_4_gated_we = mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_4_gated_we), |
| .wd (mio_pad_sleep_mode_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_5_gated_we; |
| assign mio_pad_sleep_mode_5_gated_we = mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_5_gated_we), |
| .wd (mio_pad_sleep_mode_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_6_gated_we; |
| assign mio_pad_sleep_mode_6_gated_we = mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_6_gated_we), |
| .wd (mio_pad_sleep_mode_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_7_gated_we; |
| assign mio_pad_sleep_mode_7_gated_we = mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_7_gated_we), |
| .wd (mio_pad_sleep_mode_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_8]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_8_gated_we; |
| assign mio_pad_sleep_mode_8_gated_we = mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_8_gated_we), |
| .wd (mio_pad_sleep_mode_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_9]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_9_gated_we; |
| assign mio_pad_sleep_mode_9_gated_we = mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_9_gated_we), |
| .wd (mio_pad_sleep_mode_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_10]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_10_gated_we; |
| assign mio_pad_sleep_mode_10_gated_we = mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_10_gated_we), |
| .wd (mio_pad_sleep_mode_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_11]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_11_gated_we; |
| assign mio_pad_sleep_mode_11_gated_we = mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_11_gated_we), |
| .wd (mio_pad_sleep_mode_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_12]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_12_gated_we; |
| assign mio_pad_sleep_mode_12_gated_we = mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_12_gated_we), |
| .wd (mio_pad_sleep_mode_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_13]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_13_gated_we; |
| assign mio_pad_sleep_mode_13_gated_we = mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_13_gated_we), |
| .wd (mio_pad_sleep_mode_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_14]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_14_gated_we; |
| assign mio_pad_sleep_mode_14_gated_we = mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_14_gated_we), |
| .wd (mio_pad_sleep_mode_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_15]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_15_gated_we; |
| assign mio_pad_sleep_mode_15_gated_we = mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_15_gated_we), |
| .wd (mio_pad_sleep_mode_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_16]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_16_gated_we; |
| assign mio_pad_sleep_mode_16_gated_we = mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_16_gated_we), |
| .wd (mio_pad_sleep_mode_16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_17]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_17_gated_we; |
| assign mio_pad_sleep_mode_17_gated_we = mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_17_gated_we), |
| .wd (mio_pad_sleep_mode_17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_18]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_18_gated_we; |
| assign mio_pad_sleep_mode_18_gated_we = mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_18_gated_we), |
| .wd (mio_pad_sleep_mode_18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_19]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_19_gated_we; |
| assign mio_pad_sleep_mode_19_gated_we = mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_19_gated_we), |
| .wd (mio_pad_sleep_mode_19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_20]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_20_gated_we; |
| assign mio_pad_sleep_mode_20_gated_we = mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_20_gated_we), |
| .wd (mio_pad_sleep_mode_20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_21]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_21_gated_we; |
| assign mio_pad_sleep_mode_21_gated_we = mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_21_gated_we), |
| .wd (mio_pad_sleep_mode_21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_22]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_22_gated_we; |
| assign mio_pad_sleep_mode_22_gated_we = mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_22_gated_we), |
| .wd (mio_pad_sleep_mode_22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_23]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_23_gated_we; |
| assign mio_pad_sleep_mode_23_gated_we = mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_23_gated_we), |
| .wd (mio_pad_sleep_mode_23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_24]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_24_gated_we; |
| assign mio_pad_sleep_mode_24_gated_we = mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_24_gated_we), |
| .wd (mio_pad_sleep_mode_24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_25]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_25_gated_we; |
| assign mio_pad_sleep_mode_25_gated_we = mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_25_gated_we), |
| .wd (mio_pad_sleep_mode_25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_26]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_26_gated_we; |
| assign mio_pad_sleep_mode_26_gated_we = mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_26_gated_we), |
| .wd (mio_pad_sleep_mode_26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_27]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_27_gated_we; |
| assign mio_pad_sleep_mode_27_gated_we = mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_27_gated_we), |
| .wd (mio_pad_sleep_mode_27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_28]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_28_gated_we; |
| assign mio_pad_sleep_mode_28_gated_we = mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_28_gated_we), |
| .wd (mio_pad_sleep_mode_28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_29]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_29_gated_we; |
| assign mio_pad_sleep_mode_29_gated_we = mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_29_gated_we), |
| .wd (mio_pad_sleep_mode_29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_30]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_30_gated_we; |
| assign mio_pad_sleep_mode_30_gated_we = mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_30_gated_we), |
| .wd (mio_pad_sleep_mode_30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[30].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg mio_pad_sleep_mode |
| // R[mio_pad_sleep_mode_31]: V(False) |
| // Create REGWEN-gated WE signal |
| logic mio_pad_sleep_mode_31_gated_we; |
| assign mio_pad_sleep_mode_31_gated_we = mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_mio_pad_sleep_mode_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (mio_pad_sleep_mode_31_gated_we), |
| .wd (mio_pad_sleep_mode_31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.mio_pad_sleep_mode[31].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (mio_pad_sleep_mode_31_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg dio_pad_sleep_status |
| // R[dio_pad_sleep_status]: V(False) |
| // F[en_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_0_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[0].de), |
| .d (hw2reg.dio_pad_sleep_status[0].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_0_qs) |
| ); |
| |
| // F[en_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_1_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[1].de), |
| .d (hw2reg.dio_pad_sleep_status[1].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_1_qs) |
| ); |
| |
| // F[en_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_2_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[2].de), |
| .d (hw2reg.dio_pad_sleep_status[2].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_2_qs) |
| ); |
| |
| // F[en_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_3_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[3].de), |
| .d (hw2reg.dio_pad_sleep_status[3].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_3_qs) |
| ); |
| |
| // F[en_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_4_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[4].de), |
| .d (hw2reg.dio_pad_sleep_status[4].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_4_qs) |
| ); |
| |
| // F[en_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_5_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[5].de), |
| .d (hw2reg.dio_pad_sleep_status[5].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_5_qs) |
| ); |
| |
| // F[en_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_6_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[6].de), |
| .d (hw2reg.dio_pad_sleep_status[6].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_6_qs) |
| ); |
| |
| // F[en_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_7_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[7].de), |
| .d (hw2reg.dio_pad_sleep_status[7].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_7_qs) |
| ); |
| |
| // F[en_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_8_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[8].de), |
| .d (hw2reg.dio_pad_sleep_status[8].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_8_qs) |
| ); |
| |
| // F[en_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_9_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[9].de), |
| .d (hw2reg.dio_pad_sleep_status[9].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_9_qs) |
| ); |
| |
| // F[en_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_10_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[10].de), |
| .d (hw2reg.dio_pad_sleep_status[10].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_10_qs) |
| ); |
| |
| // F[en_11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_11_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[11].de), |
| .d (hw2reg.dio_pad_sleep_status[11].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_11_qs) |
| ); |
| |
| // F[en_12]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_12_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[12].de), |
| .d (hw2reg.dio_pad_sleep_status[12].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_12_qs) |
| ); |
| |
| // F[en_13]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_13_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[13].de), |
| .d (hw2reg.dio_pad_sleep_status[13].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_13_qs) |
| ); |
| |
| // F[en_14]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_14_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[14].de), |
| .d (hw2reg.dio_pad_sleep_status[14].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_14_qs) |
| ); |
| |
| // F[en_15]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_status_en_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_status_we), |
| .wd (dio_pad_sleep_status_en_15_wd), |
| |
| // from internal hardware |
| .de (hw2reg.dio_pad_sleep_status[15].de), |
| .d (hw2reg.dio_pad_sleep_status[15].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_status[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_status_en_15_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_0_we), |
| .wd (dio_pad_sleep_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_1_we), |
| .wd (dio_pad_sleep_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_2_we), |
| .wd (dio_pad_sleep_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_3_we), |
| .wd (dio_pad_sleep_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_4_we), |
| .wd (dio_pad_sleep_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_5_we), |
| .wd (dio_pad_sleep_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_6_we), |
| .wd (dio_pad_sleep_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_7_we), |
| .wd (dio_pad_sleep_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_8]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_8_we), |
| .wd (dio_pad_sleep_regwen_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_9]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_9_we), |
| .wd (dio_pad_sleep_regwen_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_10]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_10_we), |
| .wd (dio_pad_sleep_regwen_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_11]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_11_we), |
| .wd (dio_pad_sleep_regwen_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_12]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_12_we), |
| .wd (dio_pad_sleep_regwen_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_13]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_13_we), |
| .wd (dio_pad_sleep_regwen_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_14]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_14_we), |
| .wd (dio_pad_sleep_regwen_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg dio_pad_sleep_regwen |
| // R[dio_pad_sleep_regwen_15]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_dio_pad_sleep_regwen_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_regwen_15_we), |
| .wd (dio_pad_sleep_regwen_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_regwen_15_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_0_gated_we; |
| assign dio_pad_sleep_en_0_gated_we = dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_0_gated_we), |
| .wd (dio_pad_sleep_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_1_gated_we; |
| assign dio_pad_sleep_en_1_gated_we = dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_1_gated_we), |
| .wd (dio_pad_sleep_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_2_gated_we; |
| assign dio_pad_sleep_en_2_gated_we = dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_2_gated_we), |
| .wd (dio_pad_sleep_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_3_gated_we; |
| assign dio_pad_sleep_en_3_gated_we = dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_3_gated_we), |
| .wd (dio_pad_sleep_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_4_gated_we; |
| assign dio_pad_sleep_en_4_gated_we = dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_4_gated_we), |
| .wd (dio_pad_sleep_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_5_gated_we; |
| assign dio_pad_sleep_en_5_gated_we = dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_5_gated_we), |
| .wd (dio_pad_sleep_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_6_gated_we; |
| assign dio_pad_sleep_en_6_gated_we = dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_6_gated_we), |
| .wd (dio_pad_sleep_en_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_7_gated_we; |
| assign dio_pad_sleep_en_7_gated_we = dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_7_gated_we), |
| .wd (dio_pad_sleep_en_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_8]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_8_gated_we; |
| assign dio_pad_sleep_en_8_gated_we = dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_8_gated_we), |
| .wd (dio_pad_sleep_en_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_9]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_9_gated_we; |
| assign dio_pad_sleep_en_9_gated_we = dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_9_gated_we), |
| .wd (dio_pad_sleep_en_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_10]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_10_gated_we; |
| assign dio_pad_sleep_en_10_gated_we = dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_10_gated_we), |
| .wd (dio_pad_sleep_en_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_11]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_11_gated_we; |
| assign dio_pad_sleep_en_11_gated_we = dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_11_gated_we), |
| .wd (dio_pad_sleep_en_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_12]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_12_gated_we; |
| assign dio_pad_sleep_en_12_gated_we = dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_12_gated_we), |
| .wd (dio_pad_sleep_en_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_13]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_13_gated_we; |
| assign dio_pad_sleep_en_13_gated_we = dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_13_gated_we), |
| .wd (dio_pad_sleep_en_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_14]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_14_gated_we; |
| assign dio_pad_sleep_en_14_gated_we = dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_14_gated_we), |
| .wd (dio_pad_sleep_en_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg dio_pad_sleep_en |
| // R[dio_pad_sleep_en_15]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_en_15_gated_we; |
| assign dio_pad_sleep_en_15_gated_we = dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_dio_pad_sleep_en_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_en_15_gated_we), |
| .wd (dio_pad_sleep_en_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_en[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_en_15_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_0_gated_we; |
| assign dio_pad_sleep_mode_0_gated_we = dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_0_gated_we), |
| .wd (dio_pad_sleep_mode_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_1_gated_we; |
| assign dio_pad_sleep_mode_1_gated_we = dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_1_gated_we), |
| .wd (dio_pad_sleep_mode_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_2_gated_we; |
| assign dio_pad_sleep_mode_2_gated_we = dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_2_gated_we), |
| .wd (dio_pad_sleep_mode_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_3_gated_we; |
| assign dio_pad_sleep_mode_3_gated_we = dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_3_gated_we), |
| .wd (dio_pad_sleep_mode_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_4_gated_we; |
| assign dio_pad_sleep_mode_4_gated_we = dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_4_gated_we), |
| .wd (dio_pad_sleep_mode_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_5_gated_we; |
| assign dio_pad_sleep_mode_5_gated_we = dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_5_gated_we), |
| .wd (dio_pad_sleep_mode_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_6_gated_we; |
| assign dio_pad_sleep_mode_6_gated_we = dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_6_gated_we), |
| .wd (dio_pad_sleep_mode_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_7]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_7_gated_we; |
| assign dio_pad_sleep_mode_7_gated_we = dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_7_gated_we), |
| .wd (dio_pad_sleep_mode_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_8]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_8_gated_we; |
| assign dio_pad_sleep_mode_8_gated_we = dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_8_gated_we), |
| .wd (dio_pad_sleep_mode_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_9]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_9_gated_we; |
| assign dio_pad_sleep_mode_9_gated_we = dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_9_gated_we), |
| .wd (dio_pad_sleep_mode_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_10]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_10_gated_we; |
| assign dio_pad_sleep_mode_10_gated_we = dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_10_gated_we), |
| .wd (dio_pad_sleep_mode_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_11]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_11_gated_we; |
| assign dio_pad_sleep_mode_11_gated_we = dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_11_gated_we), |
| .wd (dio_pad_sleep_mode_11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_12]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_12_gated_we; |
| assign dio_pad_sleep_mode_12_gated_we = dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_12_gated_we), |
| .wd (dio_pad_sleep_mode_12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_13]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_13_gated_we; |
| assign dio_pad_sleep_mode_13_gated_we = dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_13_gated_we), |
| .wd (dio_pad_sleep_mode_13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_14]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_14_gated_we; |
| assign dio_pad_sleep_mode_14_gated_we = dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_14_gated_we), |
| .wd (dio_pad_sleep_mode_14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg dio_pad_sleep_mode |
| // R[dio_pad_sleep_mode_15]: V(False) |
| // Create REGWEN-gated WE signal |
| logic dio_pad_sleep_mode_15_gated_we; |
| assign dio_pad_sleep_mode_15_gated_we = dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs; |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h2) |
| ) u_dio_pad_sleep_mode_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dio_pad_sleep_mode_15_gated_we), |
| .wd (dio_pad_sleep_mode_15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dio_pad_sleep_mode[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dio_pad_sleep_mode_15_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_0]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_0_we), |
| .wd (wkup_detector_regwen_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_1]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_1_we), |
| .wd (wkup_detector_regwen_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_2]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_2_we), |
| .wd (wkup_detector_regwen_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_3]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_3_we), |
| .wd (wkup_detector_regwen_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_4]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_4_we), |
| .wd (wkup_detector_regwen_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_5]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_5_we), |
| .wd (wkup_detector_regwen_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_6]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_6_we), |
| .wd (wkup_detector_regwen_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg wkup_detector_regwen |
| // R[wkup_detector_regwen_7]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_wkup_detector_regwen_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (wkup_detector_regwen_7_we), |
| .wd (wkup_detector_regwen_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (wkup_detector_regwen_7_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg wkup_detector_en |
| // R[wkup_detector_en_0]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_0_gated_we; |
| assign aon_wkup_detector_en_0_gated_we = |
| aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_0 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_0_gated_we), |
| .wd (aon_wkup_detector_en_0_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.wkup_detector_en[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_wkup_detector_en_0_qs_int) |
| ); |
| |
| |
| // Subregister 1 of Multireg wkup_detector_en |
| // R[wkup_detector_en_1]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_1_gated_we; |
| assign aon_wkup_detector_en_1_gated_we = |
| aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_1 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_1_gated_we), |
| .wd (aon_wkup_detector_en_1_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.wkup_detector_en[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_wkup_detector_en_1_qs_int) |
| ); |
| |
| |
| // Subregister 2 of Multireg wkup_detector_en |
| // R[wkup_detector_en_2]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_2_gated_we; |
| assign aon_wkup_detector_en_2_gated_we = |
| aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_2 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_2_gated_we), |
| .wd (aon_wkup_detector_en_2_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.wkup_detector_en[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_wkup_detector_en_2_qs_int) |
| ); |
| |
| |
| // Subregister 3 of Multireg wkup_detector_en |
| // R[wkup_detector_en_3]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_3_gated_we; |
| assign aon_wkup_detector_en_3_gated_we = |
| aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_3 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_3_gated_we), |
| .wd (aon_wkup_detector_en_3_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.wkup_detector_en[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_wkup_detector_en_3_qs_int) |
| ); |
| |
| |
| // Subregister 4 of Multireg wkup_detector_en |
| // R[wkup_detector_en_4]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_4_gated_we; |
| assign aon_wkup_detector_en_4_gated_we = |
| aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_4 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_4_gated_we), |
| .wd (aon_wkup_detector_en_4_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.wkup_detector_en[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_wkup_detector_en_4_qs_int) |
| ); |
| |
| |
| // Subregister 5 of Multireg wkup_detector_en |
| // R[wkup_detector_en_5]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_5_gated_we; |
| assign aon_wkup_detector_en_5_gated_we = |
| aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_5 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_5_gated_we), |
| .wd (aon_wkup_detector_en_5_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.wkup_detector_en[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (aon_wkup_detector_en_5_qs_int) |
| ); |
| |
| |
| // Subregister 6 of Multireg wkup_detector_en |
| // R[wkup_detector_en_6]: V(False) |
| // Create REGWEN-gated WE signal |
| logic aon_wkup_detector_en_6_gated_we; |
| assign aon_wkup_detector_en_6_gated_we = |
| aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen; |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_wkup_detector_en_6 ( |
| .clk_i (clk_aon_i), |
| .rst_ni (rst_aon_ni), |
| |
| // from register interface |
| .we (aon_wkup_detector_en_6_gated_we), |
| .wd (aon_wkup_detector_en_6_wdata[0]), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
|
