| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module i2c_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| // To HW |
| output i2c_reg_pkg::i2c_reg2hw_t reg2hw, // Write |
| input i2c_reg_pkg::i2c_hw2reg_t hw2reg, // Read |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import i2c_reg_pkg::* ; |
| |
| localparam int AW = 7; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [21:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(22) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(1) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| assign tl_reg_h2d = tl_i; |
| assign tl_o_pre = tl_reg_d2h; |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(0) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic intr_state_we; |
| logic intr_state_fmt_threshold_qs; |
| logic intr_state_fmt_threshold_wd; |
| logic intr_state_rx_threshold_qs; |
| logic intr_state_rx_threshold_wd; |
| logic intr_state_fmt_overflow_qs; |
| logic intr_state_fmt_overflow_wd; |
| logic intr_state_rx_overflow_qs; |
| logic intr_state_rx_overflow_wd; |
| logic intr_state_nak_qs; |
| logic intr_state_nak_wd; |
| logic intr_state_scl_interference_qs; |
| logic intr_state_scl_interference_wd; |
| logic intr_state_sda_interference_qs; |
| logic intr_state_sda_interference_wd; |
| logic intr_state_stretch_timeout_qs; |
| logic intr_state_stretch_timeout_wd; |
| logic intr_state_sda_unstable_qs; |
| logic intr_state_sda_unstable_wd; |
| logic intr_state_cmd_complete_qs; |
| logic intr_state_cmd_complete_wd; |
| logic intr_state_tx_stretch_qs; |
| logic intr_state_tx_overflow_qs; |
| logic intr_state_tx_overflow_wd; |
| logic intr_state_acq_full_qs; |
| logic intr_state_unexp_stop_qs; |
| logic intr_state_unexp_stop_wd; |
| logic intr_state_host_timeout_qs; |
| logic intr_state_host_timeout_wd; |
| logic intr_enable_we; |
| logic intr_enable_fmt_threshold_qs; |
| logic intr_enable_fmt_threshold_wd; |
| logic intr_enable_rx_threshold_qs; |
| logic intr_enable_rx_threshold_wd; |
| logic intr_enable_fmt_overflow_qs; |
| logic intr_enable_fmt_overflow_wd; |
| logic intr_enable_rx_overflow_qs; |
| logic intr_enable_rx_overflow_wd; |
| logic intr_enable_nak_qs; |
| logic intr_enable_nak_wd; |
| logic intr_enable_scl_interference_qs; |
| logic intr_enable_scl_interference_wd; |
| logic intr_enable_sda_interference_qs; |
| logic intr_enable_sda_interference_wd; |
| logic intr_enable_stretch_timeout_qs; |
| logic intr_enable_stretch_timeout_wd; |
| logic intr_enable_sda_unstable_qs; |
| logic intr_enable_sda_unstable_wd; |
| logic intr_enable_cmd_complete_qs; |
| logic intr_enable_cmd_complete_wd; |
| logic intr_enable_tx_stretch_qs; |
| logic intr_enable_tx_stretch_wd; |
| logic intr_enable_tx_overflow_qs; |
| logic intr_enable_tx_overflow_wd; |
| logic intr_enable_acq_full_qs; |
| logic intr_enable_acq_full_wd; |
| logic intr_enable_unexp_stop_qs; |
| logic intr_enable_unexp_stop_wd; |
| logic intr_enable_host_timeout_qs; |
| logic intr_enable_host_timeout_wd; |
| logic intr_test_we; |
| logic intr_test_fmt_threshold_wd; |
| logic intr_test_rx_threshold_wd; |
| logic intr_test_fmt_overflow_wd; |
| logic intr_test_rx_overflow_wd; |
| logic intr_test_nak_wd; |
| logic intr_test_scl_interference_wd; |
| logic intr_test_sda_interference_wd; |
| logic intr_test_stretch_timeout_wd; |
| logic intr_test_sda_unstable_wd; |
| logic intr_test_cmd_complete_wd; |
| logic intr_test_tx_stretch_wd; |
| logic intr_test_tx_overflow_wd; |
| logic intr_test_acq_full_wd; |
| logic intr_test_unexp_stop_wd; |
| logic intr_test_host_timeout_wd; |
| logic alert_test_we; |
| logic alert_test_wd; |
| logic ctrl_we; |
| logic ctrl_enablehost_qs; |
| logic ctrl_enablehost_wd; |
| logic ctrl_enabletarget_qs; |
| logic ctrl_enabletarget_wd; |
| logic ctrl_llpbk_qs; |
| logic ctrl_llpbk_wd; |
| logic status_re; |
| logic status_fmtfull_qs; |
| logic status_rxfull_qs; |
| logic status_fmtempty_qs; |
| logic status_hostidle_qs; |
| logic status_targetidle_qs; |
| logic status_rxempty_qs; |
| logic status_txfull_qs; |
| logic status_acqfull_qs; |
| logic status_txempty_qs; |
| logic status_acqempty_qs; |
| logic rdata_re; |
| logic [7:0] rdata_qs; |
| logic fdata_we; |
| logic [7:0] fdata_fbyte_wd; |
| logic fdata_start_wd; |
| logic fdata_stop_wd; |
| logic fdata_read_wd; |
| logic fdata_rcont_wd; |
| logic fdata_nakok_wd; |
| logic fifo_ctrl_we; |
| logic fifo_ctrl_rxrst_wd; |
| logic fifo_ctrl_fmtrst_wd; |
| logic [2:0] fifo_ctrl_rxilvl_qs; |
| logic [2:0] fifo_ctrl_rxilvl_wd; |
| logic [1:0] fifo_ctrl_fmtilvl_qs; |
| logic [1:0] fifo_ctrl_fmtilvl_wd; |
| logic fifo_ctrl_acqrst_wd; |
| logic fifo_ctrl_txrst_wd; |
| logic fifo_status_re; |
| logic [6:0] fifo_status_fmtlvl_qs; |
| logic [6:0] fifo_status_txlvl_qs; |
| logic [6:0] fifo_status_rxlvl_qs; |
| logic [6:0] fifo_status_acqlvl_qs; |
| logic ovrd_we; |
| logic ovrd_txovrden_qs; |
| logic ovrd_txovrden_wd; |
| logic ovrd_sclval_qs; |
| logic ovrd_sclval_wd; |
| logic ovrd_sdaval_qs; |
| logic ovrd_sdaval_wd; |
| logic val_re; |
| logic [15:0] val_scl_rx_qs; |
| logic [15:0] val_sda_rx_qs; |
| logic timing0_we; |
| logic [15:0] timing0_thigh_qs; |
| logic [15:0] timing0_thigh_wd; |
| logic [15:0] timing0_tlow_qs; |
| logic [15:0] timing0_tlow_wd; |
| logic timing1_we; |
| logic [15:0] timing1_t_r_qs; |
| logic [15:0] timing1_t_r_wd; |
| logic [15:0] timing1_t_f_qs; |
| logic [15:0] timing1_t_f_wd; |
| logic timing2_we; |
| logic [15:0] timing2_tsu_sta_qs; |
| logic [15:0] timing2_tsu_sta_wd; |
| logic [15:0] timing2_thd_sta_qs; |
| logic [15:0] timing2_thd_sta_wd; |
| logic timing3_we; |
| logic [15:0] timing3_tsu_dat_qs; |
| logic [15:0] timing3_tsu_dat_wd; |
| logic [15:0] timing3_thd_dat_qs; |
| logic [15:0] timing3_thd_dat_wd; |
| logic timing4_we; |
| logic [15:0] timing4_tsu_sto_qs; |
| logic [15:0] timing4_tsu_sto_wd; |
| logic [15:0] timing4_t_buf_qs; |
| logic [15:0] timing4_t_buf_wd; |
| logic timeout_ctrl_we; |
| logic [30:0] timeout_ctrl_val_qs; |
| logic [30:0] timeout_ctrl_val_wd; |
| logic timeout_ctrl_en_qs; |
| logic timeout_ctrl_en_wd; |
| logic target_id_we; |
| logic [6:0] target_id_address0_qs; |
| logic [6:0] target_id_address0_wd; |
| logic [6:0] target_id_mask0_qs; |
| logic [6:0] target_id_mask0_wd; |
| logic [6:0] target_id_address1_qs; |
| logic [6:0] target_id_address1_wd; |
| logic [6:0] target_id_mask1_qs; |
| logic [6:0] target_id_mask1_wd; |
| logic acqdata_re; |
| logic [7:0] acqdata_abyte_qs; |
| logic [1:0] acqdata_signal_qs; |
| logic txdata_we; |
| logic [7:0] txdata_wd; |
| logic host_timeout_ctrl_we; |
| logic [31:0] host_timeout_ctrl_qs; |
| logic [31:0] host_timeout_ctrl_wd; |
| |
| // Register instances |
| // R[intr_state]: V(False) |
| // F[fmt_threshold]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_fmt_threshold ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_fmt_threshold_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.fmt_threshold.de), |
| .d (hw2reg.intr_state.fmt_threshold.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.fmt_threshold.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_fmt_threshold_qs) |
| ); |
| |
| // F[rx_threshold]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_rx_threshold ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_rx_threshold_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.rx_threshold.de), |
| .d (hw2reg.intr_state.rx_threshold.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.rx_threshold.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_rx_threshold_qs) |
| ); |
| |
| // F[fmt_overflow]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_fmt_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_fmt_overflow_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.fmt_overflow.de), |
| .d (hw2reg.intr_state.fmt_overflow.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.fmt_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_fmt_overflow_qs) |
| ); |
| |
| // F[rx_overflow]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_rx_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_rx_overflow_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.rx_overflow.de), |
| .d (hw2reg.intr_state.rx_overflow.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.rx_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_rx_overflow_qs) |
| ); |
| |
| // F[nak]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_nak ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_nak_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.nak.de), |
| .d (hw2reg.intr_state.nak.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.nak.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_nak_qs) |
| ); |
| |
| // F[scl_interference]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_scl_interference ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_scl_interference_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.scl_interference.de), |
| .d (hw2reg.intr_state.scl_interference.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.scl_interference.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_scl_interference_qs) |
| ); |
| |
| // F[sda_interference]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_sda_interference ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_sda_interference_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.sda_interference.de), |
| .d (hw2reg.intr_state.sda_interference.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.sda_interference.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_sda_interference_qs) |
| ); |
| |
| // F[stretch_timeout]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_stretch_timeout ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_stretch_timeout_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.stretch_timeout.de), |
| .d (hw2reg.intr_state.stretch_timeout.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.stretch_timeout.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_stretch_timeout_qs) |
| ); |
| |
| // F[sda_unstable]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_sda_unstable ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_sda_unstable_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.sda_unstable.de), |
| .d (hw2reg.intr_state.sda_unstable.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.sda_unstable.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_sda_unstable_qs) |
| ); |
| |
| // F[cmd_complete]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_cmd_complete ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_cmd_complete_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.cmd_complete.de), |
| .d (hw2reg.intr_state.cmd_complete.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.cmd_complete.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_cmd_complete_qs) |
| ); |
| |
| // F[tx_stretch]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_intr_state_tx_stretch ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.tx_stretch.de), |
| .d (hw2reg.intr_state.tx_stretch.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.tx_stretch.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_tx_stretch_qs) |
| ); |
| |
| // F[tx_overflow]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_tx_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_tx_overflow_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.tx_overflow.de), |
| .d (hw2reg.intr_state.tx_overflow.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.tx_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_tx_overflow_qs) |
| ); |
| |
| // F[acq_full]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_intr_state_acq_full ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.acq_full.de), |
| .d (hw2reg.intr_state.acq_full.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.acq_full.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_acq_full_qs) |
| ); |
| |
| // F[unexp_stop]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_unexp_stop ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_unexp_stop_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.unexp_stop.de), |
| .d (hw2reg.intr_state.unexp_stop.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.unexp_stop.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_unexp_stop_qs) |
| ); |
| |
| // F[host_timeout]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_host_timeout ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_host_timeout_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.host_timeout.de), |
| .d (hw2reg.intr_state.host_timeout.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.host_timeout.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_host_timeout_qs) |
| ); |
| |
| |
| // R[intr_enable]: V(False) |
| // F[fmt_threshold]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_fmt_threshold ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_fmt_threshold_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.fmt_threshold.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_fmt_threshold_qs) |
| ); |
| |
| // F[rx_threshold]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_rx_threshold ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_rx_threshold_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.rx_threshold.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_rx_threshold_qs) |
| ); |
| |
| // F[fmt_overflow]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_fmt_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_fmt_overflow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.fmt_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_fmt_overflow_qs) |
| ); |
| |
| // F[rx_overflow]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_rx_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_rx_overflow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.rx_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_rx_overflow_qs) |
| ); |
| |
| // F[nak]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_nak ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_nak_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.nak.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_nak_qs) |
| ); |
| |
| // F[scl_interference]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_scl_interference ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_scl_interference_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.scl_interference.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_scl_interference_qs) |
| ); |
| |
| // F[sda_interference]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_sda_interference ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_sda_interference_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.sda_interference.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_sda_interference_qs) |
| ); |
| |
| // F[stretch_timeout]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_stretch_timeout ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_stretch_timeout_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.stretch_timeout.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_stretch_timeout_qs) |
| ); |
| |
| // F[sda_unstable]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_sda_unstable ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_sda_unstable_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.sda_unstable.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_sda_unstable_qs) |
| ); |
| |
| // F[cmd_complete]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_cmd_complete ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_cmd_complete_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.cmd_complete.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_cmd_complete_qs) |
| ); |
| |
| // F[tx_stretch]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_tx_stretch ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_tx_stretch_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.tx_stretch.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_tx_stretch_qs) |
| ); |
| |
| // F[tx_overflow]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_tx_overflow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_tx_overflow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.tx_overflow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_tx_overflow_qs) |
| ); |
| |
| // F[acq_full]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_acq_full ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_acq_full_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.acq_full.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_acq_full_qs) |
| ); |
| |
| // F[unexp_stop]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_unexp_stop ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_unexp_stop_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.unexp_stop.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_unexp_stop_qs) |
| ); |
| |
| // F[host_timeout]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_host_timeout ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_host_timeout_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.host_timeout.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_host_timeout_qs) |
| ); |
| |
| |
| // R[intr_test]: V(True) |
| logic intr_test_qe; |
| logic [14:0] intr_test_flds_we; |
| assign intr_test_qe = &intr_test_flds_we; |
| // F[fmt_threshold]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_fmt_threshold ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_fmt_threshold_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[0]), |
| .q (reg2hw.intr_test.fmt_threshold.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.fmt_threshold.qe = intr_test_qe; |
| |
| // F[rx_threshold]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_rx_threshold ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_rx_threshold_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[1]), |
| .q (reg2hw.intr_test.rx_threshold.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.rx_threshold.qe = intr_test_qe; |
| |
| // F[fmt_overflow]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_fmt_overflow ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_fmt_overflow_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[2]), |
| .q (reg2hw.intr_test.fmt_overflow.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.fmt_overflow.qe = intr_test_qe; |
| |
| // F[rx_overflow]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_rx_overflow ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_rx_overflow_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[3]), |
| .q (reg2hw.intr_test.rx_overflow.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.rx_overflow.qe = intr_test_qe; |
| |
| // F[nak]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_nak ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_nak_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[4]), |
| .q (reg2hw.intr_test.nak.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.nak.qe = intr_test_qe; |
| |
| // F[scl_interference]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_scl_interference ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_scl_interference_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[5]), |
| .q (reg2hw.intr_test.scl_interference.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.scl_interference.qe = intr_test_qe; |
| |
| // F[sda_interference]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_sda_interference ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_sda_interference_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[6]), |
| .q (reg2hw.intr_test.sda_interference.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.sda_interference.qe = intr_test_qe; |
| |
| // F[stretch_timeout]: 7:7 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_stretch_timeout ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_stretch_timeout_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[7]), |
| .q (reg2hw.intr_test.stretch_timeout.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.stretch_timeout.qe = intr_test_qe; |
| |
| // F[sda_unstable]: 8:8 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_sda_unstable ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_sda_unstable_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[8]), |
| .q (reg2hw.intr_test.sda_unstable.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.sda_unstable.qe = intr_test_qe; |
| |
| // F[cmd_complete]: 9:9 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_cmd_complete ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_cmd_complete_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[9]), |
| .q (reg2hw.intr_test.cmd_complete.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.cmd_complete.qe = intr_test_qe; |
| |
| // F[tx_stretch]: 10:10 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_tx_stretch ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_tx_stretch_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[10]), |
| .q (reg2hw.intr_test.tx_stretch.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.tx_stretch.qe = intr_test_qe; |
| |
| // F[tx_overflow]: 11:11 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_tx_overflow ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_tx_overflow_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[11]), |
| .q (reg2hw.intr_test.tx_overflow.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.tx_overflow.qe = intr_test_qe; |
| |
| // F[acq_full]: 12:12 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_acq_full ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_acq_full_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[12]), |
| .q (reg2hw.intr_test.acq_full.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.acq_full.qe = intr_test_qe; |
| |
| // F[unexp_stop]: 13:13 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_unexp_stop ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_unexp_stop_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[13]), |
| .q (reg2hw.intr_test.unexp_stop.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.unexp_stop.qe = intr_test_qe; |
| |
| // F[host_timeout]: 14:14 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_host_timeout ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_host_timeout_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[14]), |
| .q (reg2hw.intr_test.host_timeout.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.host_timeout.qe = intr_test_qe; |
| |
| |
| // R[alert_test]: V(True) |
| logic alert_test_qe; |
| logic [0:0] alert_test_flds_we; |
| assign alert_test_qe = &alert_test_flds_we; |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[0]), |
| .q (reg2hw.alert_test.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.qe = alert_test_qe; |
| |
| |
| // R[ctrl]: V(False) |
| // F[enablehost]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_ctrl_enablehost ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (ctrl_we), |
| .wd (ctrl_enablehost_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ctrl.enablehost.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (ctrl_enablehost_qs) |
| ); |
| |
| // F[enabletarget]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_ctrl_enabletarget ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (ctrl_we), |
| .wd (ctrl_enabletarget_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ctrl.enabletarget.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (ctrl_enabletarget_qs) |
| ); |
| |
| // F[llpbk]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_ctrl_llpbk ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (ctrl_we), |
| .wd (ctrl_llpbk_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ctrl.llpbk.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (ctrl_llpbk_qs) |
| ); |
| |
| |
| // R[status]: V(True) |
| // F[fmtfull]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_fmtfull ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.fmtfull.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_fmtfull_qs) |
| ); |
| |
| // F[rxfull]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_rxfull ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.rxfull.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_rxfull_qs) |
| ); |
| |
| // F[fmtempty]: 2:2 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_fmtempty ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.fmtempty.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_fmtempty_qs) |
| ); |
| |
| // F[hostidle]: 3:3 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_hostidle ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.hostidle.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_hostidle_qs) |
| ); |
| |
| // F[targetidle]: 4:4 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_targetidle ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.targetidle.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_targetidle_qs) |
| ); |
| |
| // F[rxempty]: 5:5 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_rxempty ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.rxempty.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_rxempty_qs) |
| ); |
| |
| // F[txfull]: 6:6 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_txfull ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.txfull.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_txfull_qs) |
| ); |
| |
| // F[acqfull]: 7:7 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_acqfull ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.acqfull.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_acqfull_qs) |
| ); |
| |
| // F[txempty]: 8:8 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_txempty ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.txempty.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_txempty_qs) |
| ); |
| |
| // F[acqempty]: 9:9 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_status_acqempty ( |
| .re (status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.status.acqempty.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (status_acqempty_qs) |
| ); |
| |
| |
| // R[rdata]: V(True) |
| prim_subreg_ext #( |
| .DW (8) |
| ) u_rdata ( |
| .re (rdata_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.rdata.d), |
| .qre (reg2hw.rdata.re), |
| .qe (), |
| .q (reg2hw.rdata.q), |
| .ds (), |
| .qs (rdata_qs) |
| ); |
| |
| |
| // R[fdata]: V(False) |
| logic fdata_qe; |
| logic [5:0] fdata_flds_we; |
| prim_flop #( |
| .Width(1), |
| .ResetValue(0) |
| ) u_fdata0_qe ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .d_i(&fdata_flds_we), |
| .q_o(fdata_qe) |
| ); |
| // F[fbyte]: 7:0 |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (8'h0) |
| ) u_fdata_fbyte ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fdata_we), |
| .wd (fdata_fbyte_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fdata_flds_we[0]), |
| .q (reg2hw.fdata.fbyte.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fdata.fbyte.qe = fdata_qe; |
| |
| // F[start]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fdata_start ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fdata_we), |
| .wd (fdata_start_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fdata_flds_we[1]), |
| .q (reg2hw.fdata.start.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fdata.start.qe = fdata_qe; |
| |
| // F[stop]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fdata_stop ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fdata_we), |
| .wd (fdata_stop_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fdata_flds_we[2]), |
| .q (reg2hw.fdata.stop.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fdata.stop.qe = fdata_qe; |
| |
| // F[read]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fdata_read ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fdata_we), |
| .wd (fdata_read_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fdata_flds_we[3]), |
| .q (reg2hw.fdata.read.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fdata.read.qe = fdata_qe; |
| |
| // F[rcont]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fdata_rcont ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fdata_we), |
| .wd (fdata_rcont_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fdata_flds_we[4]), |
| .q (reg2hw.fdata.rcont.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fdata.rcont.qe = fdata_qe; |
| |
| // F[nakok]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fdata_nakok ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fdata_we), |
| .wd (fdata_nakok_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fdata_flds_we[5]), |
| .q (reg2hw.fdata.nakok.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fdata.nakok.qe = fdata_qe; |
| |
| |
| // R[fifo_ctrl]: V(False) |
| logic fifo_ctrl_qe; |
| logic [5:0] fifo_ctrl_flds_we; |
| prim_flop #( |
| .Width(1), |
| .ResetValue(0) |
| ) u_fifo_ctrl0_qe ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .d_i(&fifo_ctrl_flds_we), |
| .q_o(fifo_ctrl_qe) |
| ); |
| // F[rxrst]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fifo_ctrl_rxrst ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_ctrl_we), |
| .wd (fifo_ctrl_rxrst_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fifo_ctrl_flds_we[0]), |
| .q (reg2hw.fifo_ctrl.rxrst.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fifo_ctrl.rxrst.qe = fifo_ctrl_qe; |
| |
| // F[fmtrst]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fifo_ctrl_fmtrst ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_ctrl_we), |
| .wd (fifo_ctrl_fmtrst_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fifo_ctrl_flds_we[1]), |
| .q (reg2hw.fifo_ctrl.fmtrst.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fifo_ctrl.fmtrst.qe = fifo_ctrl_qe; |
| |
| // F[rxilvl]: 4:2 |
| prim_subreg #( |
| .DW (3), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (3'h0) |
| ) u_fifo_ctrl_rxilvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_ctrl_we), |
| .wd (fifo_ctrl_rxilvl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fifo_ctrl_flds_we[2]), |
| .q (reg2hw.fifo_ctrl.rxilvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fifo_ctrl_rxilvl_qs) |
| ); |
| assign reg2hw.fifo_ctrl.rxilvl.qe = fifo_ctrl_qe; |
| |
| // F[fmtilvl]: 6:5 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (2'h0) |
| ) u_fifo_ctrl_fmtilvl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_ctrl_we), |
| .wd (fifo_ctrl_fmtilvl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fifo_ctrl_flds_we[3]), |
| .q (reg2hw.fifo_ctrl.fmtilvl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fifo_ctrl_fmtilvl_qs) |
| ); |
| assign reg2hw.fifo_ctrl.fmtilvl.qe = fifo_ctrl_qe; |
| |
| // F[acqrst]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fifo_ctrl_acqrst ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_ctrl_we), |
| .wd (fifo_ctrl_acqrst_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fifo_ctrl_flds_we[4]), |
| .q (reg2hw.fifo_ctrl.acqrst.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fifo_ctrl.acqrst.qe = fifo_ctrl_qe; |
| |
| // F[txrst]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_fifo_ctrl_txrst ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fifo_ctrl_we), |
| .wd (fifo_ctrl_txrst_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (fifo_ctrl_flds_we[5]), |
| .q (reg2hw.fifo_ctrl.txrst.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.fifo_ctrl.txrst.qe = fifo_ctrl_qe; |
| |
| |
| // R[fifo_status]: V(True) |
| // F[fmtlvl]: 6:0 |
| prim_subreg_ext #( |
| .DW (7) |
| ) u_fifo_status_fmtlvl ( |
| .re (fifo_status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.fifo_status.fmtlvl.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (fifo_status_fmtlvl_qs) |
| ); |
| |
| // F[txlvl]: 14:8 |
| prim_subreg_ext #( |
| .DW (7) |
| ) u_fifo_status_txlvl ( |
| .re (fifo_status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.fifo_status.txlvl.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (fifo_status_txlvl_qs) |
| ); |
| |
| // F[rxlvl]: 22:16 |
| prim_subreg_ext #( |
| .DW (7) |
| ) u_fifo_status_rxlvl ( |
| .re (fifo_status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.fifo_status.rxlvl.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (fifo_status_rxlvl_qs) |
| ); |
| |
| // F[acqlvl]: 30:24 |
| prim_subreg_ext #( |
| .DW (7) |
| ) u_fifo_status_acqlvl ( |
| .re (fifo_status_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.fifo_status.acqlvl.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (fifo_status_acqlvl_qs) |
| ); |
| |
| |
| // R[ovrd]: V(False) |
| // F[txovrden]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_ovrd_txovrden ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (ovrd_we), |
| .wd (ovrd_txovrden_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ovrd.txovrden.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (ovrd_txovrden_qs) |
| ); |
| |
| // F[sclval]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_ovrd_sclval ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (ovrd_we), |
| .wd (ovrd_sclval_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ovrd.sclval.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (ovrd_sclval_qs) |
| ); |
| |
| // F[sdaval]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_ovrd_sdaval ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (ovrd_we), |
| .wd (ovrd_sdaval_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ovrd.sdaval.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (ovrd_sdaval_qs) |
| ); |
| |
| |
| // R[val]: V(True) |
| // F[scl_rx]: 15:0 |
| prim_subreg_ext #( |
| .DW (16) |
| ) u_val_scl_rx ( |
| .re (val_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.val.scl_rx.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (val_scl_rx_qs) |
| ); |
| |
| // F[sda_rx]: 31:16 |
| prim_subreg_ext #( |
| .DW (16) |
| ) u_val_sda_rx ( |
| .re (val_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.val.sda_rx.d), |
| .qre (), |
| .qe (), |
| .q (), |
| .ds (), |
| .qs (val_sda_rx_qs) |
| ); |
| |
| |
| // R[timing0]: V(False) |
| // F[thigh]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing0_thigh ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing0_we), |
| .wd (timing0_thigh_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing0.thigh.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing0_thigh_qs) |
| ); |
| |
| // F[tlow]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing0_tlow ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing0_we), |
| .wd (timing0_tlow_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing0.tlow.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing0_tlow_qs) |
| ); |
| |
| |
| // R[timing1]: V(False) |
| // F[t_r]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing1_t_r ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing1_we), |
| .wd (timing1_t_r_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing1.t_r.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing1_t_r_qs) |
| ); |
| |
| // F[t_f]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing1_t_f ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing1_we), |
| .wd (timing1_t_f_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing1.t_f.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing1_t_f_qs) |
| ); |
| |
| |
| // R[timing2]: V(False) |
| // F[tsu_sta]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing2_tsu_sta ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing2_we), |
| .wd (timing2_tsu_sta_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing2.tsu_sta.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing2_tsu_sta_qs) |
| ); |
| |
| // F[thd_sta]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing2_thd_sta ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing2_we), |
| .wd (timing2_thd_sta_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing2.thd_sta.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing2_thd_sta_qs) |
| ); |
| |
| |
| // R[timing3]: V(False) |
| // F[tsu_dat]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing3_tsu_dat ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing3_we), |
| .wd (timing3_tsu_dat_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing3.tsu_dat.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing3_tsu_dat_qs) |
| ); |
| |
| // F[thd_dat]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing3_thd_dat ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing3_we), |
| .wd (timing3_thd_dat_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing3.thd_dat.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing3_thd_dat_qs) |
| ); |
| |
| |
| // R[timing4]: V(False) |
| // F[tsu_sto]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing4_tsu_sto ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing4_we), |
| .wd (timing4_tsu_sto_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing4.tsu_sto.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing4_tsu_sto_qs) |
| ); |
| |
| // F[t_buf]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (16'h0) |
| ) u_timing4_t_buf ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timing4_we), |
| .wd (timing4_t_buf_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timing4.t_buf.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timing4_t_buf_qs) |
| ); |
| |
| |
| // R[timeout_ctrl]: V(False) |
| // F[val]: 30:0 |
| prim_subreg #( |
| .DW (31), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (31'h0) |
| ) u_timeout_ctrl_val ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timeout_ctrl_we), |
| .wd (timeout_ctrl_val_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timeout_ctrl.val.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timeout_ctrl_val_qs) |
| ); |
| |
| // F[en]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_timeout_ctrl_en ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (timeout_ctrl_we), |
| .wd (timeout_ctrl_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.timeout_ctrl.en.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (timeout_ctrl_en_qs) |
| ); |
| |
| |
| // R[target_id]: V(False) |
| // F[address0]: 6:0 |
| prim_subreg #( |
| .DW (7), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (7'h0) |
| ) u_target_id_address0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (target_id_we), |
| .wd (target_id_address0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.target_id.address0.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (target_id_address0_qs) |
| ); |
| |
| // F[mask0]: 13:7 |
| prim_subreg #( |
| .DW (7), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (7'h0) |
| ) u_target_id_mask0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (target_id_we), |
| .wd (target_id_mask0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.target_id.mask0.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (target_id_mask0_qs) |
| ); |
| |
| // F[address1]: 20:14 |
| prim_subreg #( |
| .DW (7), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (7'h0) |
| ) u_target_id_address1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (target_id_we), |
| .wd (target_id_address1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.target_id.address1.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (target_id_address1_qs) |
| ); |
| |
| // F[mask1]: 27:21 |
| prim_subreg #( |
| .DW (7), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (7'h0) |
| ) u_target_id_mask1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (target_id_we), |
| .wd (target_id_mask1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.target_id.mask1.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (target_id_mask1_qs) |
| ); |
| |
| |
| // R[acqdata]: V(True) |
| // F[abyte]: 7:0 |
| prim_subreg_ext #( |
| .DW (8) |
| ) u_acqdata_abyte ( |
| .re (acqdata_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.acqdata.abyte.d), |
| .qre (reg2hw.acqdata.abyte.re), |
| .qe (), |
| .q (reg2hw.acqdata.abyte.q), |
| .ds (), |
| .qs (acqdata_abyte_qs) |
| ); |
| |
| // F[signal]: 9:8 |
| prim_subreg_ext #( |
| .DW (2) |
| ) u_acqdata_signal ( |
| .re (acqdata_re), |
| .we (1'b0), |
| .wd ('0), |
| .d (hw2reg.acqdata.signal.d), |
| .qre (reg2hw.acqdata.signal.re), |
| .qe (), |
| .q (reg2hw.acqdata.signal.q), |
| .ds (), |
| .qs (acqdata_signal_qs) |
| ); |
| |
| |
| // R[txdata]: V(False) |
| logic txdata_qe; |
| logic [0:0] txdata_flds_we; |
| prim_flop #( |
| .Width(1), |
| .ResetValue(0) |
| ) u_txdata0_qe ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .d_i(&txdata_flds_we), |
| .q_o(txdata_qe) |
| ); |
| prim_subreg #( |
| .DW (8), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (8'h0) |
| ) u_txdata ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (txdata_we), |
| .wd (txdata_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (txdata_flds_we[0]), |
| .q (reg2hw.txdata.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| assign reg2hw.txdata.qe = txdata_qe; |
| |
| |
| // R[host_timeout_ctrl]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (32'h0) |
| ) u_host_timeout_ctrl ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (host_timeout_ctrl_we), |
| .wd (host_timeout_ctrl_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.host_timeout_ctrl.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (host_timeout_ctrl_qs) |
| ); |
| |
| |
| |
| logic [21:0] addr_hit; |
| always_comb begin |
| addr_hit = '0; |
| addr_hit[ 0] = (reg_addr == I2C_INTR_STATE_OFFSET); |
| addr_hit[ 1] = (reg_addr == I2C_INTR_ENABLE_OFFSET); |
| addr_hit[ 2] = (reg_addr == I2C_INTR_TEST_OFFSET); |
| addr_hit[ 3] = (reg_addr == I2C_ALERT_TEST_OFFSET); |
| addr_hit[ 4] = (reg_addr == I2C_CTRL_OFFSET); |
| addr_hit[ 5] = (reg_addr == I2C_STATUS_OFFSET); |
| addr_hit[ 6] = (reg_addr == I2C_RDATA_OFFSET); |
| addr_hit[ 7] = (reg_addr == I2C_FDATA_OFFSET); |
| addr_hit[ 8] = (reg_addr == I2C_FIFO_CTRL_OFFSET); |
| addr_hit[ 9] = (reg_addr == I2C_FIFO_STATUS_OFFSET); |
| addr_hit[10] = (reg_addr == I2C_OVRD_OFFSET); |
| addr_hit[11] = (reg_addr == I2C_VAL_OFFSET); |
| addr_hit[12] = (reg_addr == I2C_TIMING0_OFFSET); |
| addr_hit[13] = (reg_addr == I2C_TIMING1_OFFSET); |
| addr_hit[14] = (reg_addr == I2C_TIMING2_OFFSET); |
| addr_hit[15] = (reg_addr == I2C_TIMING3_OFFSET); |
| addr_hit[16] = (reg_addr == I2C_TIMING4_OFFSET); |
| addr_hit[17] = (reg_addr == I2C_TIMEOUT_CTRL_OFFSET); |
| addr_hit[18] = (reg_addr == I2C_TARGET_ID_OFFSET); |
| addr_hit[19] = (reg_addr == I2C_ACQDATA_OFFSET); |
| addr_hit[20] = (reg_addr == I2C_TXDATA_OFFSET); |
| addr_hit[21] = (reg_addr == I2C_HOST_TIMEOUT_CTRL_OFFSET); |
| end |
| |
| assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; |
| |
| // Check sub-word write is permitted |
| always_comb begin |
| wr_err = (reg_we & |
| ((addr_hit[ 0] & (|(I2C_PERMIT[ 0] & ~reg_be))) | |
| (addr_hit[ 1] & (|(I2C_PERMIT[ 1] & ~reg_be))) | |
| (addr_hit[ 2] & (|(I2C_PERMIT[ 2] & ~reg_be))) | |
| (addr_hit[ 3] & (|(I2C_PERMIT[ 3] & ~reg_be))) | |
| (addr_hit[ 4] & (|(I2C_PERMIT[ 4] & ~reg_be))) | |
| (addr_hit[ 5] & (|(I2C_PERMIT[ 5] & ~reg_be))) | |
| (addr_hit[ 6] & (|(I2C_PERMIT[ 6] & ~reg_be))) | |
| (addr_hit[ 7] & (|(I2C_PERMIT[ 7] & ~reg_be))) | |
| (addr_hit[ 8] & (|(I2C_PERMIT[ 8] & ~reg_be))) | |
| (addr_hit[ 9] & (|(I2C_PERMIT[ 9] & ~reg_be))) | |
| (addr_hit[10] & (|(I2C_PERMIT[10] & ~reg_be))) | |
| (addr_hit[11] & (|(I2C_PERMIT[11] & ~reg_be))) | |
| (addr_hit[12] & (|(I2C_PERMIT[12] & ~reg_be))) | |
| (addr_hit[13] & (|(I2C_PERMIT[13] & ~reg_be))) | |
| (addr_hit[14] & (|(I2C_PERMIT[14] & ~reg_be))) | |
| (addr_hit[15] & (|(I2C_PERMIT[15] & ~reg_be))) | |
| (addr_hit[16] & (|(I2C_PERMIT[16] & ~reg_be))) | |
| (addr_hit[17] & (|(I2C_PERMIT[17] & ~reg_be))) | |
| (addr_hit[18] & (|(I2C_PERMIT[18] & ~reg_be))) | |
| (addr_hit[19] & (|(I2C_PERMIT[19] & ~reg_be))) | |
| (addr_hit[20] & (|(I2C_PERMIT[20] & ~reg_be))) | |
| (addr_hit[21] & (|(I2C_PERMIT[21] & ~reg_be))))); |
| end |
| |
| // Generate write-enables |
| assign intr_state_we = addr_hit[0] & reg_we & !reg_error; |
| |
| assign intr_state_fmt_threshold_wd = reg_wdata[0]; |
| |
| assign intr_state_rx_threshold_wd = reg_wdata[1]; |
| |
| assign intr_state_fmt_overflow_wd = reg_wdata[2]; |
| |
| assign intr_state_rx_overflow_wd = reg_wdata[3]; |
| |
| assign intr_state_nak_wd = reg_wdata[4]; |
| |
| assign intr_state_scl_interference_wd = reg_wdata[5]; |
| |
| assign intr_state_sda_interference_wd = reg_wdata[6]; |
| |
| assign intr_state_stretch_timeout_wd = reg_wdata[7]; |
| |
| assign intr_state_sda_unstable_wd = reg_wdata[8]; |
| |
| assign intr_state_cmd_complete_wd = reg_wdata[9]; |
| |
| assign intr_state_tx_overflow_wd = reg_wdata[11]; |
| |
| assign intr_state_unexp_stop_wd = reg_wdata[13]; |
| |
| assign intr_state_host_timeout_wd = reg_wdata[14]; |
| assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; |
| |
| assign intr_enable_fmt_threshold_wd = reg_wdata[0]; |
| |
| assign intr_enable_rx_threshold_wd = reg_wdata[1]; |
| |
| assign intr_enable_fmt_overflow_wd = reg_wdata[2]; |
| |
| assign intr_enable_rx_overflow_wd = reg_wdata[3]; |
| |
| assign intr_enable_nak_wd = reg_wdata[4]; |
| |
| assign intr_enable_scl_interference_wd = reg_wdata[5]; |
| |
| assign intr_enable_sda_interference_wd = reg_wdata[6]; |
| |
| assign intr_enable_stretch_timeout_wd = reg_wdata[7]; |
| |
| assign intr_enable_sda_unstable_wd = reg_wdata[8]; |
| |
| assign intr_enable_cmd_complete_wd = reg_wdata[9]; |
| |
| assign intr_enable_tx_stretch_wd = reg_wdata[10]; |
| |
| assign intr_enable_tx_overflow_wd = reg_wdata[11]; |
| |
| assign intr_enable_acq_full_wd = reg_wdata[12]; |
| |
| assign intr_enable_unexp_stop_wd = reg_wdata[13]; |
| |
| assign intr_enable_host_timeout_wd = reg_wdata[14]; |
| assign intr_test_we = addr_hit[2] & reg_we & !reg_error; |
| |
| assign intr_test_fmt_threshold_wd = reg_wdata[0]; |
| |
| assign intr_test_rx_threshold_wd = reg_wdata[1]; |
| |
| assign intr_test_fmt_overflow_wd = reg_wdata[2]; |
| |
| assign intr_test_rx_overflow_wd = reg_wdata[3]; |
| |
| assign intr_test_nak_wd = reg_wdata[4]; |
| |
| assign intr_test_scl_interference_wd = reg_wdata[5]; |
| |
| assign intr_test_sda_interference_wd = reg_wdata[6]; |
| |
| assign intr_test_stretch_timeout_wd = reg_wdata[7]; |
| |
| assign intr_test_sda_unstable_wd = reg_wdata[8]; |
| |
| assign intr_test_cmd_complete_wd = reg_wdata[9]; |
| |
| assign intr_test_tx_stretch_wd = reg_wdata[10]; |
| |
| assign intr_test_tx_overflow_wd = reg_wdata[11]; |
| |
| assign intr_test_acq_full_wd = reg_wdata[12]; |
| |
| assign intr_test_unexp_stop_wd = reg_wdata[13]; |
| |
| assign intr_test_host_timeout_wd = reg_wdata[14]; |
| assign alert_test_we = addr_hit[3] & reg_we & !reg_error; |
| |
| assign alert_test_wd = reg_wdata[0]; |
| assign ctrl_we = addr_hit[4] & reg_we & !reg_error; |
| |
| assign ctrl_enablehost_wd = reg_wdata[0]; |
| |
| assign ctrl_enabletarget_wd = reg_wdata[1]; |
| |
| assign ctrl_llpbk_wd = reg_wdata[2]; |
| assign status_re = addr_hit[5] & reg_re & !reg_error; |
| assign rdata_re = addr_hit[6] & reg_re & !reg_error; |
| assign fdata_we = addr_hit[7] & reg_we & !reg_error; |
| |
| assign fdata_fbyte_wd = reg_wdata[7:0]; |
| |
| assign fdata_start_wd = reg_wdata[8]; |
| |
| assign fdata_stop_wd = reg_wdata[9]; |
| |
| assign fdata_read_wd = reg_wdata[10]; |
| |
| assign fdata_rcont_wd = reg_wdata[11]; |
| |
| assign fdata_nakok_wd = reg_wdata[12]; |
| assign fifo_ctrl_we = addr_hit[8] & reg_we & !reg_error; |
| |
| assign fifo_ctrl_rxrst_wd = reg_wdata[0]; |
| |
| assign fifo_ctrl_fmtrst_wd = reg_wdata[1]; |
| |
| assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2]; |
| |
| assign fifo_ctrl_fmtilvl_wd = reg_wdata[6:5]; |
| |
| assign fifo_ctrl_acqrst_wd = reg_wdata[7]; |
| |
| assign fifo_ctrl_txrst_wd = reg_wdata[8]; |
| assign fifo_status_re = addr_hit[9] & reg_re & !reg_error; |
| assign ovrd_we = addr_hit[10] & reg_we & !reg_error; |
| |
| assign ovrd_txovrden_wd = reg_wdata[0]; |
| |
| assign ovrd_sclval_wd = reg_wdata[1]; |
| |
| assign ovrd_sdaval_wd = reg_wdata[2]; |
| assign val_re = addr_hit[11] & reg_re & !reg_error; |
| assign timing0_we = addr_hit[12] & reg_we & !reg_error; |
| |
| assign timing0_thigh_wd = reg_wdata[15:0]; |
| |
| assign timing0_tlow_wd = reg_wdata[31:16]; |
| assign timing1_we = addr_hit[13] & reg_we & !reg_error; |
| |
| assign timing1_t_r_wd = reg_wdata[15:0]; |
| |
| assign timing1_t_f_wd = reg_wdata[31:16]; |
| assign timing2_we = addr_hit[14] & reg_we & !reg_error; |
| |
| assign timing2_tsu_sta_wd = reg_wdata[15:0]; |
| |
| assign timing2_thd_sta_wd = reg_wdata[31:16]; |
| assign timing3_we = addr_hit[15] & reg_we & !reg_error; |
| |
| assign timing3_tsu_dat_wd = reg_wdata[15:0]; |
| |
| assign timing3_thd_dat_wd = reg_wdata[31:16]; |
| assign timing4_we = addr_hit[16] & reg_we & !reg_error; |
| |
| assign timing4_tsu_sto_wd = reg_wdata[15:0]; |
| |
| assign timing4_t_buf_wd = reg_wdata[31:16]; |
| assign timeout_ctrl_we = addr_hit[17] & reg_we & !reg_error; |
| |
| assign timeout_ctrl_val_wd = reg_wdata[30:0]; |
| |
| assign timeout_ctrl_en_wd = reg_wdata[31]; |
| assign target_id_we = addr_hit[18] & reg_we & !reg_error; |
| |
| assign target_id_address0_wd = reg_wdata[6:0]; |
| |
| assign target_id_mask0_wd = reg_wdata[13:7]; |
| |
| assign target_id_address1_wd = reg_wdata[20:14]; |
| |
| assign target_id_mask1_wd = reg_wdata[27:21]; |
| assign acqdata_re = addr_hit[19] & reg_re & !reg_error; |
| assign txdata_we = addr_hit[20] & reg_we & !reg_error; |
| |
| assign txdata_wd = reg_wdata[7:0]; |
| assign host_timeout_ctrl_we = addr_hit[21] & reg_we & !reg_error; |
| |
| assign host_timeout_ctrl_wd = reg_wdata[31:0]; |
| |
| // Assign write-enables to checker logic vector. |
| always_comb begin |
| reg_we_check = '0; |
| reg_we_check[0] = intr_state_we; |
| reg_we_check[1] = intr_enable_we; |
| reg_we_check[2] = intr_test_we; |
| reg_we_check[3] = alert_test_we; |
| reg_we_check[4] = ctrl_we; |
| reg_we_check[5] = 1'b0; |
| reg_we_check[6] = 1'b0; |
| reg_we_check[7] = fdata_we; |
| reg_we_check[8] = fifo_ctrl_we; |
| reg_we_check[9] = 1'b0; |
| reg_we_check[10] = ovrd_we; |
| reg_we_check[11] = 1'b0; |
| reg_we_check[12] = timing0_we; |
| reg_we_check[13] = timing1_we; |
| reg_we_check[14] = timing2_we; |
| reg_we_check[15] = timing3_we; |
| reg_we_check[16] = timing4_we; |
| reg_we_check[17] = timeout_ctrl_we; |
| reg_we_check[18] = target_id_we; |
| reg_we_check[19] = 1'b0; |
| reg_we_check[20] = txdata_we; |
| reg_we_check[21] = host_timeout_ctrl_we; |
| end |
| |
| // Read data return |
| always_comb begin |
| reg_rdata_next = '0; |
| unique case (1'b1) |
| addr_hit[0]: begin |
| reg_rdata_next[0] = intr_state_fmt_threshold_qs; |
| reg_rdata_next[1] = intr_state_rx_threshold_qs; |
| reg_rdata_next[2] = intr_state_fmt_overflow_qs; |
| reg_rdata_next[3] = intr_state_rx_overflow_qs; |
| reg_rdata_next[4] = intr_state_nak_qs; |
| reg_rdata_next[5] = intr_state_scl_interference_qs; |
| reg_rdata_next[6] = intr_state_sda_interference_qs; |
| reg_rdata_next[7] = intr_state_stretch_timeout_qs; |
| reg_rdata_next[8] = intr_state_sda_unstable_qs; |
| reg_rdata_next[9] = intr_state_cmd_complete_qs; |
| reg_rdata_next[10] = intr_state_tx_stretch_qs; |
| reg_rdata_next[11] = intr_state_tx_overflow_qs; |
| reg_rdata_next[12] = intr_state_acq_full_qs; |
| reg_rdata_next[13] = intr_state_unexp_stop_qs; |
| reg_rdata_next[14] = intr_state_host_timeout_qs; |
| end |
| |
| addr_hit[1]: begin |
| reg_rdata_next[0] = intr_enable_fmt_threshold_qs; |
| reg_rdata_next[1] = intr_enable_rx_threshold_qs; |
| reg_rdata_next[2] = intr_enable_fmt_overflow_qs; |
| reg_rdata_next[3] = intr_enable_rx_overflow_qs; |
| reg_rdata_next[4] = intr_enable_nak_qs; |
| reg_rdata_next[5] = intr_enable_scl_interference_qs; |
| reg_rdata_next[6] = intr_enable_sda_interference_qs; |
| reg_rdata_next[7] = intr_enable_stretch_timeout_qs; |
| reg_rdata_next[8] = intr_enable_sda_unstable_qs; |
| reg_rdata_next[9] = intr_enable_cmd_complete_qs; |
| reg_rdata_next[10] = intr_enable_tx_stretch_qs; |
| reg_rdata_next[11] = intr_enable_tx_overflow_qs; |
| reg_rdata_next[12] = intr_enable_acq_full_qs; |
| reg_rdata_next[13] = intr_enable_unexp_stop_qs; |
| reg_rdata_next[14] = intr_enable_host_timeout_qs; |
| end |
| |
| addr_hit[2]: begin |
| reg_rdata_next[0] = '0; |
| reg_rdata_next[1] = '0; |
| reg_rdata_next[2] = '0; |
| reg_rdata_next[3] = '0; |
| reg_rdata_next[4] = '0; |
| reg_rdata_next[5] = '0; |
| reg_rdata_next[6] = '0; |
| reg_rdata_next[7] = '0; |
| reg_rdata_next[8] = '0; |
| reg_rdata_next[9] = '0; |
| reg_rdata_next[10] = '0; |
| reg_rdata_next[11] = '0; |
| reg_rdata_next[12] = '0; |
| reg_rdata_next[13] = '0; |
| reg_rdata_next[14] = '0; |
| end |
| |
| addr_hit[3]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[4]: begin |
| reg_rdata_next[0] = ctrl_enablehost_qs; |
| reg_rdata_next[1] = ctrl_enabletarget_qs; |
| reg_rdata_next[2] = ctrl_llpbk_qs; |
| end |
| |
| addr_hit[5]: begin |
| reg_rdata_next[0] = status_fmtfull_qs; |
| reg_rdata_next[1] = status_rxfull_qs; |
| reg_rdata_next[2] = status_fmtempty_qs; |
| reg_rdata_next[3] = status_hostidle_qs; |
| reg_rdata_next[4] = status_targetidle_qs; |
| reg_rdata_next[5] = status_rxempty_qs; |
| reg_rdata_next[6] = status_txfull_qs; |
| reg_rdata_next[7] = status_acqfull_qs; |
| reg_rdata_next[8] = status_txempty_qs; |
| reg_rdata_next[9] = status_acqempty_qs; |
| end |
| |
| addr_hit[6]: begin |
| reg_rdata_next[7:0] = rdata_qs; |
| end |
| |
| addr_hit[7]: begin |
| reg_rdata_next[7:0] = '0; |
| reg_rdata_next[8] = '0; |
| reg_rdata_next[9] = '0; |
| reg_rdata_next[10] = '0; |
| reg_rdata_next[11] = '0; |
| reg_rdata_next[12] = '0; |
| end |
| |
| addr_hit[8]: begin |
| reg_rdata_next[0] = '0; |
| reg_rdata_next[1] = '0; |
| reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs; |
| reg_rdata_next[6:5] = fifo_ctrl_fmtilvl_qs; |
| reg_rdata_next[7] = '0; |
| reg_rdata_next[8] = '0; |
| end |
| |
| addr_hit[9]: begin |
| reg_rdata_next[6:0] = fifo_status_fmtlvl_qs; |
| reg_rdata_next[14:8] = fifo_status_txlvl_qs; |
| reg_rdata_next[22:16] = fifo_status_rxlvl_qs; |
| reg_rdata_next[30:24] = fifo_status_acqlvl_qs; |
| end |
| |
| addr_hit[10]: begin |
| reg_rdata_next[0] = ovrd_txovrden_qs; |
| reg_rdata_next[1] = ovrd_sclval_qs; |
| reg_rdata_next[2] = ovrd_sdaval_qs; |
| end |
| |
| addr_hit[11]: begin |
| reg_rdata_next[15:0] = val_scl_rx_qs; |
| reg_rdata_next[31:16] = val_sda_rx_qs; |
| end |
| |
| addr_hit[12]: begin |
| reg_rdata_next[15:0] = timing0_thigh_qs; |
| reg_rdata_next[31:16] = timing0_tlow_qs; |
| end |
| |
| addr_hit[13]: begin |
| reg_rdata_next[15:0] = timing1_t_r_qs; |
| reg_rdata_next[31:16] = timing1_t_f_qs; |
| end |
| |
| addr_hit[14]: begin |
| reg_rdata_next[15:0] = timing2_tsu_sta_qs; |
| reg_rdata_next[31:16] = timing2_thd_sta_qs; |
| end |
| |
| addr_hit[15]: begin |
| reg_rdata_next[15:0] = timing3_tsu_dat_qs; |
| reg_rdata_next[31:16] = timing3_thd_dat_qs; |
| end |
| |
| addr_hit[16]: begin |
| reg_rdata_next[15:0] = timing4_tsu_sto_qs; |
| reg_rdata_next[31:16] = timing4_t_buf_qs; |
| end |
| |
| addr_hit[17]: begin |
| reg_rdata_next[30:0] = timeout_ctrl_val_qs; |
| reg_rdata_next[31] = timeout_ctrl_en_qs; |
| end |
| |
| addr_hit[18]: begin |
| reg_rdata_next[6:0] = target_id_address0_qs; |
| reg_rdata_next[13:7] = target_id_mask0_qs; |
| reg_rdata_next[20:14] = target_id_address1_qs; |
| reg_rdata_next[27:21] = target_id_mask1_qs; |
| end |
| |
| addr_hit[19]: begin |
| reg_rdata_next[7:0] = acqdata_abyte_qs; |
| reg_rdata_next[9:8] = acqdata_signal_qs; |
| end |
| |
| addr_hit[20]: begin |
| reg_rdata_next[7:0] = '0; |
| end |
| |
| addr_hit[21]: begin |
| reg_rdata_next[31:0] = host_timeout_ctrl_qs; |
| end |
| |
| default: begin |
| reg_rdata_next = '1; |
| end |
| endcase |
| end |
| |
| // shadow busy |
| logic shadow_busy; |
| assign shadow_busy = 1'b0; |
| |
| // register busy |
| assign reg_busy = shadow_busy; |
| |
| // Unused signal tieoff |
| |
| // wdata / byte enable are not always fully used |
| // add a blanket unused statement to handle lint waivers |
| logic unused_wdata; |
| logic unused_be; |
| assign unused_wdata = ^reg_wdata; |
| assign unused_be = ^reg_be; |
| |
| // Assertions for Register Interface |
| `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) |
| `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) |
| |
| `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) |
| |
| `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) |
| |
| // this is formulated as an assumption such that the FPV testbenches do disprove this |
| // property by mistake |
| //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) |
| |
| endmodule |
