diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 172981e..a4395c3 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -579,6 +579,13 @@
           type: "req_rsp"
           act: "rsp"
           name: "tl"
+        },
+        // Interface to memory configuration
+        { struct:  "rom_cfg",
+          package: "prim_rom_pkg",
+          type:    "uni",
+          name:    "cfg",
+          act:     "rcv"
         }
       ]
     },
@@ -619,6 +626,13 @@
           name:    "intg_error",
           act:     "req",
         },
+        // Interface to memory configuration
+        { struct:  "ram_1p_cfg",
+          package: "prim_ram_1p_pkg",
+          type:    "uni",
+          name:    "cfg",
+          act:     "rcv"
+        }
       ]
     },
     { name: "ram_ret_aon",
@@ -659,6 +673,13 @@
           name:    "intg_error",
           act:     "req",
         },
+        // Interface to memory configuration
+        { struct:  "ram_1p_cfg",
+          package: "prim_ram_1p_pkg",
+          type:    "uni",
+          name:    "cfg",
+          act:     "rcv"
+        }
       ]
     },
     { name: "eflash",
@@ -729,7 +750,7 @@
   // For example, this allows us to designate a port as part of inter-module
   // connections.
   port: [
-    { name: "ast_edn",
+    { name: "ast",
       inter_signal_list: [
         { struct: "edn",
           type: "req_rsp",
@@ -739,6 +760,42 @@
           act:  "rsp",
           package: "edn_pkg",
         },
+
+        { struct: "lc_tx",
+          type: "uni",
+          name: "lc_dft_en",
+          // The activity direction for a port inter-signal is "opposite" of
+          // what the external module actually needs.
+          act:  "req",
+          package: "lc_ctrl_pkg",
+        },
+
+        { struct:  "ram_1p_cfg",
+          package: "prim_ram_1p_pkg",
+          type:    "uni",
+          name:    "ram_1p_cfg",
+          // The activity direction for a port inter-signal is "opposite" of
+          // what the external module actually needs.
+          act:     "rcv"
+        },
+
+        { struct:  "ram_2p_cfg",
+          package: "prim_ram_2p_pkg",
+          type:    "uni",
+          name:    "ram_2p_cfg",
+          // The activity direction for a port inter-signal is "opposite" of
+          // what the external module actually needs.
+          act:     "rcv"
+        },
+
+        { struct:  "rom_cfg",
+          package: "prim_rom_pkg",
+          type:    "uni",
+          name:    "rom_cfg",
+          // The activity direction for a port inter-signal is "opposite" of
+          // what the external module actually needs.
+          act:     "rcv"
+        }
       ]
     },
   ]
@@ -751,6 +808,9 @@
   //  e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
   inter_module: {
     'connect': {
+      'ast.ram_1p_cfg'          : ['otbn.ram_cfg', 'ram_main.cfg', 'ram_ret_aon.cfg'],
+      'ast.ram_2p_cfg'          : ['spi_device.ram_cfg', 'usbdev.ram_cfg'],
+      'ast.rom_cfg'             : ['rom.cfg'],
       'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
       'alert_handler.esc_rx'    : ['rv_core_ibex.esc_nmi_rx',
                                    'lc_ctrl.esc_wipe_secrets_rx',
@@ -796,7 +856,7 @@
       'pinmux_aon.usb_state_debug' : ['usbdev.usb_state_debug'],
 
       // Edn connections
-      'edn0.edn'              : ['keymgr.edn', 'otp_ctrl.edn', 'ast_edn.edn', 'kmac.entropy',
+      'edn0.edn'              : ['keymgr.edn', 'otp_ctrl.edn', 'ast.edn', 'kmac.entropy',
                                  'alert_handler.edn', 'aes.edn', 'otbn.edn_urnd'],
       'edn1.edn'              : ['otbn.edn_rnd'],
 
@@ -830,7 +890,9 @@
 
       // LC function control signal broadcast
       'lc_ctrl.lc_dft_en'          : ['otp_ctrl.lc_dft_en',
-                                      'pinmux_aon.lc_dft_en'],
+                                      'pinmux_aon.lc_dft_en',
+                                      'ast.lc_dft_en'
+                                     ],
       'lc_ctrl.lc_nvm_debug_en'    : ['eflash.lc_nvm_debug_en'],
       'lc_ctrl.lc_hw_debug_en'     : ['sram_ctrl_main.lc_hw_debug_en',
                                       'sram_ctrl_ret_aon.lc_hw_debug_en',
@@ -868,19 +930,17 @@
 
     // ext is to create port in the top.
     'external': {
-       'clkmgr_aon.clk_main'           : 'clk_main',  // clock inputs
+        'ast.edn'                      : '',
+        'ast.lc_dft_en'                : '',
+        'ast.ram_1p_cfg'               : 'ram_1p_cfg',
+        'ast.ram_2p_cfg'               : 'ram_2p_cfg',
+        'ast.rom_cfg'                  : 'rom_cfg',
+        'clkmgr_aon.clk_main'          : 'clk_main',  // clock inputs
         'clkmgr_aon.clk_io'            : 'clk_io',    // clock inputs
         'clkmgr_aon.clk_usb'           : 'clk_usb',   // clock inputs
         'clkmgr_aon.clk_aon'           : 'clk_aon',   // clock inputs
         'clkmgr_aon.jitter_en'         : 'clk_main_jitter_en',
-        'pwrmgr_aon.pwr_ast'           : 'pwrmgr_ast',
-        'sensor_ctrl_aon.ast_alert'    : 'sensor_ctrl_ast_alert',
-        'sensor_ctrl_aon.ast_status'   : 'sensor_ctrl_ast_status',
-        'usbdev.usb_ref_val'           : '',
-        'usbdev.usb_ref_pulse'         : '',
-        'peri.tl_ast'                  : 'ast_tl',
-        'otp_ctrl.otp_ast_pwr_seq'     : '',
-        'otp_ctrl.otp_ast_pwr_seq_h'   : '',
+        'clkmgr_aon.ast_clk_bypass_ack': 'lc_clk_byp_ack',
         'eflash.flash_bist_enable'     : 'flash_bist_enable',
         'eflash.flash_power_down_h'    : 'flash_power_down_h',
         'eflash.flash_power_ready_h'   : 'flash_power_ready_h',
@@ -888,8 +948,17 @@
         'eflash.flash_test_voltage_h'  : 'flash_test_voltage_h',
         'entropy_src.entropy_src_rng'  : 'es_rng',
         'lc_ctrl.lc_clk_byp_req'       : 'lc_clk_byp_req',
-        'clkmgr_aon.ast_clk_bypass_ack': 'lc_clk_byp_ack',
-        'ast_edn.edn'                  : ''
+        'peri.tl_ast'                  : 'ast_tl',
+        'pinmux_aon.dft_strap_test'    : 'dft_strap_test'
+        'pwrmgr_aon.pwr_ast'           : 'pwrmgr_ast',
+        'otp_ctrl.otp_ast_pwr_seq'     : '',
+        'otp_ctrl.otp_ast_pwr_seq_h'   : '',
+        'sensor_ctrl_aon.ast_alert'    : 'sensor_ctrl_ast_alert',
+        'sensor_ctrl_aon.ast_status'   : 'sensor_ctrl_ast_status',
+        'sensor_ctrl_aon.pinmux2ast'   : 'pinmux2ast',
+        'sensor_ctrl_aon.ast2pinmux'   : 'ast2pinmux',
+        'usbdev.usb_ref_val'           : '',
+        'usbdev.usb_ref_pulse'         : '',
     },
   },
 
@@ -944,7 +1013,7 @@
     //  module list except defined in `dio_modules`.
     mio_modules: ["gpio", "uart0", "uart1", "uart2", "uart3",
                   "i2c0", "i2c1", "i2c2", "pattgen", "spi_host1",
-                  "flash_ctrl"]
+                  "flash_ctrl", "sensor_ctrl_aon"]
 
     // If any module isn't defined in above two lists, its inputs will be tied
     //  to 0, and the output/OE signals will be floating (or connected to