)]}'
{
  "commit": "681f48ad85bb53a2ed1f112ee25e27dcf4f411c8",
  "tree": "ed2f3f43dc9870d0652feeb84dd38ff543f3cb33",
  "parents": [
    "231d0d0ff9c31707dddb402004683a18516f90e4"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Thu Aug 06 20:19:03 2020 -0700"
  },
  "committer": {
    "name": "sriyerg",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Fri Aug 07 11:25:23 2020 -0700"
  },
  "message": "[dvsim] Allow testplan to be omitted\n\nIn the current implementation, `dvsim` makes it necessary to provide a\ntestplan, otherwise it results in errors being thrown.\n\nThis patch fixes that and allows testplan to be completely omitted. The\ntests in that case appear as \u0027Unmapped Tests\u0027 in the final results\ntable. This is useful for DUTs such as `prim_lfsr` and `prim_present`.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0ccf3444d551ba4555fcbde9119f08ed0a851ee3",
      "old_mode": 33188,
      "old_path": "util/dvsim/SimCfg.py",
      "new_id": "2bf439b7fd0dff535454562695d2de2caa963cdc",
      "new_mode": 33188,
      "new_path": "util/dvsim/SimCfg.py"
    },
    {
      "type": "modify",
      "old_id": "ee84e7e521ba3233d1540ecdd8377e243c52c77d",
      "old_mode": 33188,
      "old_path": "util/dvsim/testplanner/class_defs.py",
      "new_id": "1c2011ae5acf14f58aecb430ea463efd1946abbf",
      "new_mode": 33188,
      "new_path": "util/dvsim/testplanner/class_defs.py"
    }
  ]
}