tree 235896da543c84369eb41b3090cce634245174dc
parent 62bdf5b03f43ce08935c737deadc3e0f4034eb88
author Rupert Swarbrick <rswarbrick@lowrisc.org> 1629996999 +0100
committer Rupert Swarbrick <rswarbrick@gmail.com> 1630427356 +0100

[otbn,dv] Add loop warping support to UVM environment

This is analogous to the previous commit (which added support to the
Verilator-based environment), but can use uvm_hdl_deposit to force
signals, which allows us to do the forcing in SystemVerilog, rather
than having to grub around in C++.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>