diff --git a/util/reggen/reg_pkg.sv.tpl b/util/reggen/reg_pkg.sv.tpl
index 8f5bd95..91c88c1 100644
--- a/util/reggen/reg_pkg.sv.tpl
+++ b/util/reggen/reg_pkg.sv.tpl
@@ -5,6 +5,7 @@
 // Register Package auto-generated by `reggen` containing data structure
 
 <%
+  from topgen import lib # TODO: Split lib to common lib module
   num_regs = block.get_n_regs_flat()
   max_regs_char = len("{}".format(num_regs-1))
 %>\
@@ -17,170 +18,127 @@
   localparam ${param["type"]} ${param["name"]} = ${param["default"]};
 % endfor
 
-% if block.contains_multiregs():
-////////////////////////////
-// Typedefs for multiregs //
-////////////////////////////
-
+  ////////////////////////////
+  // Typedefs for registers //
+  ////////////////////////////
 % for r in block.regs:
   ## in this case we have a homogeneous multireg, with only one replicated field
-  % if r.is_multi_reg() and r.get_n_bits(["q"]) and r.ishomog:
-typedef struct packed {
-  logic [${r.get_field_flat(0).get_n_bits()-1}:0] q;
-  % if r.get_field_flat(0).hwqe:
-  logic qe;
-  % endif
-  % if r.get_field_flat(0).hwre:
-  logic re;
-  % endif
-} ${block.name + "_reg2hw_" + r.name + "_mreg_t"};
+  % if r.get_n_bits(["q"]) and r.ishomog:
+  typedef struct packed {
+    logic ${lib.bitarray(r.get_field_flat(0).get_n_bits(["q"]),2)} q;
+    % if r.get_field_flat(0).hwqe:
+    logic        qe;
+    % endif
+    % if r.get_field_flat(0).hwre:
+    logic        re;
+    % endif
+  } ${block.name + "_reg2hw_" + r.name + ("_mreg_t" if r.is_multi_reg() else "_reg_t")};
+
   ## in this case we have an inhomogeneous multireg, with several different fields per register
-  % elif r.is_multi_reg() and r.get_n_bits(["q"]) and not r.ishomog:
-typedef struct packed {
+  % elif r.get_n_bits(["q"]) and not r.ishomog:
+  typedef struct packed {
     % for f in r.get_reg_flat(0).fields:
-  struct packed {
-    logic [${f.get_n_bits()-1}:0] q;
+      % if f.get_n_bits(["q"]) >= 1:
+    struct packed {
+      logic ${lib.bitarray(f.get_n_bits(["q"]),2)} q;
       % if f.hwqe:
-    logic qe;
+      logic        qe;
       % endif
       % if f.hwre:
-    logic re;
+      logic        re;
       % endif
-  } ${f.get_basename()};
+    } ${f.get_basename() if r.is_multi_reg() else f.name};
+      %endif
     %endfor
-} ${block.name + "_reg2hw_" + r.name + "_mreg_t"};
+  } ${block.name + "_reg2hw_" + r.name + ("_mreg_t" if r.is_multi_reg() else "_reg_t")};
+
   %endif
 % endfor
 
 % for r in block.regs:
  ## in this case we have a homogeneous multireg, with only one replicated field
-  % if r.is_multi_reg() and r.get_n_bits(["d"]) and r.ishomog:
-typedef struct packed {
-  logic [${r.get_field_flat(0).get_n_bits(["d"])-1}:0] d;
+  % if r.get_n_bits(["d"]) and r.ishomog:
+  typedef struct packed {
+    logic ${lib.bitarray(r.get_field_flat(0).get_n_bits(["d"]),2)} d;
     % if not r.get_reg_flat(0).hwext:
-  logic de;
+    logic        de;
     % endif
-} ${block.name + "_hw2reg_" + r.name + "_mreg_t"};
+  } ${block.name + "_hw2reg_" + r.name + ("_mreg_t" if r.is_multi_reg() else "_reg_t")};
+
   ## in this case we have an inhomogeneous multireg, with several different fields per register
-  % elif r.is_multi_reg() and r.get_n_bits(["d"]) and not r.ishomog:
-typedef struct packed {
+  % elif r.get_n_bits(["d"]) and not r.ishomog:
+  typedef struct packed {
     % for f in r.get_reg_flat(0).fields:
-  struct packed {
-    logic [${f.get_n_bits(["d"])-1}:0] d;
+      % if f.get_n_bits(["d"]) >= 1:
+    struct packed {
+      logic ${lib.bitarray(f.get_n_bits(["d"]),2)} d;
       % if not r.hwext:
-    logic de;
+      logic        de;
       % endif
-  } ${f.get_basename()};
+    } ${f.get_basename() if r.is_multi_reg() else f.name};
+      %endif
     %endfor
-} ${block.name + "_hw2reg_" + r.name + "_mreg_t"};
+  } ${block.name + "_hw2reg_" + r.name + ("_mreg_t" if r.is_multi_reg() else "_reg_t")};
+
   % endif
 % endfor
 
-% endif
-///////////////////////////////////////
-// Register to internal design logic //
-///////////////////////////////////////
+  ///////////////////////////////////////
+  // Register to internal design logic //
+  ///////////////////////////////////////
 <%
 nbits = block.get_n_bits(["q","qe","re"]) - 1
 packbit = 0
-%>
+%>\
 % if nbits > 0:
-typedef struct packed {
+  typedef struct packed {
 % for r in block.regs:
   ######################## multiregister ###########################
   % if r.is_multi_reg() and r.get_n_bits(["q"]):
-  <%
+<%
   array_dims = ""
   for d in r.get_nested_dims():
     array_dims += "[%d:0]" % (d-1)
-  %>${block.name + "_reg2hw_" + r.name + "_mreg_t"} ${array_dims} ${r.name}; // [${nbits - packbit}:${nbits - (packbit + r.get_n_bits(["q", "qe", "re"]) - 1)}]<% packbit += r.get_n_bits(["q", "qe", "re"]) %>
-  ######################## register with single field ###########################
-  % elif len(r.fields) == 1 and r.get_n_bits(["q"]):
+%>\
+    ${block.name + "_reg2hw_" + r.name + "_mreg_t"} ${array_dims} ${r.name}; // [${nbits - packbit}:${nbits - (packbit + r.get_n_bits(["q", "qe", "re"]) - 1)}]<% packbit += r.get_n_bits(["q", "qe", "re"]) %>\
+
+  ######################## register ###########################
+  % elif r.get_n_bits(["q"]):
     ## Only one field, should use register name as it is
-  struct packed {
-    logic [${r.fields[0].get_n_bits()-1}:0] q; // [${nbits - packbit}:${nbits - (packbit + r.fields[0].get_n_bits() - 1)}]<% packbit += r.fields[0].get_n_bits() %>
-    % if r.fields[0].hwqe:
-    logic qe; // [${nbits - packbit}]<% packbit += 1 %>
-    % endif
-    % if r.fields[0].hwre:
-    logic re; // [${nbits - packbit}]<% packbit += 1 %>
-    % endif
-  } ${r.name};
-  ######################## register with multiple fields ###########################
-  % elif len(r.fields) >= 2 and r.get_n_bits(["q"]):
-  struct packed {
-    % for f in r.fields:
-      % if f.hwaccess in [HwAccess.HRW, HwAccess.HRO]:
-    struct packed {
-      ## reg2hw signal based on HW type and virtual?
-      % if f.get_n_bits() > 1:
-      logic [${f.get_n_bits()-1}:0] q; // [${nbits - packbit}:${nbits - (packbit + f.get_n_bits() - 1)}]<% packbit += f.get_n_bits() %>
-      % else:
-      logic q; // [${nbits - packbit}]<% packbit += 1 %>
-      % endif
-      % if f.hwqe:
-      logic qe; // [${nbits - packbit}]<% packbit += 1 %>
-      % endif
-      % if f.hwre:
-      logic re; // [${nbits - packbit}]<% packbit += 1 %>
-      % endif
-    } ${f.name};
-      % endif
-    % endfor
-  } ${r.name};
+    ${block.name + "_reg2hw_" + r.name + "_reg_t"} ${r.name}; // [${nbits - packbit}:${nbits - (packbit + r.get_n_bits(["q", "qe", "re"]) - 1)}]<% packbit += r.get_n_bits(["q", "qe", "re"]) %>\
+
   % endif
 % endfor
-} ${block.name}_reg2hw_t;
+  } ${block.name}_reg2hw_t;
 % endif
 
-///////////////////////////////////////
-// Internal design logic to register //
-///////////////////////////////////////
+  ///////////////////////////////////////
+  // Internal design logic to register //
+  ///////////////////////////////////////
 <%
 nbits = block.get_n_bits(["d","de"]) - 1
 packbit = 0
-%>
+%>\
 % if nbits > 0:
-typedef struct packed {
+  typedef struct packed {
 % for r in block.regs:
   ######################## multiregister ###########################
   % if r.is_multi_reg() and r.get_n_bits(["d"]):
-  <%
+<%
   array_dims = ""
   for d in r.get_nested_dims():
     array_dims += "[%d:0]" % (d-1)
-  %>${block.name + "_hw2reg_" + r.name + "_mreg_t"} ${array_dims} ${r.name}; // [${nbits - packbit}:${nbits - (packbit + r.get_n_bits(["d", "de"]) - 1)}]<% packbit += r.get_n_bits(["d", "de"]) %>
+%>\
+    ${block.name + "_hw2reg_" + r.name + "_mreg_t"} ${array_dims} ${r.name}; // [${nbits - packbit}:${nbits - (packbit + r.get_n_bits(["d", "de"]) - 1)}]<% packbit += r.get_n_bits(["d", "de"]) %>\
+
   ######################## register with single field ###########################
-  % elif len(r.fields) == 1 and r.get_n_bits(["d"]):
+  % elif r.get_n_bits(["d"]):
     ## Only one field, should use register name as it is
-  struct packed {
-    logic [${r.fields[0].get_n_bits("d")-1}:0] d; // [${nbits - packbit}:${nbits - (packbit + r.fields[0].get_n_bits("d") - 1)}]<% packbit += r.fields[0].get_n_bits("d") %>
-    % if r.hwext == 0:
-    logic de; // [${nbits - packbit}]<% packbit += 1 %>
-    % endif
-  } ${r.name};
-  ######################## register with multiple fields ###########################
-  % elif len(r.fields) >= 2 and r.get_n_bits(["d"]):
-  struct packed {
-    % for f in r.fields:
-      % if f.hwaccess in [HwAccess.HRW, HwAccess.HWO]:
-    struct packed {
-      ## reg2hw signal based on HW type and virtual?
-      % if f.get_n_bits("d") > 1:
-      logic [${f.get_n_bits("d")-1}:0] d; // [${nbits - packbit}:${nbits - (packbit + f.get_n_bits("d") - 1)}]<% packbit += f.get_n_bits("d") %>
-      % else:
-      logic d; // [${nbits - packbit}]<% packbit += 1 %>
-      % endif
-      % if not r.hwext:
-      logic de; // [${nbits - packbit}]<% packbit += 1 %>
-      % endif
-    } ${f.name};
-      % endif
-    % endfor
-  } ${r.name};
+    ${block.name + "_hw2reg_" + r.name + "_reg_t"} ${r.name}; // [${nbits - packbit}:${nbits - (packbit + r.get_n_bits(["q", "qe", "re"]) - 1)}]<% packbit += r.get_n_bits(["q", "qe", "re"]) %>\
+
   % endif
 % endfor
-} ${block.name}_hw2reg_t;
+  } ${block.name}_hw2reg_t;
 % endif
 
   // Register Address