diff --git a/hw/ip/alert_handler/rtl/alert_handler_accu.sv b/hw/ip/alert_handler/rtl/alert_handler_accu.sv
index 1d32280..0865239 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_accu.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_accu.sv
@@ -10,17 +10,17 @@
 // does not wrap around.
 //
 
-module alert_handler_accu (
-  input                                   clk_i,
-  input                                   rst_ni,
-  input                                   clr_i,        // clear the accumulator
-  input                                   class_trig_i, // increments the accu
-  input        [alert_pkg::AccuCntDw-1:0] thresh_i,     // escalation trigger threshold
-  output logic [alert_pkg::AccuCntDw-1:0] accu_cnt_o,   // output of current accu value
-  output logic                            accu_trig_o   // escalation trigger output
+module alert_handler_accu import alert_pkg::*; (
+  input                        clk_i,
+  input                        rst_ni,
+  input                        clr_i,        // clear the accumulator
+  input                        class_trig_i, // increments the accu
+  input        [AccuCntDw-1:0] thresh_i,     // escalation trigger threshold
+  output logic [AccuCntDw-1:0] accu_cnt_o,   // output of current accu value
+  output logic                 accu_trig_o   // escalation trigger output
 );
 
-  logic [alert_pkg::AccuCntDw-1:0] accu_d, accu_q;
+  logic [AccuCntDw-1:0] accu_d, accu_q;
 
   assign accu_d = (clr_i)                      ? '0            : // clear
                   (class_trig_i && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum
diff --git a/hw/ip/alert_handler/rtl/alert_handler_class.sv b/hw/ip/alert_handler/rtl/alert_handler_class.sv
index 9f0838e..be23344 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_class.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_class.sv
@@ -7,18 +7,18 @@
 // produces the alert cause and class trigger signals.
 //
 
-module alert_handler_class (
-  input [alert_pkg::NAlerts-1:0]                              alert_trig_i,      // alert trigger
-  input [alert_pkg::N_LOC_ALERT-1:0]                          loc_alert_trig_i,  // alert trigger
-  input [alert_pkg::NAlerts-1:0]                              alert_en_i,        // alert enable
-  input [alert_pkg::N_LOC_ALERT-1:0]                          loc_alert_en_i,    // alert enable
-  input [alert_pkg::NAlerts-1:0]    [alert_pkg::CLASS_DW-1:0] alert_class_i,     // class assignment
-  input [alert_pkg::N_LOC_ALERT-1:0][alert_pkg::CLASS_DW-1:0] loc_alert_class_i, // class assignment
-  input [alert_pkg::N_CLASSES-1:0]                            class_en_i,        // class enables
+module alert_handler_class import alert_pkg::*; (
+  input [NAlerts-1:0]                   alert_trig_i,      // alert trigger
+  input [N_LOC_ALERT-1:0]               loc_alert_trig_i,  // alert trigger
+  input [NAlerts-1:0]                   alert_en_i,        // alert enable
+  input [N_LOC_ALERT-1:0]               loc_alert_en_i,    // alert enable
+  input [NAlerts-1:0]    [CLASS_DW-1:0] alert_class_i,     // class assignment
+  input [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class_i, // class assignment
+  input [N_CLASSES-1:0]                 class_en_i,        // class enables
 
-  output logic [alert_pkg::NAlerts-1:0]                       alert_cause_o,     // alert cause
-  output logic [alert_pkg::N_LOC_ALERT-1:0]                   loc_alert_cause_o, // alert cause
-  output logic [alert_pkg::N_CLASSES-1:0]                     class_trig_o       // class triggered
+  output logic [NAlerts-1:0]            alert_cause_o,     // alert cause
+  output logic [N_LOC_ALERT-1:0]        loc_alert_cause_o, // alert cause
+  output logic [N_CLASSES-1:0]          class_trig_o       // class triggered
 );
 
   // assign alert cause
@@ -26,23 +26,23 @@
   assign loc_alert_cause_o = loc_alert_en_i & loc_alert_trig_i;
 
   // classification mapping
-  logic [alert_pkg::N_CLASSES-1:0][alert_pkg::NAlerts-1:0]     class_masks;
-  logic [alert_pkg::N_CLASSES-1:0][alert_pkg::N_LOC_ALERT-1:0] loc_class_masks;
+  logic [N_CLASSES-1:0][NAlerts-1:0]     class_masks;
+  logic [N_CLASSES-1:0][N_LOC_ALERT-1:0] loc_class_masks;
 
   // this is basically an address to onehot0 decoder
   always_comb begin : p_class_mask
     class_masks = '0;
     loc_class_masks = '0;
-    for (int unsigned kk = 0; kk < alert_pkg::NAlerts; kk++) begin
+    for (int unsigned kk = 0; kk < NAlerts; kk++) begin
       class_masks[alert_class_i[kk]][kk] = 1'b1;
     end
-    for (int unsigned kk = 0; kk < alert_pkg::N_LOC_ALERT; kk++) begin
+    for (int unsigned kk = 0; kk < N_LOC_ALERT; kk++) begin
       loc_class_masks[loc_alert_class_i[kk]][kk] = 1'b1;
     end
   end
 
   // mask and OR reduction, followed by class enable gating
-  for (genvar k = 0; k < alert_pkg::N_CLASSES; k++) begin : gen_classifier
+  for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classifier
     assign class_trig_o[k] = class_en_i[k]         &
                              (|{ alert_cause_o     & class_masks[k],
                                  loc_alert_cause_o & loc_class_masks[k] });
diff --git a/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv
index 84fcaeb..81dcf5e 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv
@@ -16,35 +16,35 @@
 // Note that escalation always takes precedence over the interrupt timeout.
 //
 
-module alert_handler_esc_timer (
-  input                                   clk_i,
-  input                                   rst_ni,
-  input                                   en_i,           // enables timeout/escalation
-  input                                   clr_i,          // aborts escalation
-  input                                   accum_trig_i,   // this will trigger escalation
-  input                                   timeout_en_i,   // enables timeout
-  input        [alert_pkg::EscCntDw-1:0]  timeout_cyc_i,  // interrupt timeout. 0 = disabled
-  input        [alert_pkg::N_ESC_SEV-1:0] esc_en_i,       // escalation signal enables
-  input        [alert_pkg::N_ESC_SEV-1:0]
-               [alert_pkg::PHASE_DW-1:0]  esc_map_i,      // escalation signal / phase map
-  input        [alert_pkg::N_PHASES-1:0]
-               [alert_pkg::EscCntDw-1:0]  phase_cyc_i,    // cycle counts of individual phases
-  output logic                            esc_trig_o,     // asserted if escalation triggers
-  output logic [alert_pkg::EscCntDw-1:0]  esc_cnt_o,      // current timeout / escalation count
-  output logic [alert_pkg::N_ESC_SEV-1:0] esc_sig_en_o,   // escalation signal outputs
+module alert_handler_esc_timer import alert_pkg::*; (
+  input                        clk_i,
+  input                        rst_ni,
+  input                        en_i,           // enables timeout/escalation
+  input                        clr_i,          // aborts escalation
+  input                        accum_trig_i,   // this will trigger escalation
+  input                        timeout_en_i,   // enables timeout
+  input        [EscCntDw-1:0]  timeout_cyc_i,  // interrupt timeout. 0 = disabled
+  input        [N_ESC_SEV-1:0] esc_en_i,       // escalation signal enables
+  input        [N_ESC_SEV-1:0]
+               [PHASE_DW-1:0]  esc_map_i,      // escalation signal / phase map
+  input        [N_PHASES-1:0]
+               [EscCntDw-1:0]  phase_cyc_i,    // cycle counts of individual phases
+  output logic                 esc_trig_o,     // asserted if escalation triggers
+  output logic [EscCntDw-1:0]  esc_cnt_o,      // current timeout / escalation count
+  output logic [N_ESC_SEV-1:0] esc_sig_en_o,   // escalation signal outputs
   // current state output
   // 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3
-  output alert_pkg::cstate_e              esc_state_o
+  output cstate_e              esc_state_o
 );
 
   /////////////
   // Counter //
   /////////////
 
-  alert_pkg::cstate_e state_d, state_q;
+  cstate_e state_d, state_q;
 
   logic cnt_en, cnt_clr, cnt_ge;
-  logic [alert_pkg::EscCntDw-1:0] cnt_d, cnt_q;
+  logic [EscCntDw-1:0] cnt_d, cnt_q;
 
   // escalation counter, used for all phases and the timeout
   assign cnt_d = cnt_q + 1'b1;
@@ -55,14 +55,14 @@
 
   // threshold test, the thresholds are muxed further below
   // depending on the current state
-  logic [alert_pkg::EscCntDw-1:0] thresh;
+  logic [EscCntDw-1:0] thresh;
   assign cnt_ge    = (cnt_q >= thresh);
 
   //////////////
   // Main FSM //
   //////////////
 
-  logic [alert_pkg::N_PHASES-1:0] phase_oh;
+  logic [N_PHASES-1:0] phase_oh;
 
   always_comb begin : p_fsm
     // default
@@ -76,16 +76,16 @@
     unique case (state_q)
       // wait for an escalation trigger or an alert trigger
       // the latter will trigger an interrupt timeout
-      alert_pkg::Idle: begin
+      Idle: begin
         if (accum_trig_i && en_i) begin
-          state_d    = alert_pkg::Phase0;
+          state_d    = Phase0;
           cnt_en     = 1'b1;
           esc_trig_o = 1'b1;
         // the counter is zero in this state. so if the
         // timeout count is zero (==disabled), cnt_ge will be true.
         end else if (timeout_en_i && !cnt_ge && en_i) begin
           cnt_en  = 1'b1;
-          state_d = alert_pkg::Timeout;
+          state_d = Timeout;
         end else begin
           cnt_clr = 1'b1;
         end
@@ -96,9 +96,9 @@
       // in case the interrupt timeout hits it's cycle count, we
       // also enter escalation phase0.
       // ongoing timeouts can always be cleared.
-      alert_pkg::Timeout: begin
+      Timeout: begin
         if (accum_trig_i || (cnt_ge && timeout_en_i)) begin
-          state_d    = alert_pkg::Phase0;
+          state_d    = Phase0;
           cnt_en     = 1'b1;
           cnt_clr    = 1'b1;
           esc_trig_o = 1'b1;
@@ -107,65 +107,65 @@
         end else if (timeout_en_i) begin
           cnt_en  = 1'b1;
         end else begin
-          state_d = alert_pkg::Idle;
+          state_d = Idle;
           cnt_clr = 1'b1;
         end
       end
       // note: autolocking the clear signal is done in the regfile
-      alert_pkg::Phase0: begin
+      Phase0: begin
         phase_oh[0] = 1'b1;
         thresh      = phase_cyc_i[0];
 
         if (clr_i) begin
-          state_d = alert_pkg::Idle;
+          state_d = Idle;
           cnt_clr = 1'b1;
         end else if (cnt_ge) begin
-          state_d = alert_pkg::Phase1;
+          state_d = Phase1;
           cnt_clr = 1'b1;
           cnt_en  = 1'b1;
         end else begin
           cnt_en = 1'b1;
         end
       end
-      alert_pkg::Phase1: begin
+      Phase1: begin
         phase_oh[1] = 1'b1;
         thresh      = phase_cyc_i[1];
 
         if (clr_i) begin
-          state_d = alert_pkg::Idle;
+          state_d = Idle;
           cnt_clr = 1'b1;
         end else if (cnt_ge) begin
-          state_d = alert_pkg::Phase2;
+          state_d = Phase2;
           cnt_clr = 1'b1;
           cnt_en  = 1'b1;
         end else begin
           cnt_en = 1'b1;
         end
       end
-      alert_pkg::Phase2: begin
+      Phase2: begin
         phase_oh[2] = 1'b1;
         thresh      = phase_cyc_i[2];
 
         if (clr_i) begin
-          state_d = alert_pkg::Idle;
+          state_d = Idle;
           cnt_clr = 1'b1;
         end else if (cnt_ge) begin
-          state_d = alert_pkg::Phase3;
+          state_d = Phase3;
           cnt_clr = 1'b1;
           cnt_en  = 1'b1;
         end else begin
           cnt_en = 1'b1;
         end
       end
-      alert_pkg::Phase3: begin
+      Phase3: begin
         phase_oh[3] = 1'b1;
         thresh      = phase_cyc_i[3];
 
         if (clr_i) begin
-          state_d = alert_pkg::Idle;
+          state_d = Idle;
           cnt_clr = 1'b1;
         end else if (cnt_ge) begin
-          state_d = alert_pkg::Terminal;
+          state_d = Terminal;
           cnt_clr = 1'b1;
         end else begin
           cnt_en = 1'b1;
@@ -174,19 +174,19 @@
       // final, terminal state after escalation.
       // if clr is locked down, only a system reset
       // will get us out of this state
-      alert_pkg::Terminal: begin
+      Terminal: begin
         if (clr_i) begin
-          state_d = alert_pkg::Idle;
+          state_d = Idle;
         end
       end
-      default : state_d = alert_pkg::Idle;
+      default : state_d = Idle;
     endcase
   end
 
-  logic [alert_pkg::N_ESC_SEV-1:0][alert_pkg::N_PHASES-1:0] esc_map_oh;
-  for (genvar k = 0; k < alert_pkg::N_ESC_SEV; k++) begin : gen_phase_map
+  logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
+  for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
     // generate configuration mask for escalation enable signals
-    assign esc_map_oh[k] = alert_pkg::N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
+    assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
     // mask reduce current phase state vector
     assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
   end
@@ -198,14 +198,14 @@
   // switch interrupt / escalation mode
   always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
     if (!rst_ni) begin
-      state_q <= alert_pkg::Idle;
+      state_q <= Idle;
       cnt_q   <= '0;
     end else begin
       state_q <= state_d;
 
       // escalation counter
       if (cnt_en && cnt_clr) begin
-        cnt_q <= alert_pkg::EscCntDw'(1'b1);
+        cnt_q <= EscCntDw'(1'b1);
       end else if (cnt_clr) begin
         cnt_q <= '0;
       end else if (cnt_en) begin
@@ -219,34 +219,34 @@
   ////////////////
 
   // a clear should always bring us back to idle
-  `ASSERT(CheckClr, clr_i && state_q != alert_pkg::Timeout |=>
-      state_q == alert_pkg::Idle, clk_i, !rst_ni)
+  `ASSERT(CheckClr, clr_i && state_q != Timeout |=>
+      state_q == Idle, clk_i, !rst_ni)
   // if currently in idle and not enabled, must remain here
-  `ASSERT(CheckEn,  state_q == alert_pkg::Idle && !en_i |=>
-      state_q == alert_pkg::Idle, clk_i, !rst_ni)
+  `ASSERT(CheckEn,  state_q == Idle && !en_i |=>
+      state_q == Idle, clk_i, !rst_ni)
   // Check if accumulation trigger correctly captured
-  `ASSERT(CheckAccumTrig0,  accum_trig_i && state_q == alert_pkg::Idle && en_i |=>
-      state_q == alert_pkg::Phase0, clk_i, !rst_ni)
-  `ASSERT(CheckAccumTrig1,  accum_trig_i && state_q == alert_pkg::Timeout && en_i |=>
-      state_q == alert_pkg::Phase0, clk_i, !rst_ni)
+  `ASSERT(CheckAccumTrig0,  accum_trig_i && state_q == Idle && en_i |=>
+      state_q == Phase0, clk_i, !rst_ni)
+  `ASSERT(CheckAccumTrig1,  accum_trig_i && state_q == Timeout && en_i |=>
+      state_q == Phase0, clk_i, !rst_ni)
   // Check if timeout correctly captured
-  `ASSERT(CheckTimeout0, state_q == alert_pkg::Idle && timeout_en_i && en_i && !cnt_ge |=>
-      state_q == alert_pkg::Timeout, clk_i, !rst_ni || accum_trig_i)
-  `ASSERT(CheckTimeout1, state_q == alert_pkg::Timeout && timeout_en_i  |=>
-      state_q == alert_pkg::Timeout, clk_i, !rst_ni || accum_trig_i)
-  `ASSERT(CheckTimeout2, state_q == alert_pkg::Timeout && !timeout_en_i |=>
-      state_q == alert_pkg::Idle, clk_i, !rst_ni || accum_trig_i)
+  `ASSERT(CheckTimeout0, state_q == Idle && timeout_en_i && en_i && !cnt_ge |=>
+      state_q == Timeout, clk_i, !rst_ni || accum_trig_i)
+  `ASSERT(CheckTimeout1, state_q == Timeout && timeout_en_i  |=>
+      state_q == Timeout, clk_i, !rst_ni || accum_trig_i)
+  `ASSERT(CheckTimeout2, state_q == Timeout && !timeout_en_i |=>
+      state_q == Idle, clk_i, !rst_ni || accum_trig_i)
   // Check if timeout correctly triggers escalation
-  `ASSERT(CheckTimeoutTrig, state_q == alert_pkg::Timeout && timeout_en_i &&
-      cnt_q == timeout_cyc_i |=> state_q == alert_pkg::Phase0, clk_i, !rst_ni)
+  `ASSERT(CheckTimeoutTrig, state_q == Timeout && timeout_en_i &&
+      cnt_q == timeout_cyc_i |=> state_q == Phase0, clk_i, !rst_ni)
   // Check whether escalation phases are correctly switched
-  `ASSERT(CheckPhase0, state_q == alert_pkg::Phase0 && !clr_i && cnt_q == phase_cyc_i[0] |=>
-      state_q == alert_pkg::Phase1, clk_i, !rst_ni)
-  `ASSERT(CheckPhase1, state_q == alert_pkg::Phase1 && !clr_i && cnt_q == phase_cyc_i[1] |=>
-      state_q == alert_pkg::Phase2, clk_i, !rst_ni)
-  `ASSERT(CheckPhase2, state_q == alert_pkg::Phase2 && !clr_i && cnt_q == phase_cyc_i[2] |=>
-      state_q == alert_pkg::Phase3, clk_i, !rst_ni)
-  `ASSERT(CheckPhase3, state_q == alert_pkg::Phase3 && !clr_i && cnt_q == phase_cyc_i[3] |=>
-      state_q == alert_pkg::Terminal, clk_i, !rst_ni)
+  `ASSERT(CheckPhase0, state_q == Phase0 && !clr_i && cnt_q == phase_cyc_i[0] |=>
+      state_q == Phase1, clk_i, !rst_ni)
+  `ASSERT(CheckPhase1, state_q == Phase1 && !clr_i && cnt_q == phase_cyc_i[1] |=>
+      state_q == Phase2, clk_i, !rst_ni)
+  `ASSERT(CheckPhase2, state_q == Phase2 && !clr_i && cnt_q == phase_cyc_i[2] |=>
+      state_q == Phase3, clk_i, !rst_ni)
+  `ASSERT(CheckPhase3, state_q == Phase3 && !clr_i && cnt_q == phase_cyc_i[3] |=>
+      state_q == Terminal, clk_i, !rst_ni)
 
 endmodule : alert_handler_esc_timer
diff --git a/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv
index d034358..fda09ff 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv
@@ -19,22 +19,22 @@
 // requested), the ping timer will also raise an internal alert.
 //
 
-module alert_handler_ping_timer (
-  input                                     clk_i,
-  input                                     rst_ni,
-  input                                     entropy_i,          // from TRNG
-  input                                     en_i,               // enable ping testing
-  input        [alert_pkg::NAlerts-1:0]     alert_en_i,         // determines which alerts to ping
-  input        [alert_pkg::PING_CNT_DW-1:0] ping_timeout_cyc_i, // timeout in cycles
-  output logic [alert_pkg::NAlerts-1:0]     alert_ping_en_o,    // enable to alert receivers
-  output logic [alert_pkg::N_ESC_SEV-1:0]   esc_ping_en_o,      // enable to esc senders
-  input        [alert_pkg::NAlerts-1:0]     alert_ping_ok_i,    // response from alert receivers
-  input        [alert_pkg::N_ESC_SEV-1:0]   esc_ping_ok_i,      // response from esc senders
-  output logic                              alert_ping_fail_o,  // any of the alert receivers failed
-  output logic                              esc_ping_fail_o     // any of the esc senders failed
+module alert_handler_ping_timer import alert_pkg::*; (
+  input                          clk_i,
+  input                          rst_ni,
+  input                          entropy_i,          // from TRNG
+  input                          en_i,               // enable ping testing
+  input        [NAlerts-1:0]     alert_en_i,         // determines which alerts to ping
+  input        [PING_CNT_DW-1:0] ping_timeout_cyc_i, // timeout in cycles
+  output logic [NAlerts-1:0]     alert_ping_en_o,    // enable to alert receivers
+  output logic [N_ESC_SEV-1:0]   esc_ping_en_o,      // enable to esc senders
+  input        [NAlerts-1:0]     alert_ping_ok_i,    // response from alert receivers
+  input        [N_ESC_SEV-1:0]   esc_ping_ok_i,      // response from esc senders
+  output logic                   alert_ping_fail_o,  // any of the alert receivers failed
+  output logic                   esc_ping_fail_o     // any of the esc senders failed
 );
 
-  localparam int unsigned NModsToPing = alert_pkg::NAlerts + alert_pkg::N_ESC_SEV;
+  localparam int unsigned NModsToPing = NAlerts + N_ESC_SEV;
   localparam int unsigned IdDw        = $clog2(NModsToPing);
 
   // this defines a random permutation
@@ -53,6 +53,7 @@
 
   logic lfsr_en;
   logic [31:0] lfsr_state, perm_state;
+  logic [16-IdDw-1:0] unused_perm_state;
 
   prim_lfsr #(
     .LfsrDw      ( 32                  ),
@@ -74,18 +75,19 @@
   end
 
   logic [IdDw-1:0] id_to_ping;
-  logic [alert_pkg::PING_CNT_DW-1:0] wait_cyc;
+  logic [PING_CNT_DW-1:0] wait_cyc;
   // we only use bits up to 23, as IdDw is 8bit maximum
   assign id_to_ping = perm_state[16 +: IdDw];
+  assign unused_perm_state = perm_state[31:16+IdDw];
   // concatenate with constant offset, introduce some stagger
   // by concatenating the lower bits below
   assign wait_cyc   = {perm_state[15:2], 8'h01, perm_state[1:0]};
 
   logic [2**IdDw-1:0] enable_mask;
   always_comb begin : p_enable_mask
-    enable_mask                                   = '0;         // tie off unused
-    enable_mask[alert_pkg::NAlerts-1:0]           = alert_en_i; // alerts
-    enable_mask[NModsToPing-1:alert_pkg::NAlerts] = '1;         // escalation senders
+    enable_mask                        = '0;         // tie off unused
+    enable_mask[NAlerts-1:0]           = alert_en_i; // alerts
+    enable_mask[NModsToPing-1:NAlerts] = '1;         // escalation senders
   end
 
   logic id_vld;
@@ -96,7 +98,7 @@
   // Counter //
   /////////////
 
-  logic [alert_pkg::PING_CNT_DW-1:0] cnt_d, cnt_q;
+  logic [PING_CNT_DW-1:0] cnt_d, cnt_q;
   logic cnt_en, cnt_clr;
   logic wait_ge, timeout_ge;
 
@@ -116,9 +118,9 @@
   logic spurious_alert_ping, spurious_esc_ping;
 
   // generate ping enable vector
-  assign ping_sel        = (alert_pkg::NAlerts+alert_pkg::N_ESC_SEV)'(ping_en) << id_to_ping;
-  assign alert_ping_en_o = ping_sel[alert_pkg::NAlerts-1:0];
-  assign esc_ping_en_o   = ping_sel[NModsToPing-1:alert_pkg::NAlerts];
+  assign ping_sel        = NModsToPing'(ping_en) << id_to_ping;
+  assign alert_ping_en_o = ping_sel[NAlerts-1:0];
+  assign esc_ping_en_o   = ping_sel[NModsToPing-1:NAlerts];
 
   // mask out response
   assign ping_ok             = |({esc_ping_ok_i, alert_ping_ok_i} & ping_sel);
@@ -126,8 +128,8 @@
   // under normal operation, these signals should never be asserted.
   // double check that these signals are not optimized away during synthesis.
   // this may need "don't touch" or "no boundary optimization" constraints
-  assign spurious_alert_ping = |spurious_ping[alert_pkg::NAlerts-1:0];
-  assign spurious_esc_ping   = |spurious_ping[NModsToPing-1:alert_pkg::NAlerts];
+  assign spurious_alert_ping = |spurious_ping[NAlerts-1:0];
+  assign spurious_esc_ping   = |spurious_ping[NModsToPing-1:NAlerts];
 
   always_comb begin : p_fsm
     // default
@@ -174,7 +176,7 @@
           state_d = RespWait;
           cnt_clr = 1'b1;
           if (timeout_ge) begin
-            if (id_to_ping < alert_pkg::NAlerts) begin
+            if (id_to_ping < NAlerts) begin
               alert_ping_fail_o = 1'b1;
             end else begin
               esc_ping_fail_o   = 1'b1;
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
index 068dc85..1a245c0 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
@@ -4,20 +4,20 @@
 //
 // Breakout / remapping wrapper for register file. Generated from template.
 
-module alert_handler_reg_wrap (
+module alert_handler_reg_wrap import alert_pkg::*; (
   input                                   clk_i,
   input                                   rst_ni,
   // Bus Interface (device)
   input  tlul_pkg::tl_h2d_t               tl_i,
   output tlul_pkg::tl_d2h_t               tl_o,
   // interrupt
-  output logic [alert_pkg::N_CLASSES-1:0] irq_o,
+  output logic [N_CLASSES-1:0] irq_o,
   // State information for HW crashdump
-  output alert_pkg::alert_crashdump_t     crashdump_o,
+  output alert_crashdump_t     crashdump_o,
   // hw2reg
-  input  alert_pkg::hw2reg_wrap_t         hw2reg_wrap,
+  input  hw2reg_wrap_t         hw2reg_wrap,
   // reg2hw
-  output alert_pkg::reg2hw_wrap_t         reg2hw_wrap
+  output reg2hw_wrap_t         reg2hw_wrap
 );
 
 
@@ -25,7 +25,7 @@
   // reg instance //
   //////////////////
 
-  logic [alert_pkg::N_CLASSES-1:0] class_autolock_en;
+  logic [N_CLASSES-1:0] class_autolock_en;
   alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw;
   alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg;
 
@@ -101,16 +101,18 @@
 
   // if an alert is enabled and it fires,
   // we have to set the corresponding cause bit
-  for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_alert_cause
+  for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause
     assign hw2reg.alert_cause[k].d  = 1'b1;
-    assign hw2reg.alert_cause[k].de = hw2reg_wrap.alert_cause[k];
+    assign hw2reg.alert_cause[k].de = reg2hw.alert_cause[k].q |
+                                      hw2reg_wrap.alert_cause[k];
   end
 
   // if a local alert is enabled and it fires,
   // we have to set the corresponding cause bit
-  for (genvar k = 0; k < alert_pkg::N_LOC_ALERT; k++) begin : gen_loc_alert_cause
+  for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause
     assign hw2reg.loc_alert_cause[k].d  = 1'b1;
-    assign hw2reg.loc_alert_cause[k].de = hw2reg_wrap.loc_alert_cause[k];
+    assign hw2reg.loc_alert_cause[k].de = reg2hw.loc_alert_cause[k].q |
+                                          hw2reg_wrap.loc_alert_cause[k];
   end
 
   // ping timeout in cycles
@@ -154,13 +156,13 @@
   assign reg2hw_wrap.config_locked = ~reg2hw.regen.q;
 
   // alert enable and class assignments
-  for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_alert_en_class
+  for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_en_class
     assign reg2hw_wrap.alert_en[k]    = reg2hw.alert_en[k].q;
     assign reg2hw_wrap.alert_class[k] = reg2hw.alert_class[k].q;
   end
 
   // local alert enable and class assignments
-  for (genvar k = 0; k < alert_pkg::N_LOC_ALERT; k++) begin : gen_loc_alert_en_class
+  for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_en_class
     assign reg2hw_wrap.loc_alert_en[k]    = reg2hw.loc_alert_en[k].q;
     assign reg2hw_wrap.loc_alert_class[k] = reg2hw.loc_alert_class[k].q;
   end
@@ -267,12 +269,12 @@
   //////////////////////
 
   // alert cause output
-  for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_alert_cause_dump
+  for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause_dump
     assign crashdump_o.alert_cause[k]  = reg2hw.alert_cause[k].q;
   end
 
   // local alert cause register output
-  for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_loc_alert_cause_dump
+  for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause_dump
     assign crashdump_o.loc_alert_cause[k]  = reg2hw.loc_alert_cause[k].q;
   end
 
diff --git a/hw/ip/hmac/data/hmac.hjson b/hw/ip/hmac/data/hmac.hjson
index fc2449d..afe5963 100644
--- a/hw/ip/hmac/data/hmac.hjson
+++ b/hw/ip/hmac/data/hmac.hjson
@@ -5,8 +5,6 @@
   clock_primary: "clk_i",
   bus_device: "tlul",
   bus_host: "none",
-  available_input_list: [],
-  available_output_list: [],
   interrupt_list: [
     { name: "hmac_done",
       desc: "HMAC-256 completes a message with key"
@@ -19,6 +17,9 @@
     }
   ],
   alert_list: [
+    { name: "msg_push_sha_disabled",
+      desc: "Dummy alert which is triggered upon writing a message when SHA is disabled",
+    }
   ],
   param_list: [
     { name:    "NumWords",
diff --git a/hw/ip/hmac/data/hmac.prj.hjson b/hw/ip/hmac/data/hmac.prj.hjson
index d7cbaae..2b94858 100644
--- a/hw/ip/hmac/data/hmac.prj.hjson
+++ b/hw/ip/hmac/data/hmac.prj.hjson
@@ -4,10 +4,22 @@
 
 {
     name:               "hmac",
-    version:            "0.5",
-    life_stage:         "L2",
-    design_stage:       "D3",
-    verification_stage: "V3",
-    commit_id:          "635afdb8dedbb50c235bd772b36002925c499884",
-    notes:              ""
+    revisions: [
+      {
+	    version:            "0.5",
+	    life_stage:         "L2",
+	    design_stage:       "D3",
+	    verification_stage: "V3",
+	    commit_id:          "635afdb8dedbb50c235bd772b36002925c499884",
+	    notes:              ""
+      }
+      {
+        version:            "0.6",
+        life_stage:         "L1",
+        design_stage:       "D2",
+        verification_stage: "V1",
+        commit_id:          "",
+        notes:              "Rolled back to D2 in order to add the first alert",
+      }
+    ]
 }
diff --git a/hw/ip/hmac/dv/env/hmac_env.sv b/hw/ip/hmac/dv/env/hmac_env.sv
index 397a625..357389b 100644
--- a/hw/ip/hmac/dv/env/hmac_env.sv
+++ b/hw/ip/hmac/dv/env/hmac_env.sv
@@ -11,6 +11,16 @@
 
   function void build_phase(uvm_phase phase);
     super.build_phase(phase);
+    // get vifs
+    if (!uvm_config_db#(ping_en_vif)::get(this, "", "ping_en_vif", cfg.ping_en_vif)) begin
+      `uvm_fatal(get_full_name(), "failed to get ping_en_vif from uvm_config_db")
+    end
+    if (!uvm_config_db#(ping_ok_vif)::get(this, "", "ping_ok_vif", cfg.ping_ok_vif)) begin
+      `uvm_fatal(get_full_name(), "failed to get ping_ok_vif from uvm_config_db")
+    end
+    if (!uvm_config_db#(integ_fail_vif)::get(this, "", "integ_fail_vif", cfg.integ_fail_vif)) begin
+      `uvm_fatal(get_full_name(), "failed to get integ_fail_vif from uvm_config_db")
+    end
   endfunction
 
 endclass
diff --git a/hw/ip/hmac/dv/env/hmac_env_cfg.sv b/hw/ip/hmac/dv/env/hmac_env_cfg.sv
index 9e4a2e8..a90d99c 100644
--- a/hw/ip/hmac/dv/env/hmac_env_cfg.sv
+++ b/hw/ip/hmac/dv/env/hmac_env_cfg.sv
@@ -3,6 +3,11 @@
 // SPDX-License-Identifier: Apache-2.0
 
 class hmac_env_cfg extends cip_base_env_cfg #(.RAL_T(hmac_reg_block));
+
+  ping_en_vif    ping_en_vif;
+  ping_ok_vif    ping_ok_vif;
+  integ_fail_vif integ_fail_vif;
+
   `uvm_object_utils(hmac_env_cfg)
   `uvm_object_new
 
diff --git a/hw/ip/hmac/dv/env/hmac_env_pkg.sv b/hw/ip/hmac/dv/env/hmac_env_pkg.sv
index f1dbef4..53a6e15 100644
--- a/hw/ip/hmac/dv/env/hmac_env_pkg.sv
+++ b/hw/ip/hmac/dv/env/hmac_env_pkg.sv
@@ -71,6 +71,11 @@
   typedef cip_base_virtual_sequencer #(hmac_env_cfg, hmac_env_cov) hmac_virtual_sequencer;
   typedef virtual pins_if #(1) d2h_a_ready_vif;
 
+  // TODO: need to standardize this and move into uvm generator
+  typedef virtual pins_if #(NUM_MAX_ALERTS) ping_en_vif;
+  typedef virtual pins_if #(NUM_MAX_ALERTS) ping_ok_vif;
+  typedef virtual pins_if #(NUM_MAX_ALERTS) integ_fail_vif;
+
   // functions
 
   // package sources
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index eb225c0..06c516f 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -59,6 +59,8 @@
 
   virtual task dut_init(string reset_kind = "HARD");
     super.dut_init(reset_kind);
+    // TODO: need agent for full alert protocol
+    cfg.ping_en_vif.drive('0);
     if (do_hmac_init) hmac_init();
   endtask
 
diff --git a/hw/ip/hmac/dv/tb/tb.sv b/hw/ip/hmac/dv/tb/tb.sv
index da9596a..6e2f4a0 100644
--- a/hw/ip/hmac/dv/tb/tb.sv
+++ b/hw/ip/hmac/dv/tb/tb.sv
@@ -17,7 +17,12 @@
   wire clk, rst_n;
   wire devmode;
   wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
-  wire [NUM_MAX_ALERTS-1:0] alerts;
+  wire [NUM_MAX_ALERTS-1:0]     alerts;
+  wire [NUM_MAX_ALERTS-1:0]     ping_ok;
+  wire [NUM_MAX_ALERTS-1:0]     ping_en;
+  wire [NUM_MAX_ALERTS-1:0]     integ_fail;
+  prim_pkg::alert_rx_t [hmac_pkg::NumAlerts-1:0] alert_rx;
+  prim_pkg::alert_tx_t [hmac_pkg::NumAlerts-1:0] alert_tx;
 
   wire intr_hmac_done;
   wire intr_fifo_full;
@@ -27,20 +32,45 @@
   clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
   pins_if #(NUM_MAX_INTERRUPTS) intr_if(.pins(interrupts));
   pins_if #(NUM_MAX_ALERTS) alerts_if(.pins(alerts));
+  pins_if #(NUM_MAX_ALERTS) ping_ok_if(.pins(ping_ok));
+  pins_if #(NUM_MAX_ALERTS) ping_en_if(.pins(ping_en));
+  pins_if #(NUM_MAX_ALERTS) integ_fail_if(.pins(integ_fail));
   pins_if #(1) devmode_if(devmode);
   tl_if tl_if(.clk(clk), .rst_n(rst_n));
 
+
+  // alert receivers
+  logic [hmac_pkg::NumAlerts-1:0] ping_p, ping_n, ack_p, ack_n, alert_p, alert_n;
+  for (genvar j = 0; j < hmac_pkg::NumAlerts; j++) begin : gen_alert_rx
+    prim_alert_receiver #(
+      .AsyncOn(hmac_pkg::AlertAsyncOn[j])
+    ) i_prim_alert_receiver (
+      .clk_i        ( clk           ),
+      .rst_ni       ( rst_n         ),
+      .ping_en_i    ( ping_en[j]    ),
+      .ping_ok_o    ( ping_ok[j]    ),
+      .integ_fail_o ( integ_fail[j] ),
+      .alert_o      ( alert[j]      ),
+      .alert_rx_o   ( alert_rx[j]   ),
+      .alert_tx_i   ( alert_tx[j]   )
+    );
+  end : gen_alert_rx
+
+
   // dut
   hmac dut (
-    .clk_i          (clk       ),
-    .rst_ni         (rst_n     ),
+    .clk_i              ( clk            ),
+    .rst_ni             ( rst_n          ),
 
-    .tl_i           (tl_if.h2d ),
-    .tl_o           (tl_if.d2h ),
+    .tl_i               ( tl_if.h2d      ),
+    .tl_o               ( tl_if.d2h      ),
 
-    .intr_hmac_done_o   (intr_hmac_done),
-    .intr_fifo_full_o   (intr_fifo_full),
-    .intr_hmac_err_o    (intr_hmac_err)
+    .intr_hmac_done_o   ( intr_hmac_done ),
+    .intr_fifo_full_o   ( intr_fifo_full ),
+    .intr_hmac_err_o    ( intr_hmac_err  ),
+
+    .alert_rx_i         ( alert_rx       ),
+    .alert_tx_o         ( alert_tx       )
   );
 
   assign interrupts[HmacDone]        = intr_hmac_done;
@@ -53,6 +83,9 @@
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
     uvm_config_db#(alerts_vif)::set(null, "*.env", "alerts_vif", alerts_if);
+    uvm_config_db#(ping_ok_vif)::set(null, "*.env", "ping_ok_vif", ping_ok_if);
+    uvm_config_db#(ping_en_vif)::set(null, "*.env", "ping_en_vif", ping_en_if);
+    uvm_config_db#(integ_fail_vif)::set(null, "*.env", "integ_fail_vif", integ_fail_if);
     uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
     uvm_config_db#(tlul_assert_ctrl_vif)::set(null, "*.env", "tlul_assert_ctrl_vif",
         dut.tlul_assert_device.tlul_assert_ctrl_if);
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index da306f6..98dcf44 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -4,7 +4,11 @@
 //
 // HMAC-SHA256
 
-module hmac (
+module hmac
+  import prim_pkg::*;
+  import hmac_pkg::*;
+  import hmac_reg_pkg::*;
+(
   input clk_i,
   input rst_ni,
 
@@ -13,11 +17,13 @@
 
   output logic intr_hmac_done_o,
   output logic intr_fifo_full_o,
-  output logic intr_hmac_err_o
+  output logic intr_hmac_err_o,
+
+  // alerts
+  input  alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output alert_tx_t [NumAlerts-1:0] alert_tx_o
 );
 
-  import hmac_pkg::*;
-  import hmac_reg_pkg::*;
 
   /////////////////////////
   // Signal declarations //
@@ -461,6 +467,26 @@
     endcase
   end
 
+  /////////////////////
+  // Hardware Alerts //
+  /////////////////////
+
+  // TODO: add CSR with REGWEN to test alert via SW
+  logic [NumAlerts-1:0] alerts;
+  assign alerts = {msg_push_sha_disabled};
+
+  for (genvar j = 0; j < hmac_pkg::NumAlerts; j++) begin : gen_alert_tx
+    prim_alert_sender #(
+      .AsyncOn(hmac_pkg::AlertAsyncOn[j])
+    ) i_prim_alert_sender (
+      .clk_i      ( clk_i         ),
+      .rst_ni     ( rst_ni        ),
+      .alert_i    ( alerts[j]     ),
+      .alert_rx_i ( alert_rx_i[j] ),
+      .alert_tx_o ( alert_tx_o[j] )
+    );
+  end : gen_alert_tx
+
   //////////////////////////////////////////////
   // Assertions, Assumptions, and Coverpoints //
   //////////////////////////////////////////////
@@ -519,4 +545,7 @@
   `ASSERT_KNOWN(TlODValidKnown, tl_o.d_valid, clk_i, !rst_ni)
   `ASSERT_KNOWN(TlOAReadyKnown, tl_o.a_ready, clk_i, !rst_ni)
 
+  // Alert outputs
+  `ASSERT_KNOWN(AlertTxOKnown, alert_tx_o, clk_i, !rst_ni)
+
 endmodule
diff --git a/hw/ip/hmac/rtl/hmac_pkg.sv b/hw/ip/hmac/rtl/hmac_pkg.sv
index ebf7322..4880447 100644
--- a/hw/ip/hmac/rtl/hmac_pkg.sv
+++ b/hw/ip/hmac/rtl/hmac_pkg.sv
@@ -5,6 +5,11 @@
 
 package hmac_pkg;
 
+  // this currently uses the
+  // fully asynchronous implemenation
+  localparam int NumAlerts = 1;
+  localparam logic [NumAlerts-1:0] AlertAsyncOn = NumAlerts'(1'b1);
+
   localparam int MsgFifoDepth = 16;
 
   localparam NumRound = 64;   // SHA-224, SHA-256
diff --git a/hw/ip/prim/rtl/prim_alert_receiver.sv b/hw/ip/prim/rtl/prim_alert_receiver.sv
index 867a94d..2b3e440 100644
--- a/hw/ip/prim/rtl/prim_alert_receiver.sv
+++ b/hw/ip/prim/rtl/prim_alert_receiver.sv
@@ -186,11 +186,13 @@
 
   if (AsyncOn) begin : gen_async_assert
     // signal integrity check propagation
-    `ASSERT(SigInt_A, alert_tx_i.alert_p == alert_tx_i.alert_n [*2] |-> ##2 integ_fail_o, clk_i, !rst_ni)
+    `ASSERT(SigInt_A, alert_tx_i.alert_p == alert_tx_i.alert_n [*2] |->
+        ##2 integ_fail_o, clk_i, !rst_ni)
     // TODO: need to add skewed cases as well, the assertions below assume no skew at the moment
     // ping response
-    `ASSERT(PingResponse1_A, ##1 $rose(alert_tx_i.alert_p) && (alert_tx_i.alert_p ^ alert_tx_i.alert_n) ##2
-        state_q == Idle && ping_pending_q |-> ping_ok_o, clk_i, !rst_ni || integ_fail_o)
+    `ASSERT(PingResponse1_A, ##1 $rose(alert_tx_i.alert_p) &&
+        (alert_tx_i.alert_p ^ alert_tx_i.alert_n) ##2 state_q == Idle && ping_pending_q |->
+        ping_ok_o, clk_i, !rst_ni || integ_fail_o)
     // alert
     `ASSERT(Alert_A, ##1 $rose(alert_tx_i.alert_p) && (alert_tx_i.alert_p ^ alert_tx_i.alert_n) ##2
         state_q == Idle && !ping_pending_q |-> alert_o, clk_i, !rst_ni || integ_fail_o)
diff --git a/hw/ip/rv_plic/data/rv_plic.hjson b/hw/ip/rv_plic/data/rv_plic.hjson
index c61da3b..314fed0 100644
--- a/hw/ip/rv_plic/data/rv_plic.hjson
+++ b/hw/ip/rv_plic/data/rv_plic.hjson
@@ -331,7 +331,8 @@
       ],
     }
     { name: "CC0",
-      desc: "Claim interrupt by read, complete interrupt by write for Target 0. Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.",
+      desc: '''Claim interrupt by read, complete interrupt by write for Target 0.
+      Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
       swaccess: "rw",
       hwaccess: "hrw",
       hwext: "true",
@@ -342,7 +343,8 @@
       ],
     }
     { name: "MSIP0",
-      desc: "msip for Hart 0. Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear",
+      desc: '''msip for Hart 0.
+      Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''',
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
diff --git a/hw/ip/rv_plic/data/rv_plic.hjson.tpl b/hw/ip/rv_plic/data/rv_plic.hjson.tpl
index 672b2ed..fd3404f 100644
--- a/hw/ip/rv_plic/data/rv_plic.hjson.tpl
+++ b/hw/ip/rv_plic/data/rv_plic.hjson.tpl
@@ -87,7 +87,8 @@
       ],
     }
     { name: "CC${i}",
-      desc: "Claim interrupt by read, complete interrupt by write for Target ${i}. Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.",
+      desc: '''Claim interrupt by read, complete interrupt by write for Target ${i}.
+      Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
       swaccess: "rw",
       hwaccess: "hrw",
       hwext: "true",
@@ -98,7 +99,8 @@
       ],
     }
     { name: "MSIP${i}",
-      desc: "msip for Hart ${i}. Write 1 to here asserts software interrupt for Hart msip_o[${i}], write 0 to clear",
+      desc: '''msip for Hart ${i}.
+      Write 1 to here asserts software interrupt for Hart msip_o[${i}], write 0 to clear.''',
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 69ffef5..2eb89e0 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -113,6 +113,7 @@
           type: interrupt
         }
       ]
+      alert_list: []
       scan: "false"
     }
     {
@@ -148,6 +149,7 @@
           type: interrupt
         }
       ]
+      alert_list: []
       scan: "false"
     }
     {
@@ -225,6 +227,7 @@
           type: interrupt
         }
       ]
+      alert_list: []
       scan: "true"
     }
     {
@@ -278,6 +281,7 @@
           type: interrupt
         }
       ]
+      alert_list: []
       scan: "false"
     }
     {
@@ -306,6 +310,7 @@
           type: interrupt
         }
       ]
+      alert_list: []
       scan: "false"
     }
     {
@@ -327,6 +332,7 @@
       available_output_list: []
       available_inout_list: []
       interrupt_list: []
+      alert_list: []
       scan: "false"
     }
     {
@@ -365,6 +371,15 @@
           type: interrupt
         }
       ]
+      alert_list:
+      [
+        {
+          name: msg_push_sha_disabled
+          width: 1
+          type: alert
+          async: 0
+        }
+      ]
       scan: "false"
     }
     {
@@ -387,6 +402,7 @@
       available_output_list: []
       available_inout_list: []
       interrupt_list: []
+      alert_list: []
       scan: "false"
     }
     {
@@ -410,6 +426,102 @@
       available_output_list: []
       available_inout_list: []
       interrupt_list: []
+      alert_list: []
+      scan: "false"
+    }
+    {
+      name: alert_handler
+      type: alert_handler
+      clock_connections:
+      {
+        clk_i: main
+      }
+      reset_connections:
+      {
+        rst_ni: sys
+      }
+      base_addr: 0x40130000
+      generated: "true"
+      localparam:
+      {
+        EscCntDw: 32
+        AccuCntDw: 16
+        LfsrSeed: 0x7FFFFFFF
+      }
+      size: 0x1000
+      bus_device: tlul
+      bus_host: none
+      available_input_list: []
+      available_output_list: []
+      available_inout_list: []
+      interrupt_list:
+      [
+        {
+          name: classa
+          width: 1
+          type: interrupt
+        }
+        {
+          name: classb
+          width: 1
+          type: interrupt
+        }
+        {
+          name: classc
+          width: 1
+          type: interrupt
+        }
+        {
+          name: classd
+          width: 1
+          type: interrupt
+        }
+      ]
+      alert_list: []
+      scan: "false"
+    }
+    {
+      name: nmi_gen
+      type: nmi_gen
+      clock_connections:
+      {
+        clk_i: main
+      }
+      reset_connections:
+      {
+        rst_ni: sys
+      }
+      base_addr: 0x40140000
+      size: 0x1000
+      bus_device: tlul
+      bus_host: none
+      available_input_list: []
+      available_output_list: []
+      available_inout_list: []
+      interrupt_list:
+      [
+        {
+          name: esc0
+          width: 1
+          type: interrupt
+        }
+        {
+          name: esc1
+          width: 1
+          type: interrupt
+        }
+        {
+          name: esc2
+          width: 1
+          type: interrupt
+        }
+        {
+          name: esc3
+          width: 1
+          type: interrupt
+        }
+      ]
+      alert_list: []
       scan: "false"
     }
   ]
@@ -495,6 +607,8 @@
           hmac
           rv_plic
           pinmux
+          alert_handler
+          nmi_gen
         ]
         dm_sba:
         [
@@ -510,6 +624,8 @@
           hmac
           rv_plic
           pinmux
+          alert_handler
+          nmi_gen
         ]
       }
       nodes:
@@ -668,6 +784,26 @@
           pipeline_byp: "false"
           pipeline: "true"
         }
+        {
+          name: alert_handler
+          type: device
+          clock: main
+          inst_type: alert_handler
+          pipeline_byp: "false"
+          base_addr: 0x40130000
+          size_byte: 0x1000
+          pipeline: "true"
+        }
+        {
+          name: nmi_gen
+          type: device
+          clock: main
+          inst_type: nmi_gen
+          pipeline_byp: "false"
+          base_addr: 0x40140000
+          size_byte: 0x1000
+          pipeline: "true"
+        }
       ]
       clock: main
     }
@@ -679,6 +815,8 @@
     spi_device
     flash_ctrl
     hmac
+    alert_handler
+    nmi_gen
   ]
   interrupt:
   [
@@ -802,6 +940,59 @@
       width: 1
       type: interrupt
     }
+    {
+      name: alert_handler_classa
+      width: 1
+      type: interrupt
+    }
+    {
+      name: alert_handler_classb
+      width: 1
+      type: interrupt
+    }
+    {
+      name: alert_handler_classc
+      width: 1
+      type: interrupt
+    }
+    {
+      name: alert_handler_classd
+      width: 1
+      type: interrupt
+    }
+    {
+      name: nmi_gen_esc0
+      width: 1
+      type: interrupt
+    }
+    {
+      name: nmi_gen_esc1
+      width: 1
+      type: interrupt
+    }
+    {
+      name: nmi_gen_esc2
+      width: 1
+      type: interrupt
+    }
+    {
+      name: nmi_gen_esc3
+      width: 1
+      type: interrupt
+    }
+  ]
+  alert_module:
+  [
+    hmac
+  ]
+  alert:
+  [
+    {
+      name: hmac_msg_push_sha_disabled
+      width: 1
+      type: alert
+      async: 0
+    }
   ]
   pinmux:
   {
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index f593627..326236b 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -97,6 +97,26 @@
       reset_connections: {rst_ni: "sys"},
       base_addr: "0x40070000",
       generated: "true"
+    },
+    { name: "alert_handler",
+      type: "alert_handler",
+      clock_connections: {clk_i: "main"},
+      reset_connections: {rst_ni: "sys"},
+      base_addr: "0x40130000",
+      generated: "true"         // Indicate this module is generated in the topgen
+      localparam: {
+        EscCntDw:  32,
+        AccuCntDw: 16,
+        LfsrSeed:  "0x7FFFFFFF"
+      }
+    }
+    // dummy module to capture the alert handler escalation signals
+    // and test them by converting them into IRQs
+    { name: "nmi_gen",
+      type: "nmi_gen",
+      clock_connections: {clk_i: "main"},
+      reset_connections: {rst_ni: "sys"},
+      base_addr: "0x40140000",
     }
   ]
 
@@ -142,7 +162,8 @@
   // If interrupt is not defined, it uses the order from the module list
   // and include every modules.
   // first item goes to LSB of the interrupt source
-  interrupt_module: ["gpio", "uart", "spi_device", "flash_ctrl", "hmac" ]
+  interrupt_module: ["gpio", "uart", "spi_device", "flash_ctrl",
+                     "hmac", "alert_handler", "nmi_gen" ]
 
   // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
   // source. "sequential" is smaller but slower, "matrix" is larger but faster.
@@ -152,7 +173,14 @@
   interrupt: [
   ]
 
-  // TODO: ALERT HANDLER
+  // ===== ALERT HANDLER ======================================================
+  // list all modules that expose alerts
+  // first item goes to LSB of the interrupt source
+  alert_module: [ "hmac" ]
+
+  // generated list of alerts:
+  alert: [
+  ]
 
   // TODO: PINMUX
   pinmux: {
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index bc19c90..c0f3207 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -154,6 +154,7 @@
     % endfor
 % endfor
 
+
   <% add_spaces = " " * len(str((interrupt_num).bit_length()-1)) %>
   logic [0:0]${add_spaces}irq_plic;
   logic [0:0]${add_spaces}msip;
@@ -163,6 +164,21 @@
   // this avoids lint errors
   assign unused_irq_id = irq_id;
 
+  // Alert list
+  prim_pkg::alert_tx_t [alert_pkg::NAlerts-1:0]  alert_tx;
+  prim_pkg::alert_rx_t [alert_pkg::NAlerts-1:0]  alert_rx;
+  // Escalation outputs
+  prim_pkg::esc_tx_t [alert_pkg::N_ESC_SEV-1:0]  esc_tx;
+  prim_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0]  esc_rx;
+
+% if not top["alert"]:
+  for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_alert_tie_off
+    // tie off if no alerts present in the system
+    assign alert_tx[k].alert_p = 1'b0;
+    assign alert_tx[k].alert_n = 1'b1;
+  end
+% endif
+
   // clock assignments
 % for clock in top['clocks']:
   assign ${clock['name']}_clk = clk_i;
@@ -452,6 +468,7 @@
 % endfor
 ## Peripheral Instantiation
 
+<% alert_idx = 0 %>
 % for m in top["module"]:
 <%
 port_list = m["available_input_list"] + m["available_output_list"] + m["available_inout_list"]
@@ -511,6 +528,17 @@
       % endif
       .${lib.ljust("intr_"+intr["name"]+"_o",max_intrwidth+7)} (intr_${m["name"]}_${intr["name"]}),
     % endfor
+    % if m["alert_list"]:
+      <%
+      w = sum([x["width"] if "width" in x else 1 for x in m["alert_list"]])
+      slice = str(alert_idx+w-1) + ":" + str(alert_idx)
+      %>
+      % for alert in m["alert_list"] if "alert_list" in m else []:
+      // [${alert_idx}]: ${alert["name"]} <% alert_idx += 1 %>
+      % endfor
+      .alert_tx_o  ( alert_tx[${slice}] ),
+      .alert_rx_i  ( alert_rx[${slice}] ),
+    % endif
     ## TODO: Inter-module Connection
     % if m["type"] == "flash_ctrl":
 
@@ -534,11 +562,27 @@
       .mio_oe_o             (mio_oe_o ),
       .mio_in_i             (mio_in_i ),
     % endif
-
+    % if m["type"] == "alert_handler":
+      // TODO: wire this to hardware debug circuit
+      .crashdump_o (          ),
+      // TODO: wire this to TRNG
+      .entropy_i   ( 1'b0     ),
+      // alert signals
+      .alert_rx_o  ( alert_rx ),
+      .alert_tx_i  ( alert_tx ),
+      // escalation outputs
+      .esc_rx_i    ( esc_rx   ),
+      .esc_tx_o    ( esc_tx   ),
+    % endif
+    % if m["type"] == "nmi_gen":
+      // escalation signal inputs
+      .esc_rx_o    ( esc_rx   ),
+      .esc_tx_i    ( esc_tx   ),
+    % endif
     % if m["scan"] == "true":
       .scanmode_i   (scanmode_i),
-
     % endif
+
     % for k, v in m["clock_connections"].items():
       .${k} (${v}_clk),
     % endfor
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson
index ba15f45..1eff346 100644
--- a/hw/top_earlgrey/data/xbar_main.hjson
+++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -96,13 +96,27 @@
       base_addr: "0x40070000",
       size_byte: "0x1000",
       pipeline_byp: "false"
+    },
+    { name:      "alert_handler",
+      type:      "device",
+      clock:     "main",
+      inst_type: "alert_handler",
+      pipeline_byp: "false"
+    },
+    // dummy module to capture the alert handler escalation signals
+    // and test them by converting them into IRQs
+    { name:      "nmi_gen",
+      type:      "device",
+      clock:     "main",
+      inst_type: "nmi_gen",
+      pipeline_byp: "false"
     }
   ],
   connections: {
     corei:  ["rom", "debug_mem", "ram_main", "eflash"],
     cored:  ["rom", "debug_mem", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl",
-    "rv_timer", "aes", "hmac", "rv_plic", "pinmux"],
+    "rv_timer", "aes", "hmac", "rv_plic", "pinmux", "alert_handler", "nmi_gen"],
     dm_sba: ["rom",              "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl",
-    "rv_timer", "aes", "hmac", "rv_plic", "pinmux"],
+    "rv_timer", "aes", "hmac", "rv_plic", "pinmux", "alert_handler", "nmi_gen"],
   },
 }
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
new file mode 100644
index 0000000..c9390e9
--- /dev/null
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -0,0 +1,1252 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --alert-handler-only -o hw/top_earlgrey/
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# ALERT_HANDLER register template
+#
+# Parameter (given by python tool)
+#  - n_alerts:    Number of alert sources
+#  - esc_cnt_dw:  Width of escalation counter
+#  - accu_cnt_dw: Width of accumulator
+#  - lfsr_seed:   Seed for LFSR timer
+#  - async_on:    Enables asynchronous sygnalling between specific alert RX/TX pairs
+#  - n_classes:   Number of supported classes (leave this at 4 at the moment)
+
+{
+  name: "ALERT_HANDLER",
+  clock_primary: "clk_i",
+  bus_device: "tlul",
+  regwidth: "32",
+  param_list: [
+    { name: "NAlerts",
+      desc: "Number of peripheral inputs",
+      type: "int",
+      default: "1",
+      local: "true"
+    },
+    { name: "EscCntDw",
+      desc: "Number of peripheral outputs",
+      type: "int",
+      default: "32",
+      local: "true"
+    },
+    { name: "AccuCntDw",
+      desc: "Number of peripheral outputs",
+      type: "int",
+      default: "16",
+      local: "true"
+    },
+    { name: "LfsrSeed",
+      desc: "Number of peripheral outputs",
+      type: "int",
+      default: "2147483647",
+      local: "true"
+    },
+    { name: "AsyncOn",
+      desc: "Number of peripheral outputs",
+      type: "logic [NAlerts-1:0]",
+      default: "1'b0",
+      local: "true"
+    },
+    { name: "N_CLASSES",
+      desc: "Number of classes",
+      type: "int",
+      default: "4",
+      local: "true"
+    },
+    { name: "N_ESC_SEV",
+      desc: "Number of escalation severities",
+      type: "int",
+      default: "4",
+      local: "true"
+    },
+    { name: "N_PHASES",
+      desc: "Number of escalation phases",
+      type: "int",
+      default: "4",
+      local: "true"
+    },
+    { name: "N_LOC_ALERT",
+      desc: "Number of local alerts phases",
+      type: "int",
+      default: "4",
+      local: "true"
+    },
+    { name: "PING_CNT_DW",
+      desc: "Width of ping counter",
+      type: "int",
+      default: "24",
+      local: "true"
+    },
+    { name: "PHASE_DW",
+      desc: "Width of phase ID",
+      type: "int",
+      default: "2",
+      local: "true"
+    },
+    { name: "CLASS_DW",
+      desc: "Width of class ID",
+      type: "int",
+      default: "2",
+      local: "true"
+    },
+  ],
+# interrupt registers for the classes
+  interrupt_list: [
+    { name: "classa",
+      desc: '''
+            Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+            ''',
+    },
+    { name: "classb",
+      desc: '''
+            Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+            ''',
+    },
+    { name: "classc",
+      desc: '''
+            Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+            ''',
+    },
+    { name: "classd",
+      desc: '''
+            Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+            ''',
+    },
+  ],
+
+  registers: [
+# register locks for alerts and class configs
+    { name: "REGEN",
+      desc: '''
+            Register write enable for all control registers.
+            ''',
+      swaccess: "rw1c",
+      hwaccess: "hro",
+      fields: [
+        {
+            bits:   "0",
+            desc: ''' When true, the alert enable and escalation configuration registers can be modified.
+            When false, they become read-only. Defaults true, write one to clear. Note that this needs to be
+            cleared after initial configuration at boot in order to lock in the configuration and activate
+            the ping testing.
+            '''
+            resval: 1,
+        },
+      ]
+    },
+    { name:     "PING_TIMEOUT_CYC",
+      desc:     '''
+                Ping timeout cycle count.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        {
+          # TODO: add PING_CNT_DW parameter here
+          bits: "23:0",
+          resval:   32,
+          desc: '''Timeout value in cycles. If an alert receiver or an escalation sender does not
+          respond to a ping within this timeout window, a pingfail alert will be raised.
+          '''
+        }
+      ]
+    }
+# all alerts
+    { multireg: { name:     "ALERT_EN",
+                  desc:     '''Enable register for alerts.
+                  ''',
+                  count:    "NAlerts",
+                  swaccess: "rw",
+                  hwaccess: "hro",
+                  regwen:   "REGEN",
+                  cname:    "alert",
+                  fields: [
+                    { bits: "0",
+                      name: "EN_A",
+                      desc: "Alert enable "
+                    }
+                  ]
+                }
+    },
+    { multireg: { name:     "ALERT_CLASS",
+                  desc:     '''Class assignment of alerts.
+                  ''',
+                  count:    "NAlerts",
+                  swaccess: "rw",
+                  hwaccess: "hro",
+                  regwen:   "REGEN",
+                  cname:    "alert",
+                  fields: [
+                    {
+                      # TODO: bitwidth should be parameterized with CLASS_DW
+                      bits: "1:0",
+                      name: "CLASS_A",
+                      desc: "Classification ",
+                      enum: [
+                              { value: "0", name: "ClassA", desc: "" },
+                              { value: "1", name: "ClassB", desc: "" },
+                              { value: "2", name: "ClassC", desc: "" },
+                              { value: "3", name: "ClassD", desc: "" },
+                            ]
+                    }
+                  ]
+                }
+    },
+    { multireg: {
+      name: "ALERT_CAUSE",
+      desc: "Alert Cause Register",
+      count: "NAlerts",
+      cname: "ALERT",
+      swaccess: "rw1c",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0", name: "A", desc: "Cause bit " }
+      ]
+      }
+    },
+# local alerts
+    { multireg: { name:     "LOC_ALERT_EN",
+                  desc:     '''Enable register for the aggregated local alerts "alert
+                  pingfail" (0), "escalation pingfail" (1), "alert integfail" (2) and "escalation integfail" (3).
+                  ''',
+                  count:    "N_LOC_ALERT",
+                  swaccess: "rw",
+                  hwaccess: "hro",
+                  regwen:   "REGEN",
+                  cname:    "local alert",
+                  fields: [
+                    { bits: "0",
+                      name: "EN_LA",
+                      desc: "Alert enable "
+                    }
+                  ]
+                }
+    },
+    { multireg: { name:     "LOC_ALERT_CLASS",
+                  desc:     '''Class assignment of local alerts. "alert
+                  pingfail" (0), "escalation pingfail" (1), "alert integfail" (2) and "escalation integfail" (3).
+                  ''',
+                  count:    "N_LOC_ALERT",
+                  swaccess: "rw",
+                  hwaccess: "hro",
+                  regwen:   "REGEN",
+                  cname:    "local alert",
+                  fields: [
+                    {
+                      # TODO: bitwidth should be parameterized with CLASS_DW
+                      bits: "1:0",
+                      name: "CLASS_LA",
+                      desc: "Classification ",
+                      enum: [
+                              { value: "0", name: "ClassA", desc: "" },
+                              { value: "1", name: "ClassB", desc: "" },
+                              { value: "2", name: "ClassC", desc: "" },
+                              { value: "3", name: "ClassD", desc: "" },
+                            ]
+                    }
+                  ]
+                }
+    },
+    { multireg: {
+      name: "LOC_ALERT_CAUSE",
+      desc: '''Alert Cause Register for Local Alerts. "alert
+      pingfail" (0), "escalation pingfail" (1), "alert integfail" (2) and "escalation integfail" (3).
+      ''',
+      count: "N_LOC_ALERT",
+      cname: "LOC_ALERT",
+      swaccess: "rw1c",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0", name: "LA", desc: "Cause bit " }
+      ]
+      }
+    },
+# classes
+
+    { name:     "CLASSA_CTRL",
+      desc:     "Escalation control register for alert Class A. Can not be modified if !!REGEN is false."
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "0",
+          name: "EN",
+          desc: '''
+                Enable escalation mechanisms (accumulation and
+                interrupt timeout) for Class A. Note that interrupts can fire
+                regardless of whether the escalation mechanisms are enabled for
+                this class or not.
+                ''',
+        }
+        { bits: "1",
+          name: "LOCK",
+          desc: '''
+                Enable automatic locking of escalation counter for class A.
+                If true, there is no way to stop the escalation protocol for class A
+                once it has been triggered.
+                '''
+        }
+        { bits: "2",
+          name: "EN_E0",
+          resval: 1,
+          desc: "Enable escalation signal 0 for Class A",
+        }
+        { bits: "3",
+          name: "EN_E1",
+          resval: 1,
+          desc: "Enable escalation signal 1 for Class A",
+        }
+        { bits: "4",
+          name: "EN_E2",
+          resval: 1,
+          desc: "Enable escalation signal 2 for Class A",
+        }
+        { bits: "5",
+          name: "EN_E3",
+          resval: 1,
+          desc: "Enable escalation signal 3 for Class A",
+        }
+        # TODO: bitwidth should be parameterized with PHASE_DW
+        { bits: "7:6",
+          name: "MAP_E0",
+          resval: 0,
+          desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+        }
+        { bits: "9:8",
+          name: "MAP_E1",
+          resval: 1,
+          desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+        }
+        { bits: "11:10",
+          name: "MAP_E2",
+          resval: 2,
+          desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+        }
+        { bits: "13:12",
+          name: "MAP_E3",
+          resval: 3,
+          desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+        }
+      ]
+    },
+    { name:     "CLASSA_CLREN",
+      desc:     '''
+                Clear enable for escalation protocol of Class A alerts.
+                '''
+      swaccess: "rw1c",
+      hwaccess: "hwo",
+      fields: [
+      {   bits:   "0",
+          desc:   '''Register defaults to true, can only be cleared. This register is set
+          to false by the hardware if the escalation protocol has been triggered and the bit
+          !!CLASSA_CTRL.LOCK is true.
+          ''',
+          resval: 1,
+        }
+      ]
+    },
+    { name:     "CLASSA_CLR",
+      desc:     '''
+                Clear for esclation protocol of Class A.
+                '''
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe:     "true",
+      regwen:   "CLASSA_CLREN",
+      fields: [
+        { bits: "0",
+          desc: '''Writing to this register clears the accumulator and aborts escalation
+          (if it has been triggered). This clear is disabled if !!CLASSA_CLREN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSA_ACCUM_CNT",
+      desc:     '''
+                Current accumulation value for alert Class A. Software can clear this register
+                with a write to !!CLASSA_CLR register unless !!CLASSA_CLREN is false.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "15:0" }
+      ]
+    },
+    { name:     "CLASSA_ACCUM_THRESH",
+      desc:     '''
+                Accumulation threshold value for alert Class A.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "15:0",
+          desc: '''Once the accumulation value register is equal to the threshold escalation will
+          be triggered on the next alert occurrence within this class A begins. Note that this
+          register can not be modified if !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSA_TIMEOUT_CYC",
+      desc:     '''
+                Interrupt timeout in cycles.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0",
+          desc: '''If the interrupt corresponding to this class is not
+          handled within the specified amount of cycles, escalation will be triggered.
+          Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero
+          by default, which disables this feature. Note that this register can not be modified if
+          !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSA_PHASE0_CYC",
+      desc:     '''
+                Duration of escalation phase 0 for Class A.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSA_PHASE1_CYC",
+      desc:     '''
+                Duration of escalation phase 1 for Class A.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSA_PHASE2_CYC",
+      desc:     '''
+                Duration of escalation phase 2 for Class A.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSA_PHASE3_CYC",
+      desc:     '''
+                Duration of escalation phase 3 for Class A.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSA_ESC_CNT",
+      desc:     '''
+                Escalation counter in cycles for Class A.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "31:0",
+          desc: '''Returns the current timeout or escalation count (depending on !!CLASSA_STATE).
+          This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+          If the class is in the Timeout state, the timeout can be aborted by clearing the
+          corresponding interrupt bit.
+
+          If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+          aborted by writing to !!CLASSA_CLR. Note however that has no effect if !!CLASSA_CLREN
+          is set to false (either by SW or by HW via the !!CLASSA_CTRL.LOCK feature).
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSA_STATE",
+      desc:     '''
+                Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "2:0",
+          enum: [
+                  { value: "0b000", name: "Idle",     desc: "No timeout or escalation triggered." },
+                  { value: "0b001", name: "Timeout",  desc: "IRQ timeout counter is active." },
+                  { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+                  { value: "0b100", name: "Phase0",   desc: "Escalation Phase0 is active." },
+                  { value: "0b101", name: "Phase1",   desc: "Escalation Phase1 is active." },
+                  { value: "0b110", name: "Phase2",   desc: "Escalation Phase2 is active." },
+                  { value: "0b111", name: "Phase3",   desc: "Escalation Phase3 is active." }
+                ]
+        }
+      ]
+    },
+
+    { name:     "CLASSB_CTRL",
+      desc:     "Escalation control register for alert Class B. Can not be modified if !!REGEN is false."
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "0",
+          name: "EN",
+          desc: '''
+                Enable escalation mechanisms (accumulation and
+                interrupt timeout) for Class B. Note that interrupts can fire
+                regardless of whether the escalation mechanisms are enabled for
+                this class or not.
+                ''',
+        }
+        { bits: "1",
+          name: "LOCK",
+          desc: '''
+                Enable automatic locking of escalation counter for class B.
+                If true, there is no way to stop the escalation protocol for class B
+                once it has been triggered.
+                '''
+        }
+        { bits: "2",
+          name: "EN_E0",
+          resval: 1,
+          desc: "Enable escalation signal 0 for Class B",
+        }
+        { bits: "3",
+          name: "EN_E1",
+          resval: 1,
+          desc: "Enable escalation signal 1 for Class B",
+        }
+        { bits: "4",
+          name: "EN_E2",
+          resval: 1,
+          desc: "Enable escalation signal 2 for Class B",
+        }
+        { bits: "5",
+          name: "EN_E3",
+          resval: 1,
+          desc: "Enable escalation signal 3 for Class B",
+        }
+        # TODO: bitwidth should be parameterized with PHASE_DW
+        { bits: "7:6",
+          name: "MAP_E0",
+          resval: 0,
+          desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+        }
+        { bits: "9:8",
+          name: "MAP_E1",
+          resval: 1,
+          desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+        }
+        { bits: "11:10",
+          name: "MAP_E2",
+          resval: 2,
+          desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+        }
+        { bits: "13:12",
+          name: "MAP_E3",
+          resval: 3,
+          desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+        }
+      ]
+    },
+    { name:     "CLASSB_CLREN",
+      desc:     '''
+                Clear enable for escalation protocol of Class B alerts.
+                '''
+      swaccess: "rw1c",
+      hwaccess: "hwo",
+      fields: [
+      {   bits:   "0",
+          desc:   '''Register defaults to true, can only be cleared. This register is set
+          to false by the hardware if the escalation protocol has been triggered and the bit
+          !!CLASSB_CTRL.LOCK is true.
+          ''',
+          resval: 1,
+        }
+      ]
+    },
+    { name:     "CLASSB_CLR",
+      desc:     '''
+                Clear for esclation protocol of Class B.
+                '''
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe:     "true",
+      regwen:   "CLASSB_CLREN",
+      fields: [
+        { bits: "0",
+          desc: '''Writing to this register clears the accumulator and aborts escalation
+          (if it has been triggered). This clear is disabled if !!CLASSB_CLREN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSB_ACCUM_CNT",
+      desc:     '''
+                Current accumulation value for alert Class B. Software can clear this register
+                with a write to !!CLASSB_CLR register unless !!CLASSB_CLREN is false.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "15:0" }
+      ]
+    },
+    { name:     "CLASSB_ACCUM_THRESH",
+      desc:     '''
+                Accumulation threshold value for alert Class B.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "15:0",
+          desc: '''Once the accumulation value register is equal to the threshold escalation will
+          be triggered on the next alert occurrence within this class B begins. Note that this
+          register can not be modified if !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSB_TIMEOUT_CYC",
+      desc:     '''
+                Interrupt timeout in cycles.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0",
+          desc: '''If the interrupt corresponding to this class is not
+          handled within the specified amount of cycles, escalation will be triggered.
+          Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero
+          by default, which disables this feature. Note that this register can not be modified if
+          !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSB_PHASE0_CYC",
+      desc:     '''
+                Duration of escalation phase 0 for Class B.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSB_PHASE1_CYC",
+      desc:     '''
+                Duration of escalation phase 1 for Class B.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSB_PHASE2_CYC",
+      desc:     '''
+                Duration of escalation phase 2 for Class B.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSB_PHASE3_CYC",
+      desc:     '''
+                Duration of escalation phase 3 for Class B.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSB_ESC_CNT",
+      desc:     '''
+                Escalation counter in cycles for Class B.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "31:0",
+          desc: '''Returns the current timeout or escalation count (depending on !!CLASSB_STATE).
+          This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+          If the class is in the Timeout state, the timeout can be aborted by clearing the
+          corresponding interrupt bit.
+
+          If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+          aborted by writing to !!CLASSB_CLR. Note however that has no effect if !!CLASSB_CLREN
+          is set to false (either by SW or by HW via the !!CLASSB_CTRL.LOCK feature).
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSB_STATE",
+      desc:     '''
+                Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "2:0",
+          enum: [
+                  { value: "0b000", name: "Idle",     desc: "No timeout or escalation triggered." },
+                  { value: "0b001", name: "Timeout",  desc: "IRQ timeout counter is active." },
+                  { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+                  { value: "0b100", name: "Phase0",   desc: "Escalation Phase0 is active." },
+                  { value: "0b101", name: "Phase1",   desc: "Escalation Phase1 is active." },
+                  { value: "0b110", name: "Phase2",   desc: "Escalation Phase2 is active." },
+                  { value: "0b111", name: "Phase3",   desc: "Escalation Phase3 is active." }
+                ]
+        }
+      ]
+    },
+
+    { name:     "CLASSC_CTRL",
+      desc:     "Escalation control register for alert Class C. Can not be modified if !!REGEN is false."
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "0",
+          name: "EN",
+          desc: '''
+                Enable escalation mechanisms (accumulation and
+                interrupt timeout) for Class C. Note that interrupts can fire
+                regardless of whether the escalation mechanisms are enabled for
+                this class or not.
+                ''',
+        }
+        { bits: "1",
+          name: "LOCK",
+          desc: '''
+                Enable automatic locking of escalation counter for class C.
+                If true, there is no way to stop the escalation protocol for class C
+                once it has been triggered.
+                '''
+        }
+        { bits: "2",
+          name: "EN_E0",
+          resval: 1,
+          desc: "Enable escalation signal 0 for Class C",
+        }
+        { bits: "3",
+          name: "EN_E1",
+          resval: 1,
+          desc: "Enable escalation signal 1 for Class C",
+        }
+        { bits: "4",
+          name: "EN_E2",
+          resval: 1,
+          desc: "Enable escalation signal 2 for Class C",
+        }
+        { bits: "5",
+          name: "EN_E3",
+          resval: 1,
+          desc: "Enable escalation signal 3 for Class C",
+        }
+        # TODO: bitwidth should be parameterized with PHASE_DW
+        { bits: "7:6",
+          name: "MAP_E0",
+          resval: 0,
+          desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+        }
+        { bits: "9:8",
+          name: "MAP_E1",
+          resval: 1,
+          desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+        }
+        { bits: "11:10",
+          name: "MAP_E2",
+          resval: 2,
+          desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+        }
+        { bits: "13:12",
+          name: "MAP_E3",
+          resval: 3,
+          desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+        }
+      ]
+    },
+    { name:     "CLASSC_CLREN",
+      desc:     '''
+                Clear enable for escalation protocol of Class C alerts.
+                '''
+      swaccess: "rw1c",
+      hwaccess: "hwo",
+      fields: [
+      {   bits:   "0",
+          desc:   '''Register defaults to true, can only be cleared. This register is set
+          to false by the hardware if the escalation protocol has been triggered and the bit
+          !!CLASSC_CTRL.LOCK is true.
+          ''',
+          resval: 1,
+        }
+      ]
+    },
+    { name:     "CLASSC_CLR",
+      desc:     '''
+                Clear for esclation protocol of Class C.
+                '''
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe:     "true",
+      regwen:   "CLASSC_CLREN",
+      fields: [
+        { bits: "0",
+          desc: '''Writing to this register clears the accumulator and aborts escalation
+          (if it has been triggered). This clear is disabled if !!CLASSC_CLREN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSC_ACCUM_CNT",
+      desc:     '''
+                Current accumulation value for alert Class C. Software can clear this register
+                with a write to !!CLASSC_CLR register unless !!CLASSC_CLREN is false.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "15:0" }
+      ]
+    },
+    { name:     "CLASSC_ACCUM_THRESH",
+      desc:     '''
+                Accumulation threshold value for alert Class C.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "15:0",
+          desc: '''Once the accumulation value register is equal to the threshold escalation will
+          be triggered on the next alert occurrence within this class C begins. Note that this
+          register can not be modified if !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSC_TIMEOUT_CYC",
+      desc:     '''
+                Interrupt timeout in cycles.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0",
+          desc: '''If the interrupt corresponding to this class is not
+          handled within the specified amount of cycles, escalation will be triggered.
+          Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero
+          by default, which disables this feature. Note that this register can not be modified if
+          !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSC_PHASE0_CYC",
+      desc:     '''
+                Duration of escalation phase 0 for Class C.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSC_PHASE1_CYC",
+      desc:     '''
+                Duration of escalation phase 1 for Class C.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSC_PHASE2_CYC",
+      desc:     '''
+                Duration of escalation phase 2 for Class C.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSC_PHASE3_CYC",
+      desc:     '''
+                Duration of escalation phase 3 for Class C.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSC_ESC_CNT",
+      desc:     '''
+                Escalation counter in cycles for Class C.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "31:0",
+          desc: '''Returns the current timeout or escalation count (depending on !!CLASSC_STATE).
+          This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+          If the class is in the Timeout state, the timeout can be aborted by clearing the
+          corresponding interrupt bit.
+
+          If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+          aborted by writing to !!CLASSC_CLR. Note however that has no effect if !!CLASSC_CLREN
+          is set to false (either by SW or by HW via the !!CLASSC_CTRL.LOCK feature).
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSC_STATE",
+      desc:     '''
+                Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "2:0",
+          enum: [
+                  { value: "0b000", name: "Idle",     desc: "No timeout or escalation triggered." },
+                  { value: "0b001", name: "Timeout",  desc: "IRQ timeout counter is active." },
+                  { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+                  { value: "0b100", name: "Phase0",   desc: "Escalation Phase0 is active." },
+                  { value: "0b101", name: "Phase1",   desc: "Escalation Phase1 is active." },
+                  { value: "0b110", name: "Phase2",   desc: "Escalation Phase2 is active." },
+                  { value: "0b111", name: "Phase3",   desc: "Escalation Phase3 is active." }
+                ]
+        }
+      ]
+    },
+
+    { name:     "CLASSD_CTRL",
+      desc:     "Escalation control register for alert Class D. Can not be modified if !!REGEN is false."
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "0",
+          name: "EN",
+          desc: '''
+                Enable escalation mechanisms (accumulation and
+                interrupt timeout) for Class D. Note that interrupts can fire
+                regardless of whether the escalation mechanisms are enabled for
+                this class or not.
+                ''',
+        }
+        { bits: "1",
+          name: "LOCK",
+          desc: '''
+                Enable automatic locking of escalation counter for class D.
+                If true, there is no way to stop the escalation protocol for class D
+                once it has been triggered.
+                '''
+        }
+        { bits: "2",
+          name: "EN_E0",
+          resval: 1,
+          desc: "Enable escalation signal 0 for Class D",
+        }
+        { bits: "3",
+          name: "EN_E1",
+          resval: 1,
+          desc: "Enable escalation signal 1 for Class D",
+        }
+        { bits: "4",
+          name: "EN_E2",
+          resval: 1,
+          desc: "Enable escalation signal 2 for Class D",
+        }
+        { bits: "5",
+          name: "EN_E3",
+          resval: 1,
+          desc: "Enable escalation signal 3 for Class D",
+        }
+        # TODO: bitwidth should be parameterized with PHASE_DW
+        { bits: "7:6",
+          name: "MAP_E0",
+          resval: 0,
+          desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+        }
+        { bits: "9:8",
+          name: "MAP_E1",
+          resval: 1,
+          desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+        }
+        { bits: "11:10",
+          name: "MAP_E2",
+          resval: 2,
+          desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+        }
+        { bits: "13:12",
+          name: "MAP_E3",
+          resval: 3,
+          desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+        }
+      ]
+    },
+    { name:     "CLASSD_CLREN",
+      desc:     '''
+                Clear enable for escalation protocol of Class D alerts.
+                '''
+      swaccess: "rw1c",
+      hwaccess: "hwo",
+      fields: [
+      {   bits:   "0",
+          desc:   '''Register defaults to true, can only be cleared. This register is set
+          to false by the hardware if the escalation protocol has been triggered and the bit
+          !!CLASSD_CTRL.LOCK is true.
+          ''',
+          resval: 1,
+        }
+      ]
+    },
+    { name:     "CLASSD_CLR",
+      desc:     '''
+                Clear for esclation protocol of Class D.
+                '''
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe:     "true",
+      regwen:   "CLASSD_CLREN",
+      fields: [
+        { bits: "0",
+          desc: '''Writing to this register clears the accumulator and aborts escalation
+          (if it has been triggered). This clear is disabled if !!CLASSD_CLREN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSD_ACCUM_CNT",
+      desc:     '''
+                Current accumulation value for alert Class D. Software can clear this register
+                with a write to !!CLASSD_CLR register unless !!CLASSD_CLREN is false.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "15:0" }
+      ]
+    },
+    { name:     "CLASSD_ACCUM_THRESH",
+      desc:     '''
+                Accumulation threshold value for alert Class D.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "15:0",
+          desc: '''Once the accumulation value register is equal to the threshold escalation will
+          be triggered on the next alert occurrence within this class D begins. Note that this
+          register can not be modified if !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSD_TIMEOUT_CYC",
+      desc:     '''
+                Interrupt timeout in cycles.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0",
+          desc: '''If the interrupt corresponding to this class is not
+          handled within the specified amount of cycles, escalation will be triggered.
+          Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero
+          by default, which disables this feature. Note that this register can not be modified if
+          !!REGEN is false.
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSD_PHASE0_CYC",
+      desc:     '''
+                Duration of escalation phase 0 for Class D.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSD_PHASE1_CYC",
+      desc:     '''
+                Duration of escalation phase 1 for Class D.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSD_PHASE2_CYC",
+      desc:     '''
+                Duration of escalation phase 2 for Class D.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSD_PHASE3_CYC",
+      desc:     '''
+                Duration of escalation phase 3 for Class D.
+                '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen:   "REGEN",
+      fields: [
+        { bits: "31:0" ,
+          desc: '''Escalation phase duration in cycles. Note that this register can not be
+          modified if !!REGEN is false.'''
+        }
+      ]
+    }
+    { name:     "CLASSD_ESC_CNT",
+      desc:     '''
+                Escalation counter in cycles for Class D.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "31:0",
+          desc: '''Returns the current timeout or escalation count (depending on !!CLASSD_STATE).
+          This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+          If the class is in the Timeout state, the timeout can be aborted by clearing the
+          corresponding interrupt bit.
+
+          If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+          aborted by writing to !!CLASSD_CLR. Note however that has no effect if !!CLASSD_CLREN
+          is set to false (either by SW or by HW via the !!CLASSD_CTRL.LOCK feature).
+          '''
+        }
+      ]
+    },
+    { name:     "CLASSD_STATE",
+      desc:     '''
+                Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
+                '''
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "2:0",
+          enum: [
+                  { value: "0b000", name: "Idle",     desc: "No timeout or escalation triggered." },
+                  { value: "0b001", name: "Timeout",  desc: "IRQ timeout counter is active." },
+                  { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+                  { value: "0b100", name: "Phase0",   desc: "Escalation Phase0 is active." },
+                  { value: "0b101", name: "Phase1",   desc: "Escalation Phase1 is active." },
+                  { value: "0b110", name: "Phase2",   desc: "Escalation Phase2 is active." },
+                  { value: "0b111", name: "Phase3",   desc: "Escalation Phase3 is active." }
+                ]
+        }
+      ]
+    },
+  ],
+}
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
new file mode 100644
index 0000000..56ad460
--- /dev/null
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -0,0 +1,716 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package alert_handler_reg_pkg;
+
+  // Param list
+  localparam int NAlerts = 1;
+  localparam int EscCntDw = 32;
+  localparam int AccuCntDw = 16;
+  localparam int LfsrSeed = 2147483647;
+  localparam logic [NAlerts-1:0] AsyncOn = 1'b0;
+  localparam int N_CLASSES = 4;
+  localparam int N_ESC_SEV = 4;
+  localparam int N_PHASES = 4;
+  localparam int N_LOC_ALERT = 4;
+  localparam int PING_CNT_DW = 24;
+  localparam int PHASE_DW = 2;
+  localparam int CLASS_DW = 2;
+
+  ////////////////////////////
+  // Typedefs for registers //
+  ////////////////////////////
+  typedef struct packed {
+    struct packed {
+      logic        q;
+    } classa;
+    struct packed {
+      logic        q;
+    } classb;
+    struct packed {
+      logic        q;
+    } classc;
+    struct packed {
+      logic        q;
+    } classd;
+  } alert_handler_reg2hw_intr_state_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic        q;
+    } classa;
+    struct packed {
+      logic        q;
+    } classb;
+    struct packed {
+      logic        q;
+    } classc;
+    struct packed {
+      logic        q;
+    } classd;
+  } alert_handler_reg2hw_intr_enable_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic        q;
+      logic        qe;
+    } classa;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } classb;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } classc;
+    struct packed {
+      logic        q;
+      logic        qe;
+    } classd;
+  } alert_handler_reg2hw_intr_test_reg_t;
+
+  typedef struct packed {
+    logic        q;
+  } alert_handler_reg2hw_regen_reg_t;
+
+  typedef struct packed {
+    logic [23:0] q;
+  } alert_handler_reg2hw_ping_timeout_cyc_reg_t;
+
+  typedef struct packed {
+    logic        q;
+  } alert_handler_reg2hw_alert_en_mreg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } alert_handler_reg2hw_alert_class_mreg_t;
+
+  typedef struct packed {
+    logic        q;
+  } alert_handler_reg2hw_alert_cause_mreg_t;
+
+  typedef struct packed {
+    logic        q;
+  } alert_handler_reg2hw_loc_alert_en_mreg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } alert_handler_reg2hw_loc_alert_class_mreg_t;
+
+  typedef struct packed {
+    logic        q;
+  } alert_handler_reg2hw_loc_alert_cause_mreg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic        q;
+    } en;
+    struct packed {
+      logic        q;
+    } lock;
+    struct packed {
+      logic        q;
+    } en_e0;
+    struct packed {
+      logic        q;
+    } en_e1;
+    struct packed {
+      logic        q;
+    } en_e2;
+    struct packed {
+      logic        q;
+    } en_e3;
+    struct packed {
+      logic [1:0]  q;
+    } map_e0;
+    struct packed {
+      logic [1:0]  q;
+    } map_e1;
+    struct packed {
+      logic [1:0]  q;
+    } map_e2;
+    struct packed {
+      logic [1:0]  q;
+    } map_e3;
+  } alert_handler_reg2hw_classa_ctrl_reg_t;
+
+  typedef struct packed {
+    logic        q;
+    logic        qe;
+  } alert_handler_reg2hw_classa_clr_reg_t;
+
+  typedef struct packed {
+    logic [15:0] q;
+  } alert_handler_reg2hw_classa_accum_thresh_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classa_timeout_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classa_phase0_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classa_phase1_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classa_phase2_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classa_phase3_cyc_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic        q;
+    } en;
+    struct packed {
+      logic        q;
+    } lock;
+    struct packed {
+      logic        q;
+    } en_e0;
+    struct packed {
+      logic        q;
+    } en_e1;
+    struct packed {
+      logic        q;
+    } en_e2;
+    struct packed {
+      logic        q;
+    } en_e3;
+    struct packed {
+      logic [1:0]  q;
+    } map_e0;
+    struct packed {
+      logic [1:0]  q;
+    } map_e1;
+    struct packed {
+      logic [1:0]  q;
+    } map_e2;
+    struct packed {
+      logic [1:0]  q;
+    } map_e3;
+  } alert_handler_reg2hw_classb_ctrl_reg_t;
+
+  typedef struct packed {
+    logic        q;
+    logic        qe;
+  } alert_handler_reg2hw_classb_clr_reg_t;
+
+  typedef struct packed {
+    logic [15:0] q;
+  } alert_handler_reg2hw_classb_accum_thresh_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classb_timeout_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classb_phase0_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classb_phase1_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classb_phase2_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classb_phase3_cyc_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic        q;
+    } en;
+    struct packed {
+      logic        q;
+    } lock;
+    struct packed {
+      logic        q;
+    } en_e0;
+    struct packed {
+      logic        q;
+    } en_e1;
+    struct packed {
+      logic        q;
+    } en_e2;
+    struct packed {
+      logic        q;
+    } en_e3;
+    struct packed {
+      logic [1:0]  q;
+    } map_e0;
+    struct packed {
+      logic [1:0]  q;
+    } map_e1;
+    struct packed {
+      logic [1:0]  q;
+    } map_e2;
+    struct packed {
+      logic [1:0]  q;
+    } map_e3;
+  } alert_handler_reg2hw_classc_ctrl_reg_t;
+
+  typedef struct packed {
+    logic        q;
+    logic        qe;
+  } alert_handler_reg2hw_classc_clr_reg_t;
+
+  typedef struct packed {
+    logic [15:0] q;
+  } alert_handler_reg2hw_classc_accum_thresh_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classc_timeout_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classc_phase0_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classc_phase1_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classc_phase2_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classc_phase3_cyc_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic        q;
+    } en;
+    struct packed {
+      logic        q;
+    } lock;
+    struct packed {
+      logic        q;
+    } en_e0;
+    struct packed {
+      logic        q;
+    } en_e1;
+    struct packed {
+      logic        q;
+    } en_e2;
+    struct packed {
+      logic        q;
+    } en_e3;
+    struct packed {
+      logic [1:0]  q;
+    } map_e0;
+    struct packed {
+      logic [1:0]  q;
+    } map_e1;
+    struct packed {
+      logic [1:0]  q;
+    } map_e2;
+    struct packed {
+      logic [1:0]  q;
+    } map_e3;
+  } alert_handler_reg2hw_classd_ctrl_reg_t;
+
+  typedef struct packed {
+    logic        q;
+    logic        qe;
+  } alert_handler_reg2hw_classd_clr_reg_t;
+
+  typedef struct packed {
+    logic [15:0] q;
+  } alert_handler_reg2hw_classd_accum_thresh_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classd_timeout_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classd_phase0_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classd_phase1_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classd_phase2_cyc_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+  } alert_handler_reg2hw_classd_phase3_cyc_reg_t;
+
+
+  typedef struct packed {
+    struct packed {
+      logic        d;
+      logic        de;
+    } classa;
+    struct packed {
+      logic        d;
+      logic        de;
+    } classb;
+    struct packed {
+      logic        d;
+      logic        de;
+    } classc;
+    struct packed {
+      logic        d;
+      logic        de;
+    } classd;
+  } alert_handler_hw2reg_intr_state_reg_t;
+
+  typedef struct packed {
+    logic        d;
+    logic        de;
+  } alert_handler_hw2reg_alert_cause_mreg_t;
+
+  typedef struct packed {
+    logic        d;
+    logic        de;
+  } alert_handler_hw2reg_loc_alert_cause_mreg_t;
+
+  typedef struct packed {
+    logic        d;
+    logic        de;
+  } alert_handler_hw2reg_classa_clren_reg_t;
+
+  typedef struct packed {
+    logic [15:0] d;
+  } alert_handler_hw2reg_classa_accum_cnt_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+  } alert_handler_hw2reg_classa_esc_cnt_reg_t;
+
+  typedef struct packed {
+    logic [2:0]  d;
+  } alert_handler_hw2reg_classa_state_reg_t;
+
+  typedef struct packed {
+    logic        d;
+    logic        de;
+  } alert_handler_hw2reg_classb_clren_reg_t;
+
+  typedef struct packed {
+    logic [15:0] d;
+  } alert_handler_hw2reg_classb_accum_cnt_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+  } alert_handler_hw2reg_classb_esc_cnt_reg_t;
+
+  typedef struct packed {
+    logic [2:0]  d;
+  } alert_handler_hw2reg_classb_state_reg_t;
+
+  typedef struct packed {
+    logic        d;
+    logic        de;
+  } alert_handler_hw2reg_classc_clren_reg_t;
+
+  typedef struct packed {
+    logic [15:0] d;
+  } alert_handler_hw2reg_classc_accum_cnt_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+  } alert_handler_hw2reg_classc_esc_cnt_reg_t;
+
+  typedef struct packed {
+    logic [2:0]  d;
+  } alert_handler_hw2reg_classc_state_reg_t;
+
+  typedef struct packed {
+    logic        d;
+    logic        de;
+  } alert_handler_hw2reg_classd_clren_reg_t;
+
+  typedef struct packed {
+    logic [15:0] d;
+  } alert_handler_hw2reg_classd_accum_cnt_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+  } alert_handler_hw2reg_classd_esc_cnt_reg_t;
+
+  typedef struct packed {
+    logic [2:0]  d;
+  } alert_handler_hw2reg_classd_state_reg_t;
+
+
+  ///////////////////////////////////////
+  // Register to internal design logic //
+  ///////////////////////////////////////
+  typedef struct packed {
+    alert_handler_reg2hw_intr_state_reg_t intr_state; // [828:825]
+    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [824:821]
+    alert_handler_reg2hw_intr_test_reg_t intr_test; // [820:813]
+    alert_handler_reg2hw_regen_reg_t regen; // [812:812]
+    alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [811:788]
+    alert_handler_reg2hw_alert_en_mreg_t [0:0] alert_en; // [787:787]
+    alert_handler_reg2hw_alert_class_mreg_t [0:0] alert_class; // [786:785]
+    alert_handler_reg2hw_alert_cause_mreg_t [0:0] alert_cause; // [784:784]
+    alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
+    alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
+    alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
+    alert_handler_reg2hw_classa_ctrl_reg_t classa_ctrl; // [767:754]
+    alert_handler_reg2hw_classa_clr_reg_t classa_clr; // [753:752]
+    alert_handler_reg2hw_classa_accum_thresh_reg_t classa_accum_thresh; // [751:736]
+    alert_handler_reg2hw_classa_timeout_cyc_reg_t classa_timeout_cyc; // [735:704]
+    alert_handler_reg2hw_classa_phase0_cyc_reg_t classa_phase0_cyc; // [703:672]
+    alert_handler_reg2hw_classa_phase1_cyc_reg_t classa_phase1_cyc; // [671:640]
+    alert_handler_reg2hw_classa_phase2_cyc_reg_t classa_phase2_cyc; // [639:608]
+    alert_handler_reg2hw_classa_phase3_cyc_reg_t classa_phase3_cyc; // [607:576]
+    alert_handler_reg2hw_classb_ctrl_reg_t classb_ctrl; // [575:562]
+    alert_handler_reg2hw_classb_clr_reg_t classb_clr; // [561:560]
+    alert_handler_reg2hw_classb_accum_thresh_reg_t classb_accum_thresh; // [559:544]
+    alert_handler_reg2hw_classb_timeout_cyc_reg_t classb_timeout_cyc; // [543:512]
+    alert_handler_reg2hw_classb_phase0_cyc_reg_t classb_phase0_cyc; // [511:480]
+    alert_handler_reg2hw_classb_phase1_cyc_reg_t classb_phase1_cyc; // [479:448]
+    alert_handler_reg2hw_classb_phase2_cyc_reg_t classb_phase2_cyc; // [447:416]
+    alert_handler_reg2hw_classb_phase3_cyc_reg_t classb_phase3_cyc; // [415:384]
+    alert_handler_reg2hw_classc_ctrl_reg_t classc_ctrl; // [383:370]
+    alert_handler_reg2hw_classc_clr_reg_t classc_clr; // [369:368]
+    alert_handler_reg2hw_classc_accum_thresh_reg_t classc_accum_thresh; // [367:352]
+    alert_handler_reg2hw_classc_timeout_cyc_reg_t classc_timeout_cyc; // [351:320]
+    alert_handler_reg2hw_classc_phase0_cyc_reg_t classc_phase0_cyc; // [319:288]
+    alert_handler_reg2hw_classc_phase1_cyc_reg_t classc_phase1_cyc; // [287:256]
+    alert_handler_reg2hw_classc_phase2_cyc_reg_t classc_phase2_cyc; // [255:224]
+    alert_handler_reg2hw_classc_phase3_cyc_reg_t classc_phase3_cyc; // [223:192]
+    alert_handler_reg2hw_classd_ctrl_reg_t classd_ctrl; // [191:178]
+    alert_handler_reg2hw_classd_clr_reg_t classd_clr; // [177:176]
+    alert_handler_reg2hw_classd_accum_thresh_reg_t classd_accum_thresh; // [175:160]
+    alert_handler_reg2hw_classd_timeout_cyc_reg_t classd_timeout_cyc; // [159:128]
+    alert_handler_reg2hw_classd_phase0_cyc_reg_t classd_phase0_cyc; // [127:96]
+    alert_handler_reg2hw_classd_phase1_cyc_reg_t classd_phase1_cyc; // [95:64]
+    alert_handler_reg2hw_classd_phase2_cyc_reg_t classd_phase2_cyc; // [63:32]
+    alert_handler_reg2hw_classd_phase3_cyc_reg_t classd_phase3_cyc; // [31:0]
+  } alert_handler_reg2hw_t;
+
+  ///////////////////////////////////////
+  // Internal design logic to register //
+  ///////////////////////////////////////
+  typedef struct packed {
+    alert_handler_hw2reg_intr_state_reg_t intr_state; // [229:226]
+    alert_handler_hw2reg_alert_cause_mreg_t [0:0] alert_cause; // [225:224]
+    alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [223:216]
+    alert_handler_hw2reg_classa_clren_reg_t classa_clren; // [215:216]
+    alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [215:216]
+    alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt; // [215:216]
+    alert_handler_hw2reg_classa_state_reg_t classa_state; // [215:216]
+    alert_handler_hw2reg_classb_clren_reg_t classb_clren; // [215:216]
+    alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt; // [215:216]
+    alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt; // [215:216]
+    alert_handler_hw2reg_classb_state_reg_t classb_state; // [215:216]
+    alert_handler_hw2reg_classc_clren_reg_t classc_clren; // [215:216]
+    alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt; // [215:216]
+    alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt; // [215:216]
+    alert_handler_hw2reg_classc_state_reg_t classc_state; // [215:216]
+    alert_handler_hw2reg_classd_clren_reg_t classd_clren; // [215:216]
+    alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt; // [215:216]
+    alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt; // [215:216]
+    alert_handler_hw2reg_classd_state_reg_t classd_state; // [215:216]
+  } alert_handler_hw2reg_t;
+
+  // Register Address
+  parameter ALERT_HANDLER_INTR_STATE_OFFSET = 8'h 0;
+  parameter ALERT_HANDLER_INTR_ENABLE_OFFSET = 8'h 4;
+  parameter ALERT_HANDLER_INTR_TEST_OFFSET = 8'h 8;
+  parameter ALERT_HANDLER_REGEN_OFFSET = 8'h c;
+  parameter ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 8'h 10;
+  parameter ALERT_HANDLER_ALERT_EN_OFFSET = 8'h 14;
+  parameter ALERT_HANDLER_ALERT_CLASS_OFFSET = 8'h 18;
+  parameter ALERT_HANDLER_ALERT_CAUSE_OFFSET = 8'h 1c;
+  parameter ALERT_HANDLER_LOC_ALERT_EN_OFFSET = 8'h 20;
+  parameter ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET = 8'h 24;
+  parameter ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET = 8'h 28;
+  parameter ALERT_HANDLER_CLASSA_CTRL_OFFSET = 8'h 2c;
+  parameter ALERT_HANDLER_CLASSA_CLREN_OFFSET = 8'h 30;
+  parameter ALERT_HANDLER_CLASSA_CLR_OFFSET = 8'h 34;
+  parameter ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 8'h 38;
+  parameter ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 8'h 3c;
+  parameter ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 8'h 40;
+  parameter ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 8'h 44;
+  parameter ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 8'h 48;
+  parameter ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 8'h 4c;
+  parameter ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 8'h 50;
+  parameter ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 8'h 54;
+  parameter ALERT_HANDLER_CLASSA_STATE_OFFSET = 8'h 58;
+  parameter ALERT_HANDLER_CLASSB_CTRL_OFFSET = 8'h 5c;
+  parameter ALERT_HANDLER_CLASSB_CLREN_OFFSET = 8'h 60;
+  parameter ALERT_HANDLER_CLASSB_CLR_OFFSET = 8'h 64;
+  parameter ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 8'h 68;
+  parameter ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 8'h 6c;
+  parameter ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 8'h 70;
+  parameter ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 8'h 74;
+  parameter ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 8'h 78;
+  parameter ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 8'h 7c;
+  parameter ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 8'h 80;
+  parameter ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 8'h 84;
+  parameter ALERT_HANDLER_CLASSB_STATE_OFFSET = 8'h 88;
+  parameter ALERT_HANDLER_CLASSC_CTRL_OFFSET = 8'h 8c;
+  parameter ALERT_HANDLER_CLASSC_CLREN_OFFSET = 8'h 90;
+  parameter ALERT_HANDLER_CLASSC_CLR_OFFSET = 8'h 94;
+  parameter ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 8'h 98;
+  parameter ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 8'h 9c;
+  parameter ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 8'h a0;
+  parameter ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 8'h a4;
+  parameter ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 8'h a8;
+  parameter ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 8'h ac;
+  parameter ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 8'h b0;
+  parameter ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 8'h b4;
+  parameter ALERT_HANDLER_CLASSC_STATE_OFFSET = 8'h b8;
+  parameter ALERT_HANDLER_CLASSD_CTRL_OFFSET = 8'h bc;
+  parameter ALERT_HANDLER_CLASSD_CLREN_OFFSET = 8'h c0;
+  parameter ALERT_HANDLER_CLASSD_CLR_OFFSET = 8'h c4;
+  parameter ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 8'h c8;
+  parameter ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 8'h cc;
+  parameter ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 8'h d0;
+  parameter ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 8'h d4;
+  parameter ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 8'h d8;
+  parameter ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 8'h dc;
+  parameter ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 8'h e0;
+  parameter ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 8'h e4;
+  parameter ALERT_HANDLER_CLASSD_STATE_OFFSET = 8'h e8;
+
+
+  // Register Index
+  typedef enum int {
+    ALERT_HANDLER_INTR_STATE,
+    ALERT_HANDLER_INTR_ENABLE,
+    ALERT_HANDLER_INTR_TEST,
+    ALERT_HANDLER_REGEN,
+    ALERT_HANDLER_PING_TIMEOUT_CYC,
+    ALERT_HANDLER_ALERT_EN,
+    ALERT_HANDLER_ALERT_CLASS,
+    ALERT_HANDLER_ALERT_CAUSE,
+    ALERT_HANDLER_LOC_ALERT_EN,
+    ALERT_HANDLER_LOC_ALERT_CLASS,
+    ALERT_HANDLER_LOC_ALERT_CAUSE,
+    ALERT_HANDLER_CLASSA_CTRL,
+    ALERT_HANDLER_CLASSA_CLREN,
+    ALERT_HANDLER_CLASSA_CLR,
+    ALERT_HANDLER_CLASSA_ACCUM_CNT,
+    ALERT_HANDLER_CLASSA_ACCUM_THRESH,
+    ALERT_HANDLER_CLASSA_TIMEOUT_CYC,
+    ALERT_HANDLER_CLASSA_PHASE0_CYC,
+    ALERT_HANDLER_CLASSA_PHASE1_CYC,
+    ALERT_HANDLER_CLASSA_PHASE2_CYC,
+    ALERT_HANDLER_CLASSA_PHASE3_CYC,
+    ALERT_HANDLER_CLASSA_ESC_CNT,
+    ALERT_HANDLER_CLASSA_STATE,
+    ALERT_HANDLER_CLASSB_CTRL,
+    ALERT_HANDLER_CLASSB_CLREN,
+    ALERT_HANDLER_CLASSB_CLR,
+    ALERT_HANDLER_CLASSB_ACCUM_CNT,
+    ALERT_HANDLER_CLASSB_ACCUM_THRESH,
+    ALERT_HANDLER_CLASSB_TIMEOUT_CYC,
+    ALERT_HANDLER_CLASSB_PHASE0_CYC,
+    ALERT_HANDLER_CLASSB_PHASE1_CYC,
+    ALERT_HANDLER_CLASSB_PHASE2_CYC,
+    ALERT_HANDLER_CLASSB_PHASE3_CYC,
+    ALERT_HANDLER_CLASSB_ESC_CNT,
+    ALERT_HANDLER_CLASSB_STATE,
+    ALERT_HANDLER_CLASSC_CTRL,
+    ALERT_HANDLER_CLASSC_CLREN,
+    ALERT_HANDLER_CLASSC_CLR,
+    ALERT_HANDLER_CLASSC_ACCUM_CNT,
+    ALERT_HANDLER_CLASSC_ACCUM_THRESH,
+    ALERT_HANDLER_CLASSC_TIMEOUT_CYC,
+    ALERT_HANDLER_CLASSC_PHASE0_CYC,
+    ALERT_HANDLER_CLASSC_PHASE1_CYC,
+    ALERT_HANDLER_CLASSC_PHASE2_CYC,
+    ALERT_HANDLER_CLASSC_PHASE3_CYC,
+    ALERT_HANDLER_CLASSC_ESC_CNT,
+    ALERT_HANDLER_CLASSC_STATE,
+    ALERT_HANDLER_CLASSD_CTRL,
+    ALERT_HANDLER_CLASSD_CLREN,
+    ALERT_HANDLER_CLASSD_CLR,
+    ALERT_HANDLER_CLASSD_ACCUM_CNT,
+    ALERT_HANDLER_CLASSD_ACCUM_THRESH,
+    ALERT_HANDLER_CLASSD_TIMEOUT_CYC,
+    ALERT_HANDLER_CLASSD_PHASE0_CYC,
+    ALERT_HANDLER_CLASSD_PHASE1_CYC,
+    ALERT_HANDLER_CLASSD_PHASE2_CYC,
+    ALERT_HANDLER_CLASSD_PHASE3_CYC,
+    ALERT_HANDLER_CLASSD_ESC_CNT,
+    ALERT_HANDLER_CLASSD_STATE
+  } alert_handler_id_e;
+
+  // Register width information to check illegal writes
+  localparam logic [3:0] ALERT_HANDLER_PERMIT [59] = '{
+    4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
+    4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
+    4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
+    4'b 0001, // index[ 3] ALERT_HANDLER_REGEN
+    4'b 0111, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC
+    4'b 0001, // index[ 5] ALERT_HANDLER_ALERT_EN
+    4'b 0001, // index[ 6] ALERT_HANDLER_ALERT_CLASS
+    4'b 0001, // index[ 7] ALERT_HANDLER_ALERT_CAUSE
+    4'b 0001, // index[ 8] ALERT_HANDLER_LOC_ALERT_EN
+    4'b 0001, // index[ 9] ALERT_HANDLER_LOC_ALERT_CLASS
+    4'b 0001, // index[10] ALERT_HANDLER_LOC_ALERT_CAUSE
+    4'b 0011, // index[11] ALERT_HANDLER_CLASSA_CTRL
+    4'b 0001, // index[12] ALERT_HANDLER_CLASSA_CLREN
+    4'b 0001, // index[13] ALERT_HANDLER_CLASSA_CLR
+    4'b 0011, // index[14] ALERT_HANDLER_CLASSA_ACCUM_CNT
+    4'b 0011, // index[15] ALERT_HANDLER_CLASSA_ACCUM_THRESH
+    4'b 1111, // index[16] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
+    4'b 1111, // index[17] ALERT_HANDLER_CLASSA_PHASE0_CYC
+    4'b 1111, // index[18] ALERT_HANDLER_CLASSA_PHASE1_CYC
+    4'b 1111, // index[19] ALERT_HANDLER_CLASSA_PHASE2_CYC
+    4'b 1111, // index[20] ALERT_HANDLER_CLASSA_PHASE3_CYC
+    4'b 1111, // index[21] ALERT_HANDLER_CLASSA_ESC_CNT
+    4'b 0001, // index[22] ALERT_HANDLER_CLASSA_STATE
+    4'b 0011, // index[23] ALERT_HANDLER_CLASSB_CTRL
+    4'b 0001, // index[24] ALERT_HANDLER_CLASSB_CLREN
+    4'b 0001, // index[25] ALERT_HANDLER_CLASSB_CLR
+    4'b 0011, // index[26] ALERT_HANDLER_CLASSB_ACCUM_CNT
+    4'b 0011, // index[27] ALERT_HANDLER_CLASSB_ACCUM_THRESH
+    4'b 1111, // index[28] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
+    4'b 1111, // index[29] ALERT_HANDLER_CLASSB_PHASE0_CYC
+    4'b 1111, // index[30] ALERT_HANDLER_CLASSB_PHASE1_CYC
+    4'b 1111, // index[31] ALERT_HANDLER_CLASSB_PHASE2_CYC
+    4'b 1111, // index[32] ALERT_HANDLER_CLASSB_PHASE3_CYC
+    4'b 1111, // index[33] ALERT_HANDLER_CLASSB_ESC_CNT
+    4'b 0001, // index[34] ALERT_HANDLER_CLASSB_STATE
+    4'b 0011, // index[35] ALERT_HANDLER_CLASSC_CTRL
+    4'b 0001, // index[36] ALERT_HANDLER_CLASSC_CLREN
+    4'b 0001, // index[37] ALERT_HANDLER_CLASSC_CLR
+    4'b 0011, // index[38] ALERT_HANDLER_CLASSC_ACCUM_CNT
+    4'b 0011, // index[39] ALERT_HANDLER_CLASSC_ACCUM_THRESH
+    4'b 1111, // index[40] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
+    4'b 1111, // index[41] ALERT_HANDLER_CLASSC_PHASE0_CYC
+    4'b 1111, // index[42] ALERT_HANDLER_CLASSC_PHASE1_CYC
+    4'b 1111, // index[43] ALERT_HANDLER_CLASSC_PHASE2_CYC
+    4'b 1111, // index[44] ALERT_HANDLER_CLASSC_PHASE3_CYC
+    4'b 1111, // index[45] ALERT_HANDLER_CLASSC_ESC_CNT
+    4'b 0001, // index[46] ALERT_HANDLER_CLASSC_STATE
+    4'b 0011, // index[47] ALERT_HANDLER_CLASSD_CTRL
+    4'b 0001, // index[48] ALERT_HANDLER_CLASSD_CLREN
+    4'b 0001, // index[49] ALERT_HANDLER_CLASSD_CLR
+    4'b 0011, // index[50] ALERT_HANDLER_CLASSD_ACCUM_CNT
+    4'b 0011, // index[51] ALERT_HANDLER_CLASSD_ACCUM_THRESH
+    4'b 1111, // index[52] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
+    4'b 1111, // index[53] ALERT_HANDLER_CLASSD_PHASE0_CYC
+    4'b 1111, // index[54] ALERT_HANDLER_CLASSD_PHASE1_CYC
+    4'b 1111, // index[55] ALERT_HANDLER_CLASSD_PHASE2_CYC
+    4'b 1111, // index[56] ALERT_HANDLER_CLASSD_PHASE3_CYC
+    4'b 1111, // index[57] ALERT_HANDLER_CLASSD_ESC_CNT
+    4'b 0001  // index[58] ALERT_HANDLER_CLASSD_STATE
+  };
+endpackage
+
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
new file mode 100644
index 0000000..b267bb6
--- /dev/null
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -0,0 +1,4006 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+module alert_handler_reg_top (
+  input clk_i,
+  input rst_ni,
+
+  // Below Regster interface can be changed
+  input  tlul_pkg::tl_h2d_t tl_i,
+  output tlul_pkg::tl_d2h_t tl_o,
+  // To HW
+  output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
+  input  alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read
+
+  // Config
+  input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+  import alert_handler_reg_pkg::* ;
+
+  localparam AW = 8;
+  localparam DW = 32;
+  localparam DBW = DW/8;                    // Byte Width
+
+  // register signals
+  logic           reg_we;
+  logic           reg_re;
+  logic [AW-1:0]  reg_addr;
+  logic [DW-1:0]  reg_wdata;
+  logic [DBW-1:0] reg_be;
+  logic [DW-1:0]  reg_rdata;
+  logic           reg_error;
+
+  logic          addrmiss, wr_err;
+
+  logic [DW-1:0] reg_rdata_next;
+
+  tlul_pkg::tl_h2d_t tl_reg_h2d;
+  tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+  assign tl_reg_h2d = tl_i;
+  assign tl_o       = tl_reg_d2h;
+
+  tlul_adapter_reg #(
+    .RegAw(AW),
+    .RegDw(DW)
+  ) u_reg_if (
+    .clk_i,
+    .rst_ni,
+
+    .tl_i (tl_reg_h2d),
+    .tl_o (tl_reg_d2h),
+
+    .we_o    (reg_we),
+    .re_o    (reg_re),
+    .addr_o  (reg_addr),
+    .wdata_o (reg_wdata),
+    .be_o    (reg_be),
+    .rdata_i (reg_rdata),
+    .error_i (reg_error)
+  );
+
+  assign reg_rdata = reg_rdata_next ;
+  assign reg_error = (devmode_i & addrmiss) | wr_err ;
+
+  // Define SW related signals
+  // Format: <reg>_<field>_{wd|we|qs}
+  //        or <reg>_{wd|we|qs} if field == 1 or 0
+  logic intr_state_classa_qs;
+  logic intr_state_classa_wd;
+  logic intr_state_classa_we;
+  logic intr_state_classb_qs;
+  logic intr_state_classb_wd;
+  logic intr_state_classb_we;
+  logic intr_state_classc_qs;
+  logic intr_state_classc_wd;
+  logic intr_state_classc_we;
+  logic intr_state_classd_qs;
+  logic intr_state_classd_wd;
+  logic intr_state_classd_we;
+  logic intr_enable_classa_qs;
+  logic intr_enable_classa_wd;
+  logic intr_enable_classa_we;
+  logic intr_enable_classb_qs;
+  logic intr_enable_classb_wd;
+  logic intr_enable_classb_we;
+  logic intr_enable_classc_qs;
+  logic intr_enable_classc_wd;
+  logic intr_enable_classc_we;
+  logic intr_enable_classd_qs;
+  logic intr_enable_classd_wd;
+  logic intr_enable_classd_we;
+  logic intr_test_classa_wd;
+  logic intr_test_classa_we;
+  logic intr_test_classb_wd;
+  logic intr_test_classb_we;
+  logic intr_test_classc_wd;
+  logic intr_test_classc_we;
+  logic intr_test_classd_wd;
+  logic intr_test_classd_we;
+  logic regen_qs;
+  logic regen_wd;
+  logic regen_we;
+  logic [23:0] ping_timeout_cyc_qs;
+  logic [23:0] ping_timeout_cyc_wd;
+  logic ping_timeout_cyc_we;
+  logic alert_en_qs;
+  logic alert_en_wd;
+  logic alert_en_we;
+  logic [1:0] alert_class_qs;
+  logic [1:0] alert_class_wd;
+  logic alert_class_we;
+  logic alert_cause_qs;
+  logic alert_cause_wd;
+  logic alert_cause_we;
+  logic loc_alert_en_en_la0_qs;
+  logic loc_alert_en_en_la0_wd;
+  logic loc_alert_en_en_la0_we;
+  logic loc_alert_en_en_la1_qs;
+  logic loc_alert_en_en_la1_wd;
+  logic loc_alert_en_en_la1_we;
+  logic loc_alert_en_en_la2_qs;
+  logic loc_alert_en_en_la2_wd;
+  logic loc_alert_en_en_la2_we;
+  logic loc_alert_en_en_la3_qs;
+  logic loc_alert_en_en_la3_wd;
+  logic loc_alert_en_en_la3_we;
+  logic [1:0] loc_alert_class_class_la0_qs;
+  logic [1:0] loc_alert_class_class_la0_wd;
+  logic loc_alert_class_class_la0_we;
+  logic [1:0] loc_alert_class_class_la1_qs;
+  logic [1:0] loc_alert_class_class_la1_wd;
+  logic loc_alert_class_class_la1_we;
+  logic [1:0] loc_alert_class_class_la2_qs;
+  logic [1:0] loc_alert_class_class_la2_wd;
+  logic loc_alert_class_class_la2_we;
+  logic [1:0] loc_alert_class_class_la3_qs;
+  logic [1:0] loc_alert_class_class_la3_wd;
+  logic loc_alert_class_class_la3_we;
+  logic loc_alert_cause_la0_qs;
+  logic loc_alert_cause_la0_wd;
+  logic loc_alert_cause_la0_we;
+  logic loc_alert_cause_la1_qs;
+  logic loc_alert_cause_la1_wd;
+  logic loc_alert_cause_la1_we;
+  logic loc_alert_cause_la2_qs;
+  logic loc_alert_cause_la2_wd;
+  logic loc_alert_cause_la2_we;
+  logic loc_alert_cause_la3_qs;
+  logic loc_alert_cause_la3_wd;
+  logic loc_alert_cause_la3_we;
+  logic classa_ctrl_en_qs;
+  logic classa_ctrl_en_wd;
+  logic classa_ctrl_en_we;
+  logic classa_ctrl_lock_qs;
+  logic classa_ctrl_lock_wd;
+  logic classa_ctrl_lock_we;
+  logic classa_ctrl_en_e0_qs;
+  logic classa_ctrl_en_e0_wd;
+  logic classa_ctrl_en_e0_we;
+  logic classa_ctrl_en_e1_qs;
+  logic classa_ctrl_en_e1_wd;
+  logic classa_ctrl_en_e1_we;
+  logic classa_ctrl_en_e2_qs;
+  logic classa_ctrl_en_e2_wd;
+  logic classa_ctrl_en_e2_we;
+  logic classa_ctrl_en_e3_qs;
+  logic classa_ctrl_en_e3_wd;
+  logic classa_ctrl_en_e3_we;
+  logic [1:0] classa_ctrl_map_e0_qs;
+  logic [1:0] classa_ctrl_map_e0_wd;
+  logic classa_ctrl_map_e0_we;
+  logic [1:0] classa_ctrl_map_e1_qs;
+  logic [1:0] classa_ctrl_map_e1_wd;
+  logic classa_ctrl_map_e1_we;
+  logic [1:0] classa_ctrl_map_e2_qs;
+  logic [1:0] classa_ctrl_map_e2_wd;
+  logic classa_ctrl_map_e2_we;
+  logic [1:0] classa_ctrl_map_e3_qs;
+  logic [1:0] classa_ctrl_map_e3_wd;
+  logic classa_ctrl_map_e3_we;
+  logic classa_clren_qs;
+  logic classa_clren_wd;
+  logic classa_clren_we;
+  logic classa_clr_wd;
+  logic classa_clr_we;
+  logic [15:0] classa_accum_cnt_qs;
+  logic classa_accum_cnt_re;
+  logic [15:0] classa_accum_thresh_qs;
+  logic [15:0] classa_accum_thresh_wd;
+  logic classa_accum_thresh_we;
+  logic [31:0] classa_timeout_cyc_qs;
+  logic [31:0] classa_timeout_cyc_wd;
+  logic classa_timeout_cyc_we;
+  logic [31:0] classa_phase0_cyc_qs;
+  logic [31:0] classa_phase0_cyc_wd;
+  logic classa_phase0_cyc_we;
+  logic [31:0] classa_phase1_cyc_qs;
+  logic [31:0] classa_phase1_cyc_wd;
+  logic classa_phase1_cyc_we;
+  logic [31:0] classa_phase2_cyc_qs;
+  logic [31:0] classa_phase2_cyc_wd;
+  logic classa_phase2_cyc_we;
+  logic [31:0] classa_phase3_cyc_qs;
+  logic [31:0] classa_phase3_cyc_wd;
+  logic classa_phase3_cyc_we;
+  logic [31:0] classa_esc_cnt_qs;
+  logic classa_esc_cnt_re;
+  logic [2:0] classa_state_qs;
+  logic classa_state_re;
+  logic classb_ctrl_en_qs;
+  logic classb_ctrl_en_wd;
+  logic classb_ctrl_en_we;
+  logic classb_ctrl_lock_qs;
+  logic classb_ctrl_lock_wd;
+  logic classb_ctrl_lock_we;
+  logic classb_ctrl_en_e0_qs;
+  logic classb_ctrl_en_e0_wd;
+  logic classb_ctrl_en_e0_we;
+  logic classb_ctrl_en_e1_qs;
+  logic classb_ctrl_en_e1_wd;
+  logic classb_ctrl_en_e1_we;
+  logic classb_ctrl_en_e2_qs;
+  logic classb_ctrl_en_e2_wd;
+  logic classb_ctrl_en_e2_we;
+  logic classb_ctrl_en_e3_qs;
+  logic classb_ctrl_en_e3_wd;
+  logic classb_ctrl_en_e3_we;
+  logic [1:0] classb_ctrl_map_e0_qs;
+  logic [1:0] classb_ctrl_map_e0_wd;
+  logic classb_ctrl_map_e0_we;
+  logic [1:0] classb_ctrl_map_e1_qs;
+  logic [1:0] classb_ctrl_map_e1_wd;
+  logic classb_ctrl_map_e1_we;
+  logic [1:0] classb_ctrl_map_e2_qs;
+  logic [1:0] classb_ctrl_map_e2_wd;
+  logic classb_ctrl_map_e2_we;
+  logic [1:0] classb_ctrl_map_e3_qs;
+  logic [1:0] classb_ctrl_map_e3_wd;
+  logic classb_ctrl_map_e3_we;
+  logic classb_clren_qs;
+  logic classb_clren_wd;
+  logic classb_clren_we;
+  logic classb_clr_wd;
+  logic classb_clr_we;
+  logic [15:0] classb_accum_cnt_qs;
+  logic classb_accum_cnt_re;
+  logic [15:0] classb_accum_thresh_qs;
+  logic [15:0] classb_accum_thresh_wd;
+  logic classb_accum_thresh_we;
+  logic [31:0] classb_timeout_cyc_qs;
+  logic [31:0] classb_timeout_cyc_wd;
+  logic classb_timeout_cyc_we;
+  logic [31:0] classb_phase0_cyc_qs;
+  logic [31:0] classb_phase0_cyc_wd;
+  logic classb_phase0_cyc_we;
+  logic [31:0] classb_phase1_cyc_qs;
+  logic [31:0] classb_phase1_cyc_wd;
+  logic classb_phase1_cyc_we;
+  logic [31:0] classb_phase2_cyc_qs;
+  logic [31:0] classb_phase2_cyc_wd;
+  logic classb_phase2_cyc_we;
+  logic [31:0] classb_phase3_cyc_qs;
+  logic [31:0] classb_phase3_cyc_wd;
+  logic classb_phase3_cyc_we;
+  logic [31:0] classb_esc_cnt_qs;
+  logic classb_esc_cnt_re;
+  logic [2:0] classb_state_qs;
+  logic classb_state_re;
+  logic classc_ctrl_en_qs;
+  logic classc_ctrl_en_wd;
+  logic classc_ctrl_en_we;
+  logic classc_ctrl_lock_qs;
+  logic classc_ctrl_lock_wd;
+  logic classc_ctrl_lock_we;
+  logic classc_ctrl_en_e0_qs;
+  logic classc_ctrl_en_e0_wd;
+  logic classc_ctrl_en_e0_we;
+  logic classc_ctrl_en_e1_qs;
+  logic classc_ctrl_en_e1_wd;
+  logic classc_ctrl_en_e1_we;
+  logic classc_ctrl_en_e2_qs;
+  logic classc_ctrl_en_e2_wd;
+  logic classc_ctrl_en_e2_we;
+  logic classc_ctrl_en_e3_qs;
+  logic classc_ctrl_en_e3_wd;
+  logic classc_ctrl_en_e3_we;
+  logic [1:0] classc_ctrl_map_e0_qs;
+  logic [1:0] classc_ctrl_map_e0_wd;
+  logic classc_ctrl_map_e0_we;
+  logic [1:0] classc_ctrl_map_e1_qs;
+  logic [1:0] classc_ctrl_map_e1_wd;
+  logic classc_ctrl_map_e1_we;
+  logic [1:0] classc_ctrl_map_e2_qs;
+  logic [1:0] classc_ctrl_map_e2_wd;
+  logic classc_ctrl_map_e2_we;
+  logic [1:0] classc_ctrl_map_e3_qs;
+  logic [1:0] classc_ctrl_map_e3_wd;
+  logic classc_ctrl_map_e3_we;
+  logic classc_clren_qs;
+  logic classc_clren_wd;
+  logic classc_clren_we;
+  logic classc_clr_wd;
+  logic classc_clr_we;
+  logic [15:0] classc_accum_cnt_qs;
+  logic classc_accum_cnt_re;
+  logic [15:0] classc_accum_thresh_qs;
+  logic [15:0] classc_accum_thresh_wd;
+  logic classc_accum_thresh_we;
+  logic [31:0] classc_timeout_cyc_qs;
+  logic [31:0] classc_timeout_cyc_wd;
+  logic classc_timeout_cyc_we;
+  logic [31:0] classc_phase0_cyc_qs;
+  logic [31:0] classc_phase0_cyc_wd;
+  logic classc_phase0_cyc_we;
+  logic [31:0] classc_phase1_cyc_qs;
+  logic [31:0] classc_phase1_cyc_wd;
+  logic classc_phase1_cyc_we;
+  logic [31:0] classc_phase2_cyc_qs;
+  logic [31:0] classc_phase2_cyc_wd;
+  logic classc_phase2_cyc_we;
+  logic [31:0] classc_phase3_cyc_qs;
+  logic [31:0] classc_phase3_cyc_wd;
+  logic classc_phase3_cyc_we;
+  logic [31:0] classc_esc_cnt_qs;
+  logic classc_esc_cnt_re;
+  logic [2:0] classc_state_qs;
+  logic classc_state_re;
+  logic classd_ctrl_en_qs;
+  logic classd_ctrl_en_wd;
+  logic classd_ctrl_en_we;
+  logic classd_ctrl_lock_qs;
+  logic classd_ctrl_lock_wd;
+  logic classd_ctrl_lock_we;
+  logic classd_ctrl_en_e0_qs;
+  logic classd_ctrl_en_e0_wd;
+  logic classd_ctrl_en_e0_we;
+  logic classd_ctrl_en_e1_qs;
+  logic classd_ctrl_en_e1_wd;
+  logic classd_ctrl_en_e1_we;
+  logic classd_ctrl_en_e2_qs;
+  logic classd_ctrl_en_e2_wd;
+  logic classd_ctrl_en_e2_we;
+  logic classd_ctrl_en_e3_qs;
+  logic classd_ctrl_en_e3_wd;
+  logic classd_ctrl_en_e3_we;
+  logic [1:0] classd_ctrl_map_e0_qs;
+  logic [1:0] classd_ctrl_map_e0_wd;
+  logic classd_ctrl_map_e0_we;
+  logic [1:0] classd_ctrl_map_e1_qs;
+  logic [1:0] classd_ctrl_map_e1_wd;
+  logic classd_ctrl_map_e1_we;
+  logic [1:0] classd_ctrl_map_e2_qs;
+  logic [1:0] classd_ctrl_map_e2_wd;
+  logic classd_ctrl_map_e2_we;
+  logic [1:0] classd_ctrl_map_e3_qs;
+  logic [1:0] classd_ctrl_map_e3_wd;
+  logic classd_ctrl_map_e3_we;
+  logic classd_clren_qs;
+  logic classd_clren_wd;
+  logic classd_clren_we;
+  logic classd_clr_wd;
+  logic classd_clr_we;
+  logic [15:0] classd_accum_cnt_qs;
+  logic classd_accum_cnt_re;
+  logic [15:0] classd_accum_thresh_qs;
+  logic [15:0] classd_accum_thresh_wd;
+  logic classd_accum_thresh_we;
+  logic [31:0] classd_timeout_cyc_qs;
+  logic [31:0] classd_timeout_cyc_wd;
+  logic classd_timeout_cyc_we;
+  logic [31:0] classd_phase0_cyc_qs;
+  logic [31:0] classd_phase0_cyc_wd;
+  logic classd_phase0_cyc_we;
+  logic [31:0] classd_phase1_cyc_qs;
+  logic [31:0] classd_phase1_cyc_wd;
+  logic classd_phase1_cyc_we;
+  logic [31:0] classd_phase2_cyc_qs;
+  logic [31:0] classd_phase2_cyc_wd;
+  logic classd_phase2_cyc_we;
+  logic [31:0] classd_phase3_cyc_qs;
+  logic [31:0] classd_phase3_cyc_wd;
+  logic classd_phase3_cyc_we;
+  logic [31:0] classd_esc_cnt_qs;
+  logic classd_esc_cnt_re;
+  logic [2:0] classd_state_qs;
+  logic classd_state_re;
+
+  // Register instances
+  // R[intr_state]: V(False)
+
+  //   F[classa]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_intr_state_classa (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_state_classa_we),
+    .wd     (intr_state_classa_wd),
+
+    // from internal hardware
+    .de     (hw2reg.intr_state.classa.de),
+    .d      (hw2reg.intr_state.classa.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_state.classa.q ),
+
+    // to register interface (read)
+    .qs     (intr_state_classa_qs)
+  );
+
+
+  //   F[classb]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_intr_state_classb (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_state_classb_we),
+    .wd     (intr_state_classb_wd),
+
+    // from internal hardware
+    .de     (hw2reg.intr_state.classb.de),
+    .d      (hw2reg.intr_state.classb.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_state.classb.q ),
+
+    // to register interface (read)
+    .qs     (intr_state_classb_qs)
+  );
+
+
+  //   F[classc]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_intr_state_classc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_state_classc_we),
+    .wd     (intr_state_classc_wd),
+
+    // from internal hardware
+    .de     (hw2reg.intr_state.classc.de),
+    .d      (hw2reg.intr_state.classc.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_state.classc.q ),
+
+    // to register interface (read)
+    .qs     (intr_state_classc_qs)
+  );
+
+
+  //   F[classd]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_intr_state_classd (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_state_classd_we),
+    .wd     (intr_state_classd_wd),
+
+    // from internal hardware
+    .de     (hw2reg.intr_state.classd.de),
+    .d      (hw2reg.intr_state.classd.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_state.classd.q ),
+
+    // to register interface (read)
+    .qs     (intr_state_classd_qs)
+  );
+
+
+  // R[intr_enable]: V(False)
+
+  //   F[classa]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_intr_enable_classa (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_enable_classa_we),
+    .wd     (intr_enable_classa_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_enable.classa.q ),
+
+    // to register interface (read)
+    .qs     (intr_enable_classa_qs)
+  );
+
+
+  //   F[classb]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_intr_enable_classb (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_enable_classb_we),
+    .wd     (intr_enable_classb_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_enable.classb.q ),
+
+    // to register interface (read)
+    .qs     (intr_enable_classb_qs)
+  );
+
+
+  //   F[classc]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_intr_enable_classc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_enable_classc_we),
+    .wd     (intr_enable_classc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_enable.classc.q ),
+
+    // to register interface (read)
+    .qs     (intr_enable_classc_qs)
+  );
+
+
+  //   F[classd]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_intr_enable_classd (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (intr_enable_classd_we),
+    .wd     (intr_enable_classd_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.intr_enable.classd.q ),
+
+    // to register interface (read)
+    .qs     (intr_enable_classd_qs)
+  );
+
+
+  // R[intr_test]: V(True)
+
+  //   F[classa]: 0:0
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_intr_test_classa (
+    .re     (1'b0),
+    .we     (intr_test_classa_we),
+    .wd     (intr_test_classa_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (reg2hw.intr_test.classa.qe),
+    .q      (reg2hw.intr_test.classa.q ),
+    .qs     ()
+  );
+
+
+  //   F[classb]: 1:1
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_intr_test_classb (
+    .re     (1'b0),
+    .we     (intr_test_classb_we),
+    .wd     (intr_test_classb_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (reg2hw.intr_test.classb.qe),
+    .q      (reg2hw.intr_test.classb.q ),
+    .qs     ()
+  );
+
+
+  //   F[classc]: 2:2
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_intr_test_classc (
+    .re     (1'b0),
+    .we     (intr_test_classc_we),
+    .wd     (intr_test_classc_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (reg2hw.intr_test.classc.qe),
+    .q      (reg2hw.intr_test.classc.q ),
+    .qs     ()
+  );
+
+
+  //   F[classd]: 3:3
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_intr_test_classd (
+    .re     (1'b0),
+    .we     (intr_test_classd_we),
+    .wd     (intr_test_classd_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (reg2hw.intr_test.classd.qe),
+    .q      (reg2hw.intr_test.classd.q ),
+    .qs     ()
+  );
+
+
+  // R[regen]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h1)
+  ) u_regen (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (regen_we),
+    .wd     (regen_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.regen.q ),
+
+    // to register interface (read)
+    .qs     (regen_qs)
+  );
+
+
+  // R[ping_timeout_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (24),
+    .SWACCESS("RW"),
+    .RESVAL  (24'h20)
+  ) u_ping_timeout_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (ping_timeout_cyc_we & regen_qs),
+    .wd     (ping_timeout_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ping_timeout_cyc.q ),
+
+    // to register interface (read)
+    .qs     (ping_timeout_cyc_qs)
+  );
+
+
+
+  // Subregister 0 of Multireg alert_en
+  // R[alert_en]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (alert_en_we & regen_qs),
+    .wd     (alert_en_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[0].q ),
+
+    // to register interface (read)
+    .qs     (alert_en_qs)
+  );
+
+
+
+  // Subregister 0 of Multireg alert_class
+  // R[alert_class]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (alert_class_we & regen_qs),
+    .wd     (alert_class_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[0].q ),
+
+    // to register interface (read)
+    .qs     (alert_class_qs)
+  );
+
+
+
+  // Subregister 0 of Multireg alert_cause
+  // R[alert_cause]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (alert_cause_we),
+    .wd     (alert_cause_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[0].de),
+    .d      (hw2reg.alert_cause[0].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[0].q ),
+
+    // to register interface (read)
+    .qs     (alert_cause_qs)
+  );
+
+
+
+  // Subregister 0 of Multireg loc_alert_en
+  // R[loc_alert_en]: V(False)
+
+  // F[en_la0]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_en_en_la0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_en_en_la0_we & regen_qs),
+    .wd     (loc_alert_en_en_la0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_en[0].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_en_en_la0_qs)
+  );
+
+
+  // F[en_la1]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_en_en_la1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_en_en_la1_we & regen_qs),
+    .wd     (loc_alert_en_en_la1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_en[1].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_en_en_la1_qs)
+  );
+
+
+  // F[en_la2]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_en_en_la2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_en_en_la2_we & regen_qs),
+    .wd     (loc_alert_en_en_la2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_en[2].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_en_en_la2_qs)
+  );
+
+
+  // F[en_la3]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_en_en_la3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_en_en_la3_we & regen_qs),
+    .wd     (loc_alert_en_en_la3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_en[3].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_en_en_la3_qs)
+  );
+
+
+
+
+  // Subregister 0 of Multireg loc_alert_class
+  // R[loc_alert_class]: V(False)
+
+  // F[class_la0]: 1:0
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_loc_alert_class_class_la0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_class_class_la0_we & regen_qs),
+    .wd     (loc_alert_class_class_la0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_class[0].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_class_class_la0_qs)
+  );
+
+
+  // F[class_la1]: 3:2
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_loc_alert_class_class_la1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_class_class_la1_we & regen_qs),
+    .wd     (loc_alert_class_class_la1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_class[1].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_class_class_la1_qs)
+  );
+
+
+  // F[class_la2]: 5:4
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_loc_alert_class_class_la2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_class_class_la2_we & regen_qs),
+    .wd     (loc_alert_class_class_la2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_class[2].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_class_class_la2_qs)
+  );
+
+
+  // F[class_la3]: 7:6
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_loc_alert_class_class_la3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (loc_alert_class_class_la3_we & regen_qs),
+    .wd     (loc_alert_class_class_la3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_class[3].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_class_class_la3_qs)
+  );
+
+
+
+
+  // Subregister 0 of Multireg loc_alert_cause
+  // R[loc_alert_cause]: V(False)
+
+  // F[la0]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_cause_la0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (loc_alert_cause_la0_we),
+    .wd     (loc_alert_cause_la0_wd),
+
+    // from internal hardware
+    .de     (hw2reg.loc_alert_cause[0].de),
+    .d      (hw2reg.loc_alert_cause[0].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_cause[0].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_cause_la0_qs)
+  );
+
+
+  // F[la1]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_cause_la1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (loc_alert_cause_la1_we),
+    .wd     (loc_alert_cause_la1_wd),
+
+    // from internal hardware
+    .de     (hw2reg.loc_alert_cause[1].de),
+    .d      (hw2reg.loc_alert_cause[1].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_cause[1].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_cause_la1_qs)
+  );
+
+
+  // F[la2]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_cause_la2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (loc_alert_cause_la2_we),
+    .wd     (loc_alert_cause_la2_wd),
+
+    // from internal hardware
+    .de     (hw2reg.loc_alert_cause[2].de),
+    .d      (hw2reg.loc_alert_cause[2].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_cause[2].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_cause_la2_qs)
+  );
+
+
+  // F[la3]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_loc_alert_cause_la3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (loc_alert_cause_la3_we),
+    .wd     (loc_alert_cause_la3_wd),
+
+    // from internal hardware
+    .de     (hw2reg.loc_alert_cause[3].de),
+    .d      (hw2reg.loc_alert_cause[3].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.loc_alert_cause[3].q ),
+
+    // to register interface (read)
+    .qs     (loc_alert_cause_la3_qs)
+  );
+
+
+
+  // R[classa_ctrl]: V(False)
+
+  //   F[en]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classa_ctrl_en (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_en_we & regen_qs),
+    .wd     (classa_ctrl_en_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.en.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_en_qs)
+  );
+
+
+  //   F[lock]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classa_ctrl_lock (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_lock_we & regen_qs),
+    .wd     (classa_ctrl_lock_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.lock.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_lock_qs)
+  );
+
+
+  //   F[en_e0]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classa_ctrl_en_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_en_e0_we & regen_qs),
+    .wd     (classa_ctrl_en_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.en_e0.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_en_e0_qs)
+  );
+
+
+  //   F[en_e1]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classa_ctrl_en_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_en_e1_we & regen_qs),
+    .wd     (classa_ctrl_en_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.en_e1.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_en_e1_qs)
+  );
+
+
+  //   F[en_e2]: 4:4
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classa_ctrl_en_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_en_e2_we & regen_qs),
+    .wd     (classa_ctrl_en_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.en_e2.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_en_e2_qs)
+  );
+
+
+  //   F[en_e3]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classa_ctrl_en_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_en_e3_we & regen_qs),
+    .wd     (classa_ctrl_en_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.en_e3.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_en_e3_qs)
+  );
+
+
+  //   F[map_e0]: 7:6
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_classa_ctrl_map_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_map_e0_we & regen_qs),
+    .wd     (classa_ctrl_map_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.map_e0.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_map_e0_qs)
+  );
+
+
+  //   F[map_e1]: 9:8
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h1)
+  ) u_classa_ctrl_map_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_map_e1_we & regen_qs),
+    .wd     (classa_ctrl_map_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.map_e1.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_map_e1_qs)
+  );
+
+
+  //   F[map_e2]: 11:10
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_classa_ctrl_map_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_map_e2_we & regen_qs),
+    .wd     (classa_ctrl_map_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.map_e2.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_map_e2_qs)
+  );
+
+
+  //   F[map_e3]: 13:12
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h3)
+  ) u_classa_ctrl_map_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_ctrl_map_e3_we & regen_qs),
+    .wd     (classa_ctrl_map_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_ctrl.map_e3.q ),
+
+    // to register interface (read)
+    .qs     (classa_ctrl_map_e3_qs)
+  );
+
+
+  // R[classa_clren]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h1)
+  ) u_classa_clren (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (classa_clren_we),
+    .wd     (classa_clren_wd),
+
+    // from internal hardware
+    .de     (hw2reg.classa_clren.de),
+    .d      (hw2reg.classa_clren.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (classa_clren_qs)
+  );
+
+
+  // R[classa_clr]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("WO"),
+    .RESVAL  (1'h0)
+  ) u_classa_clr (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_clr_we & classa_clren_qs),
+    .wd     (classa_clr_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (reg2hw.classa_clr.qe),
+    .q      (reg2hw.classa_clr.q ),
+
+    .qs     ()
+  );
+
+
+  // R[classa_accum_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (16)
+  ) u_classa_accum_cnt (
+    .re     (classa_accum_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classa_accum_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classa_accum_cnt_qs)
+  );
+
+
+  // R[classa_accum_thresh]: V(False)
+
+  prim_subreg #(
+    .DW      (16),
+    .SWACCESS("RW"),
+    .RESVAL  (16'h0)
+  ) u_classa_accum_thresh (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_accum_thresh_we & regen_qs),
+    .wd     (classa_accum_thresh_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_accum_thresh.q ),
+
+    // to register interface (read)
+    .qs     (classa_accum_thresh_qs)
+  );
+
+
+  // R[classa_timeout_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classa_timeout_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_timeout_cyc_we & regen_qs),
+    .wd     (classa_timeout_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_timeout_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classa_timeout_cyc_qs)
+  );
+
+
+  // R[classa_phase0_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classa_phase0_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_phase0_cyc_we & regen_qs),
+    .wd     (classa_phase0_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_phase0_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classa_phase0_cyc_qs)
+  );
+
+
+  // R[classa_phase1_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classa_phase1_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_phase1_cyc_we & regen_qs),
+    .wd     (classa_phase1_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_phase1_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classa_phase1_cyc_qs)
+  );
+
+
+  // R[classa_phase2_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classa_phase2_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_phase2_cyc_we & regen_qs),
+    .wd     (classa_phase2_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_phase2_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classa_phase2_cyc_qs)
+  );
+
+
+  // R[classa_phase3_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classa_phase3_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classa_phase3_cyc_we & regen_qs),
+    .wd     (classa_phase3_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classa_phase3_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classa_phase3_cyc_qs)
+  );
+
+
+  // R[classa_esc_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (32)
+  ) u_classa_esc_cnt (
+    .re     (classa_esc_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classa_esc_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classa_esc_cnt_qs)
+  );
+
+
+  // R[classa_state]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (3)
+  ) u_classa_state (
+    .re     (classa_state_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classa_state.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classa_state_qs)
+  );
+
+
+  // R[classb_ctrl]: V(False)
+
+  //   F[en]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classb_ctrl_en (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_en_we & regen_qs),
+    .wd     (classb_ctrl_en_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.en.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_en_qs)
+  );
+
+
+  //   F[lock]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classb_ctrl_lock (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_lock_we & regen_qs),
+    .wd     (classb_ctrl_lock_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.lock.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_lock_qs)
+  );
+
+
+  //   F[en_e0]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classb_ctrl_en_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_en_e0_we & regen_qs),
+    .wd     (classb_ctrl_en_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.en_e0.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_en_e0_qs)
+  );
+
+
+  //   F[en_e1]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classb_ctrl_en_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_en_e1_we & regen_qs),
+    .wd     (classb_ctrl_en_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.en_e1.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_en_e1_qs)
+  );
+
+
+  //   F[en_e2]: 4:4
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classb_ctrl_en_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_en_e2_we & regen_qs),
+    .wd     (classb_ctrl_en_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.en_e2.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_en_e2_qs)
+  );
+
+
+  //   F[en_e3]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classb_ctrl_en_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_en_e3_we & regen_qs),
+    .wd     (classb_ctrl_en_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.en_e3.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_en_e3_qs)
+  );
+
+
+  //   F[map_e0]: 7:6
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_classb_ctrl_map_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_map_e0_we & regen_qs),
+    .wd     (classb_ctrl_map_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.map_e0.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_map_e0_qs)
+  );
+
+
+  //   F[map_e1]: 9:8
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h1)
+  ) u_classb_ctrl_map_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_map_e1_we & regen_qs),
+    .wd     (classb_ctrl_map_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.map_e1.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_map_e1_qs)
+  );
+
+
+  //   F[map_e2]: 11:10
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_classb_ctrl_map_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_map_e2_we & regen_qs),
+    .wd     (classb_ctrl_map_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.map_e2.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_map_e2_qs)
+  );
+
+
+  //   F[map_e3]: 13:12
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h3)
+  ) u_classb_ctrl_map_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_ctrl_map_e3_we & regen_qs),
+    .wd     (classb_ctrl_map_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_ctrl.map_e3.q ),
+
+    // to register interface (read)
+    .qs     (classb_ctrl_map_e3_qs)
+  );
+
+
+  // R[classb_clren]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h1)
+  ) u_classb_clren (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (classb_clren_we),
+    .wd     (classb_clren_wd),
+
+    // from internal hardware
+    .de     (hw2reg.classb_clren.de),
+    .d      (hw2reg.classb_clren.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (classb_clren_qs)
+  );
+
+
+  // R[classb_clr]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("WO"),
+    .RESVAL  (1'h0)
+  ) u_classb_clr (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_clr_we & classb_clren_qs),
+    .wd     (classb_clr_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (reg2hw.classb_clr.qe),
+    .q      (reg2hw.classb_clr.q ),
+
+    .qs     ()
+  );
+
+
+  // R[classb_accum_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (16)
+  ) u_classb_accum_cnt (
+    .re     (classb_accum_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classb_accum_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classb_accum_cnt_qs)
+  );
+
+
+  // R[classb_accum_thresh]: V(False)
+
+  prim_subreg #(
+    .DW      (16),
+    .SWACCESS("RW"),
+    .RESVAL  (16'h0)
+  ) u_classb_accum_thresh (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_accum_thresh_we & regen_qs),
+    .wd     (classb_accum_thresh_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_accum_thresh.q ),
+
+    // to register interface (read)
+    .qs     (classb_accum_thresh_qs)
+  );
+
+
+  // R[classb_timeout_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classb_timeout_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_timeout_cyc_we & regen_qs),
+    .wd     (classb_timeout_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_timeout_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classb_timeout_cyc_qs)
+  );
+
+
+  // R[classb_phase0_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classb_phase0_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_phase0_cyc_we & regen_qs),
+    .wd     (classb_phase0_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_phase0_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classb_phase0_cyc_qs)
+  );
+
+
+  // R[classb_phase1_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classb_phase1_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_phase1_cyc_we & regen_qs),
+    .wd     (classb_phase1_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_phase1_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classb_phase1_cyc_qs)
+  );
+
+
+  // R[classb_phase2_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classb_phase2_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_phase2_cyc_we & regen_qs),
+    .wd     (classb_phase2_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_phase2_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classb_phase2_cyc_qs)
+  );
+
+
+  // R[classb_phase3_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classb_phase3_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classb_phase3_cyc_we & regen_qs),
+    .wd     (classb_phase3_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classb_phase3_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classb_phase3_cyc_qs)
+  );
+
+
+  // R[classb_esc_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (32)
+  ) u_classb_esc_cnt (
+    .re     (classb_esc_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classb_esc_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classb_esc_cnt_qs)
+  );
+
+
+  // R[classb_state]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (3)
+  ) u_classb_state (
+    .re     (classb_state_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classb_state.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classb_state_qs)
+  );
+
+
+  // R[classc_ctrl]: V(False)
+
+  //   F[en]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classc_ctrl_en (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_en_we & regen_qs),
+    .wd     (classc_ctrl_en_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.en.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_en_qs)
+  );
+
+
+  //   F[lock]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classc_ctrl_lock (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_lock_we & regen_qs),
+    .wd     (classc_ctrl_lock_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.lock.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_lock_qs)
+  );
+
+
+  //   F[en_e0]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classc_ctrl_en_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_en_e0_we & regen_qs),
+    .wd     (classc_ctrl_en_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.en_e0.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_en_e0_qs)
+  );
+
+
+  //   F[en_e1]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classc_ctrl_en_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_en_e1_we & regen_qs),
+    .wd     (classc_ctrl_en_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.en_e1.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_en_e1_qs)
+  );
+
+
+  //   F[en_e2]: 4:4
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classc_ctrl_en_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_en_e2_we & regen_qs),
+    .wd     (classc_ctrl_en_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.en_e2.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_en_e2_qs)
+  );
+
+
+  //   F[en_e3]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classc_ctrl_en_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_en_e3_we & regen_qs),
+    .wd     (classc_ctrl_en_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.en_e3.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_en_e3_qs)
+  );
+
+
+  //   F[map_e0]: 7:6
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_classc_ctrl_map_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_map_e0_we & regen_qs),
+    .wd     (classc_ctrl_map_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.map_e0.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_map_e0_qs)
+  );
+
+
+  //   F[map_e1]: 9:8
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h1)
+  ) u_classc_ctrl_map_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_map_e1_we & regen_qs),
+    .wd     (classc_ctrl_map_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.map_e1.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_map_e1_qs)
+  );
+
+
+  //   F[map_e2]: 11:10
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_classc_ctrl_map_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_map_e2_we & regen_qs),
+    .wd     (classc_ctrl_map_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.map_e2.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_map_e2_qs)
+  );
+
+
+  //   F[map_e3]: 13:12
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h3)
+  ) u_classc_ctrl_map_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_ctrl_map_e3_we & regen_qs),
+    .wd     (classc_ctrl_map_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_ctrl.map_e3.q ),
+
+    // to register interface (read)
+    .qs     (classc_ctrl_map_e3_qs)
+  );
+
+
+  // R[classc_clren]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h1)
+  ) u_classc_clren (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (classc_clren_we),
+    .wd     (classc_clren_wd),
+
+    // from internal hardware
+    .de     (hw2reg.classc_clren.de),
+    .d      (hw2reg.classc_clren.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (classc_clren_qs)
+  );
+
+
+  // R[classc_clr]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("WO"),
+    .RESVAL  (1'h0)
+  ) u_classc_clr (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_clr_we & classc_clren_qs),
+    .wd     (classc_clr_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (reg2hw.classc_clr.qe),
+    .q      (reg2hw.classc_clr.q ),
+
+    .qs     ()
+  );
+
+
+  // R[classc_accum_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (16)
+  ) u_classc_accum_cnt (
+    .re     (classc_accum_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classc_accum_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classc_accum_cnt_qs)
+  );
+
+
+  // R[classc_accum_thresh]: V(False)
+
+  prim_subreg #(
+    .DW      (16),
+    .SWACCESS("RW"),
+    .RESVAL  (16'h0)
+  ) u_classc_accum_thresh (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_accum_thresh_we & regen_qs),
+    .wd     (classc_accum_thresh_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_accum_thresh.q ),
+
+    // to register interface (read)
+    .qs     (classc_accum_thresh_qs)
+  );
+
+
+  // R[classc_timeout_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classc_timeout_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_timeout_cyc_we & regen_qs),
+    .wd     (classc_timeout_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_timeout_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classc_timeout_cyc_qs)
+  );
+
+
+  // R[classc_phase0_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classc_phase0_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_phase0_cyc_we & regen_qs),
+    .wd     (classc_phase0_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_phase0_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classc_phase0_cyc_qs)
+  );
+
+
+  // R[classc_phase1_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classc_phase1_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_phase1_cyc_we & regen_qs),
+    .wd     (classc_phase1_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_phase1_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classc_phase1_cyc_qs)
+  );
+
+
+  // R[classc_phase2_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classc_phase2_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_phase2_cyc_we & regen_qs),
+    .wd     (classc_phase2_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_phase2_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classc_phase2_cyc_qs)
+  );
+
+
+  // R[classc_phase3_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classc_phase3_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classc_phase3_cyc_we & regen_qs),
+    .wd     (classc_phase3_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classc_phase3_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classc_phase3_cyc_qs)
+  );
+
+
+  // R[classc_esc_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (32)
+  ) u_classc_esc_cnt (
+    .re     (classc_esc_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classc_esc_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classc_esc_cnt_qs)
+  );
+
+
+  // R[classc_state]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (3)
+  ) u_classc_state (
+    .re     (classc_state_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classc_state.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classc_state_qs)
+  );
+
+
+  // R[classd_ctrl]: V(False)
+
+  //   F[en]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classd_ctrl_en (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_en_we & regen_qs),
+    .wd     (classd_ctrl_en_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.en.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_en_qs)
+  );
+
+
+  //   F[lock]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_classd_ctrl_lock (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_lock_we & regen_qs),
+    .wd     (classd_ctrl_lock_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.lock.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_lock_qs)
+  );
+
+
+  //   F[en_e0]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classd_ctrl_en_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_en_e0_we & regen_qs),
+    .wd     (classd_ctrl_en_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.en_e0.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_en_e0_qs)
+  );
+
+
+  //   F[en_e1]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classd_ctrl_en_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_en_e1_we & regen_qs),
+    .wd     (classd_ctrl_en_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.en_e1.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_en_e1_qs)
+  );
+
+
+  //   F[en_e2]: 4:4
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classd_ctrl_en_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_en_e2_we & regen_qs),
+    .wd     (classd_ctrl_en_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.en_e2.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_en_e2_qs)
+  );
+
+
+  //   F[en_e3]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h1)
+  ) u_classd_ctrl_en_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_en_e3_we & regen_qs),
+    .wd     (classd_ctrl_en_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.en_e3.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_en_e3_qs)
+  );
+
+
+  //   F[map_e0]: 7:6
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_classd_ctrl_map_e0 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_map_e0_we & regen_qs),
+    .wd     (classd_ctrl_map_e0_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.map_e0.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_map_e0_qs)
+  );
+
+
+  //   F[map_e1]: 9:8
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h1)
+  ) u_classd_ctrl_map_e1 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_map_e1_we & regen_qs),
+    .wd     (classd_ctrl_map_e1_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.map_e1.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_map_e1_qs)
+  );
+
+
+  //   F[map_e2]: 11:10
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_classd_ctrl_map_e2 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_map_e2_we & regen_qs),
+    .wd     (classd_ctrl_map_e2_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.map_e2.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_map_e2_qs)
+  );
+
+
+  //   F[map_e3]: 13:12
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h3)
+  ) u_classd_ctrl_map_e3 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_ctrl_map_e3_we & regen_qs),
+    .wd     (classd_ctrl_map_e3_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_ctrl.map_e3.q ),
+
+    // to register interface (read)
+    .qs     (classd_ctrl_map_e3_qs)
+  );
+
+
+  // R[classd_clren]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h1)
+  ) u_classd_clren (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (classd_clren_we),
+    .wd     (classd_clren_wd),
+
+    // from internal hardware
+    .de     (hw2reg.classd_clren.de),
+    .d      (hw2reg.classd_clren.d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (classd_clren_qs)
+  );
+
+
+  // R[classd_clr]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("WO"),
+    .RESVAL  (1'h0)
+  ) u_classd_clr (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_clr_we & classd_clren_qs),
+    .wd     (classd_clr_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (reg2hw.classd_clr.qe),
+    .q      (reg2hw.classd_clr.q ),
+
+    .qs     ()
+  );
+
+
+  // R[classd_accum_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (16)
+  ) u_classd_accum_cnt (
+    .re     (classd_accum_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classd_accum_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classd_accum_cnt_qs)
+  );
+
+
+  // R[classd_accum_thresh]: V(False)
+
+  prim_subreg #(
+    .DW      (16),
+    .SWACCESS("RW"),
+    .RESVAL  (16'h0)
+  ) u_classd_accum_thresh (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_accum_thresh_we & regen_qs),
+    .wd     (classd_accum_thresh_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_accum_thresh.q ),
+
+    // to register interface (read)
+    .qs     (classd_accum_thresh_qs)
+  );
+
+
+  // R[classd_timeout_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classd_timeout_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_timeout_cyc_we & regen_qs),
+    .wd     (classd_timeout_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_timeout_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classd_timeout_cyc_qs)
+  );
+
+
+  // R[classd_phase0_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classd_phase0_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_phase0_cyc_we & regen_qs),
+    .wd     (classd_phase0_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_phase0_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classd_phase0_cyc_qs)
+  );
+
+
+  // R[classd_phase1_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classd_phase1_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_phase1_cyc_we & regen_qs),
+    .wd     (classd_phase1_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_phase1_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classd_phase1_cyc_qs)
+  );
+
+
+  // R[classd_phase2_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classd_phase2_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_phase2_cyc_we & regen_qs),
+    .wd     (classd_phase2_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_phase2_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classd_phase2_cyc_qs)
+  );
+
+
+  // R[classd_phase3_cyc]: V(False)
+
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_classd_phase3_cyc (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (classd_phase3_cyc_we & regen_qs),
+    .wd     (classd_phase3_cyc_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.classd_phase3_cyc.q ),
+
+    // to register interface (read)
+    .qs     (classd_phase3_cyc_qs)
+  );
+
+
+  // R[classd_esc_cnt]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (32)
+  ) u_classd_esc_cnt (
+    .re     (classd_esc_cnt_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classd_esc_cnt.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classd_esc_cnt_qs)
+  );
+
+
+  // R[classd_state]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (3)
+  ) u_classd_state (
+    .re     (classd_state_re),
+    .we     (1'b0),
+    .wd     ('0),
+    .d      (hw2reg.classd_state.d),
+    .qre    (),
+    .qe     (),
+    .q      (),
+    .qs     (classd_state_qs)
+  );
+
+
+
+
+  logic [58:0] addr_hit;
+  always_comb begin
+    addr_hit = '0;
+    addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
+    addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET);
+    addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET);
+    addr_hit[ 3] = (reg_addr == ALERT_HANDLER_REGEN_OFFSET);
+    addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET);
+    addr_hit[ 5] = (reg_addr == ALERT_HANDLER_ALERT_EN_OFFSET);
+    addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_OFFSET);
+    addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_OFFSET);
+    addr_hit[ 8] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_OFFSET);
+    addr_hit[ 9] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET);
+    addr_hit[10] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET);
+    addr_hit[11] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+    addr_hit[12] = (reg_addr == ALERT_HANDLER_CLASSA_CLREN_OFFSET);
+    addr_hit[13] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+    addr_hit[14] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+    addr_hit[15] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+    addr_hit[16] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+    addr_hit[17] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+    addr_hit[18] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+    addr_hit[19] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+    addr_hit[20] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+    addr_hit[21] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+    addr_hit[22] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+    addr_hit[23] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+    addr_hit[24] = (reg_addr == ALERT_HANDLER_CLASSB_CLREN_OFFSET);
+    addr_hit[25] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+    addr_hit[26] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+    addr_hit[27] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+    addr_hit[28] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+    addr_hit[29] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+    addr_hit[30] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+    addr_hit[31] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+    addr_hit[32] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+    addr_hit[33] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+    addr_hit[34] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+    addr_hit[35] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+    addr_hit[36] = (reg_addr == ALERT_HANDLER_CLASSC_CLREN_OFFSET);
+    addr_hit[37] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+    addr_hit[38] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+    addr_hit[39] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+    addr_hit[40] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+    addr_hit[41] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+    addr_hit[42] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+    addr_hit[43] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+    addr_hit[44] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+    addr_hit[45] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+    addr_hit[46] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+    addr_hit[47] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+    addr_hit[48] = (reg_addr == ALERT_HANDLER_CLASSD_CLREN_OFFSET);
+    addr_hit[49] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+    addr_hit[50] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+    addr_hit[51] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+    addr_hit[52] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+    addr_hit[53] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+    addr_hit[54] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+    addr_hit[55] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+    addr_hit[56] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+    addr_hit[57] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+    addr_hit[58] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+  end
+
+  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+  // Check sub-word write is permitted
+  always_comb begin
+    wr_err = 1'b0;
+    if (addr_hit[ 0] && reg_we && (ALERT_HANDLER_PERMIT[ 0] != (ALERT_HANDLER_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 1] && reg_we && (ALERT_HANDLER_PERMIT[ 1] != (ALERT_HANDLER_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 2] && reg_we && (ALERT_HANDLER_PERMIT[ 2] != (ALERT_HANDLER_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 3] && reg_we && (ALERT_HANDLER_PERMIT[ 3] != (ALERT_HANDLER_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 4] && reg_we && (ALERT_HANDLER_PERMIT[ 4] != (ALERT_HANDLER_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 5] && reg_we && (ALERT_HANDLER_PERMIT[ 5] != (ALERT_HANDLER_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 6] && reg_we && (ALERT_HANDLER_PERMIT[ 6] != (ALERT_HANDLER_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 7] && reg_we && (ALERT_HANDLER_PERMIT[ 7] != (ALERT_HANDLER_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 8] && reg_we && (ALERT_HANDLER_PERMIT[ 8] != (ALERT_HANDLER_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[ 9] && reg_we && (ALERT_HANDLER_PERMIT[ 9] != (ALERT_HANDLER_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[10] && reg_we && (ALERT_HANDLER_PERMIT[10] != (ALERT_HANDLER_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[11] && reg_we && (ALERT_HANDLER_PERMIT[11] != (ALERT_HANDLER_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[12] && reg_we && (ALERT_HANDLER_PERMIT[12] != (ALERT_HANDLER_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[13] && reg_we && (ALERT_HANDLER_PERMIT[13] != (ALERT_HANDLER_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[14] && reg_we && (ALERT_HANDLER_PERMIT[14] != (ALERT_HANDLER_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[15] && reg_we && (ALERT_HANDLER_PERMIT[15] != (ALERT_HANDLER_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[16] && reg_we && (ALERT_HANDLER_PERMIT[16] != (ALERT_HANDLER_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[17] && reg_we && (ALERT_HANDLER_PERMIT[17] != (ALERT_HANDLER_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[18] && reg_we && (ALERT_HANDLER_PERMIT[18] != (ALERT_HANDLER_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[19] && reg_we && (ALERT_HANDLER_PERMIT[19] != (ALERT_HANDLER_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[20] && reg_we && (ALERT_HANDLER_PERMIT[20] != (ALERT_HANDLER_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[21] && reg_we && (ALERT_HANDLER_PERMIT[21] != (ALERT_HANDLER_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[22] && reg_we && (ALERT_HANDLER_PERMIT[22] != (ALERT_HANDLER_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[23] && reg_we && (ALERT_HANDLER_PERMIT[23] != (ALERT_HANDLER_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[24] && reg_we && (ALERT_HANDLER_PERMIT[24] != (ALERT_HANDLER_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[25] && reg_we && (ALERT_HANDLER_PERMIT[25] != (ALERT_HANDLER_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[26] && reg_we && (ALERT_HANDLER_PERMIT[26] != (ALERT_HANDLER_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[27] && reg_we && (ALERT_HANDLER_PERMIT[27] != (ALERT_HANDLER_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[28] && reg_we && (ALERT_HANDLER_PERMIT[28] != (ALERT_HANDLER_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[29] && reg_we && (ALERT_HANDLER_PERMIT[29] != (ALERT_HANDLER_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[30] && reg_we && (ALERT_HANDLER_PERMIT[30] != (ALERT_HANDLER_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[31] && reg_we && (ALERT_HANDLER_PERMIT[31] != (ALERT_HANDLER_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[32] && reg_we && (ALERT_HANDLER_PERMIT[32] != (ALERT_HANDLER_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[33] && reg_we && (ALERT_HANDLER_PERMIT[33] != (ALERT_HANDLER_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[34] && reg_we && (ALERT_HANDLER_PERMIT[34] != (ALERT_HANDLER_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[35] && reg_we && (ALERT_HANDLER_PERMIT[35] != (ALERT_HANDLER_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[36] && reg_we && (ALERT_HANDLER_PERMIT[36] != (ALERT_HANDLER_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[37] && reg_we && (ALERT_HANDLER_PERMIT[37] != (ALERT_HANDLER_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[38] && reg_we && (ALERT_HANDLER_PERMIT[38] != (ALERT_HANDLER_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[39] && reg_we && (ALERT_HANDLER_PERMIT[39] != (ALERT_HANDLER_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[40] && reg_we && (ALERT_HANDLER_PERMIT[40] != (ALERT_HANDLER_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[41] && reg_we && (ALERT_HANDLER_PERMIT[41] != (ALERT_HANDLER_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[42] && reg_we && (ALERT_HANDLER_PERMIT[42] != (ALERT_HANDLER_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[43] && reg_we && (ALERT_HANDLER_PERMIT[43] != (ALERT_HANDLER_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[44] && reg_we && (ALERT_HANDLER_PERMIT[44] != (ALERT_HANDLER_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[45] && reg_we && (ALERT_HANDLER_PERMIT[45] != (ALERT_HANDLER_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[46] && reg_we && (ALERT_HANDLER_PERMIT[46] != (ALERT_HANDLER_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[47] && reg_we && (ALERT_HANDLER_PERMIT[47] != (ALERT_HANDLER_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[48] && reg_we && (ALERT_HANDLER_PERMIT[48] != (ALERT_HANDLER_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[49] && reg_we && (ALERT_HANDLER_PERMIT[49] != (ALERT_HANDLER_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[50] && reg_we && (ALERT_HANDLER_PERMIT[50] != (ALERT_HANDLER_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[51] && reg_we && (ALERT_HANDLER_PERMIT[51] != (ALERT_HANDLER_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[52] && reg_we && (ALERT_HANDLER_PERMIT[52] != (ALERT_HANDLER_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[53] && reg_we && (ALERT_HANDLER_PERMIT[53] != (ALERT_HANDLER_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[54] && reg_we && (ALERT_HANDLER_PERMIT[54] != (ALERT_HANDLER_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[55] && reg_we && (ALERT_HANDLER_PERMIT[55] != (ALERT_HANDLER_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[56] && reg_we && (ALERT_HANDLER_PERMIT[56] != (ALERT_HANDLER_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[57] && reg_we && (ALERT_HANDLER_PERMIT[57] != (ALERT_HANDLER_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[58] && reg_we && (ALERT_HANDLER_PERMIT[58] != (ALERT_HANDLER_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
+  end
+
+  assign intr_state_classa_we = addr_hit[0] & reg_we & ~wr_err;
+  assign intr_state_classa_wd = reg_wdata[0];
+
+  assign intr_state_classb_we = addr_hit[0] & reg_we & ~wr_err;
+  assign intr_state_classb_wd = reg_wdata[1];
+
+  assign intr_state_classc_we = addr_hit[0] & reg_we & ~wr_err;
+  assign intr_state_classc_wd = reg_wdata[2];
+
+  assign intr_state_classd_we = addr_hit[0] & reg_we & ~wr_err;
+  assign intr_state_classd_wd = reg_wdata[3];
+
+  assign intr_enable_classa_we = addr_hit[1] & reg_we & ~wr_err;
+  assign intr_enable_classa_wd = reg_wdata[0];
+
+  assign intr_enable_classb_we = addr_hit[1] & reg_we & ~wr_err;
+  assign intr_enable_classb_wd = reg_wdata[1];
+
+  assign intr_enable_classc_we = addr_hit[1] & reg_we & ~wr_err;
+  assign intr_enable_classc_wd = reg_wdata[2];
+
+  assign intr_enable_classd_we = addr_hit[1] & reg_we & ~wr_err;
+  assign intr_enable_classd_wd = reg_wdata[3];
+
+  assign intr_test_classa_we = addr_hit[2] & reg_we & ~wr_err;
+  assign intr_test_classa_wd = reg_wdata[0];
+
+  assign intr_test_classb_we = addr_hit[2] & reg_we & ~wr_err;
+  assign intr_test_classb_wd = reg_wdata[1];
+
+  assign intr_test_classc_we = addr_hit[2] & reg_we & ~wr_err;
+  assign intr_test_classc_wd = reg_wdata[2];
+
+  assign intr_test_classd_we = addr_hit[2] & reg_we & ~wr_err;
+  assign intr_test_classd_wd = reg_wdata[3];
+
+  assign regen_we = addr_hit[3] & reg_we & ~wr_err;
+  assign regen_wd = reg_wdata[0];
+
+  assign ping_timeout_cyc_we = addr_hit[4] & reg_we & ~wr_err;
+  assign ping_timeout_cyc_wd = reg_wdata[23:0];
+
+  assign alert_en_we = addr_hit[5] & reg_we & ~wr_err;
+  assign alert_en_wd = reg_wdata[0];
+
+  assign alert_class_we = addr_hit[6] & reg_we & ~wr_err;
+  assign alert_class_wd = reg_wdata[1:0];
+
+  assign alert_cause_we = addr_hit[7] & reg_we & ~wr_err;
+  assign alert_cause_wd = reg_wdata[0];
+
+  assign loc_alert_en_en_la0_we = addr_hit[8] & reg_we & ~wr_err;
+  assign loc_alert_en_en_la0_wd = reg_wdata[0];
+
+  assign loc_alert_en_en_la1_we = addr_hit[8] & reg_we & ~wr_err;
+  assign loc_alert_en_en_la1_wd = reg_wdata[1];
+
+  assign loc_alert_en_en_la2_we = addr_hit[8] & reg_we & ~wr_err;
+  assign loc_alert_en_en_la2_wd = reg_wdata[2];
+
+  assign loc_alert_en_en_la3_we = addr_hit[8] & reg_we & ~wr_err;
+  assign loc_alert_en_en_la3_wd = reg_wdata[3];
+
+  assign loc_alert_class_class_la0_we = addr_hit[9] & reg_we & ~wr_err;
+  assign loc_alert_class_class_la0_wd = reg_wdata[1:0];
+
+  assign loc_alert_class_class_la1_we = addr_hit[9] & reg_we & ~wr_err;
+  assign loc_alert_class_class_la1_wd = reg_wdata[3:2];
+
+  assign loc_alert_class_class_la2_we = addr_hit[9] & reg_we & ~wr_err;
+  assign loc_alert_class_class_la2_wd = reg_wdata[5:4];
+
+  assign loc_alert_class_class_la3_we = addr_hit[9] & reg_we & ~wr_err;
+  assign loc_alert_class_class_la3_wd = reg_wdata[7:6];
+
+  assign loc_alert_cause_la0_we = addr_hit[10] & reg_we & ~wr_err;
+  assign loc_alert_cause_la0_wd = reg_wdata[0];
+
+  assign loc_alert_cause_la1_we = addr_hit[10] & reg_we & ~wr_err;
+  assign loc_alert_cause_la1_wd = reg_wdata[1];
+
+  assign loc_alert_cause_la2_we = addr_hit[10] & reg_we & ~wr_err;
+  assign loc_alert_cause_la2_wd = reg_wdata[2];
+
+  assign loc_alert_cause_la3_we = addr_hit[10] & reg_we & ~wr_err;
+  assign loc_alert_cause_la3_wd = reg_wdata[3];
+
+  assign classa_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_en_wd = reg_wdata[0];
+
+  assign classa_ctrl_lock_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_lock_wd = reg_wdata[1];
+
+  assign classa_ctrl_en_e0_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_en_e0_wd = reg_wdata[2];
+
+  assign classa_ctrl_en_e1_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_en_e1_wd = reg_wdata[3];
+
+  assign classa_ctrl_en_e2_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_en_e2_wd = reg_wdata[4];
+
+  assign classa_ctrl_en_e3_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_en_e3_wd = reg_wdata[5];
+
+  assign classa_ctrl_map_e0_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
+
+  assign classa_ctrl_map_e1_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
+
+  assign classa_ctrl_map_e2_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
+
+  assign classa_ctrl_map_e3_we = addr_hit[11] & reg_we & ~wr_err;
+  assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
+
+  assign classa_clren_we = addr_hit[12] & reg_we & ~wr_err;
+  assign classa_clren_wd = reg_wdata[0];
+
+  assign classa_clr_we = addr_hit[13] & reg_we & ~wr_err;
+  assign classa_clr_wd = reg_wdata[0];
+
+  assign classa_accum_cnt_re = addr_hit[14] && reg_re;
+
+  assign classa_accum_thresh_we = addr_hit[15] & reg_we & ~wr_err;
+  assign classa_accum_thresh_wd = reg_wdata[15:0];
+
+  assign classa_timeout_cyc_we = addr_hit[16] & reg_we & ~wr_err;
+  assign classa_timeout_cyc_wd = reg_wdata[31:0];
+
+  assign classa_phase0_cyc_we = addr_hit[17] & reg_we & ~wr_err;
+  assign classa_phase0_cyc_wd = reg_wdata[31:0];
+
+  assign classa_phase1_cyc_we = addr_hit[18] & reg_we & ~wr_err;
+  assign classa_phase1_cyc_wd = reg_wdata[31:0];
+
+  assign classa_phase2_cyc_we = addr_hit[19] & reg_we & ~wr_err;
+  assign classa_phase2_cyc_wd = reg_wdata[31:0];
+
+  assign classa_phase3_cyc_we = addr_hit[20] & reg_we & ~wr_err;
+  assign classa_phase3_cyc_wd = reg_wdata[31:0];
+
+  assign classa_esc_cnt_re = addr_hit[21] && reg_re;
+
+  assign classa_state_re = addr_hit[22] && reg_re;
+
+  assign classb_ctrl_en_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_en_wd = reg_wdata[0];
+
+  assign classb_ctrl_lock_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_lock_wd = reg_wdata[1];
+
+  assign classb_ctrl_en_e0_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_en_e0_wd = reg_wdata[2];
+
+  assign classb_ctrl_en_e1_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_en_e1_wd = reg_wdata[3];
+
+  assign classb_ctrl_en_e2_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_en_e2_wd = reg_wdata[4];
+
+  assign classb_ctrl_en_e3_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_en_e3_wd = reg_wdata[5];
+
+  assign classb_ctrl_map_e0_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
+
+  assign classb_ctrl_map_e1_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
+
+  assign classb_ctrl_map_e2_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
+
+  assign classb_ctrl_map_e3_we = addr_hit[23] & reg_we & ~wr_err;
+  assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
+
+  assign classb_clren_we = addr_hit[24] & reg_we & ~wr_err;
+  assign classb_clren_wd = reg_wdata[0];
+
+  assign classb_clr_we = addr_hit[25] & reg_we & ~wr_err;
+  assign classb_clr_wd = reg_wdata[0];
+
+  assign classb_accum_cnt_re = addr_hit[26] && reg_re;
+
+  assign classb_accum_thresh_we = addr_hit[27] & reg_we & ~wr_err;
+  assign classb_accum_thresh_wd = reg_wdata[15:0];
+
+  assign classb_timeout_cyc_we = addr_hit[28] & reg_we & ~wr_err;
+  assign classb_timeout_cyc_wd = reg_wdata[31:0];
+
+  assign classb_phase0_cyc_we = addr_hit[29] & reg_we & ~wr_err;
+  assign classb_phase0_cyc_wd = reg_wdata[31:0];
+
+  assign classb_phase1_cyc_we = addr_hit[30] & reg_we & ~wr_err;
+  assign classb_phase1_cyc_wd = reg_wdata[31:0];
+
+  assign classb_phase2_cyc_we = addr_hit[31] & reg_we & ~wr_err;
+  assign classb_phase2_cyc_wd = reg_wdata[31:0];
+
+  assign classb_phase3_cyc_we = addr_hit[32] & reg_we & ~wr_err;
+  assign classb_phase3_cyc_wd = reg_wdata[31:0];
+
+  assign classb_esc_cnt_re = addr_hit[33] && reg_re;
+
+  assign classb_state_re = addr_hit[34] && reg_re;
+
+  assign classc_ctrl_en_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_en_wd = reg_wdata[0];
+
+  assign classc_ctrl_lock_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_lock_wd = reg_wdata[1];
+
+  assign classc_ctrl_en_e0_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_en_e0_wd = reg_wdata[2];
+
+  assign classc_ctrl_en_e1_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_en_e1_wd = reg_wdata[3];
+
+  assign classc_ctrl_en_e2_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_en_e2_wd = reg_wdata[4];
+
+  assign classc_ctrl_en_e3_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_en_e3_wd = reg_wdata[5];
+
+  assign classc_ctrl_map_e0_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
+
+  assign classc_ctrl_map_e1_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
+
+  assign classc_ctrl_map_e2_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
+
+  assign classc_ctrl_map_e3_we = addr_hit[35] & reg_we & ~wr_err;
+  assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
+
+  assign classc_clren_we = addr_hit[36] & reg_we & ~wr_err;
+  assign classc_clren_wd = reg_wdata[0];
+
+  assign classc_clr_we = addr_hit[37] & reg_we & ~wr_err;
+  assign classc_clr_wd = reg_wdata[0];
+
+  assign classc_accum_cnt_re = addr_hit[38] && reg_re;
+
+  assign classc_accum_thresh_we = addr_hit[39] & reg_we & ~wr_err;
+  assign classc_accum_thresh_wd = reg_wdata[15:0];
+
+  assign classc_timeout_cyc_we = addr_hit[40] & reg_we & ~wr_err;
+  assign classc_timeout_cyc_wd = reg_wdata[31:0];
+
+  assign classc_phase0_cyc_we = addr_hit[41] & reg_we & ~wr_err;
+  assign classc_phase0_cyc_wd = reg_wdata[31:0];
+
+  assign classc_phase1_cyc_we = addr_hit[42] & reg_we & ~wr_err;
+  assign classc_phase1_cyc_wd = reg_wdata[31:0];
+
+  assign classc_phase2_cyc_we = addr_hit[43] & reg_we & ~wr_err;
+  assign classc_phase2_cyc_wd = reg_wdata[31:0];
+
+  assign classc_phase3_cyc_we = addr_hit[44] & reg_we & ~wr_err;
+  assign classc_phase3_cyc_wd = reg_wdata[31:0];
+
+  assign classc_esc_cnt_re = addr_hit[45] && reg_re;
+
+  assign classc_state_re = addr_hit[46] && reg_re;
+
+  assign classd_ctrl_en_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_en_wd = reg_wdata[0];
+
+  assign classd_ctrl_lock_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_lock_wd = reg_wdata[1];
+
+  assign classd_ctrl_en_e0_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_en_e0_wd = reg_wdata[2];
+
+  assign classd_ctrl_en_e1_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_en_e1_wd = reg_wdata[3];
+
+  assign classd_ctrl_en_e2_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_en_e2_wd = reg_wdata[4];
+
+  assign classd_ctrl_en_e3_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_en_e3_wd = reg_wdata[5];
+
+  assign classd_ctrl_map_e0_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
+
+  assign classd_ctrl_map_e1_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
+
+  assign classd_ctrl_map_e2_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
+
+  assign classd_ctrl_map_e3_we = addr_hit[47] & reg_we & ~wr_err;
+  assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
+
+  assign classd_clren_we = addr_hit[48] & reg_we & ~wr_err;
+  assign classd_clren_wd = reg_wdata[0];
+
+  assign classd_clr_we = addr_hit[49] & reg_we & ~wr_err;
+  assign classd_clr_wd = reg_wdata[0];
+
+  assign classd_accum_cnt_re = addr_hit[50] && reg_re;
+
+  assign classd_accum_thresh_we = addr_hit[51] & reg_we & ~wr_err;
+  assign classd_accum_thresh_wd = reg_wdata[15:0];
+
+  assign classd_timeout_cyc_we = addr_hit[52] & reg_we & ~wr_err;
+  assign classd_timeout_cyc_wd = reg_wdata[31:0];
+
+  assign classd_phase0_cyc_we = addr_hit[53] & reg_we & ~wr_err;
+  assign classd_phase0_cyc_wd = reg_wdata[31:0];
+
+  assign classd_phase1_cyc_we = addr_hit[54] & reg_we & ~wr_err;
+  assign classd_phase1_cyc_wd = reg_wdata[31:0];
+
+  assign classd_phase2_cyc_we = addr_hit[55] & reg_we & ~wr_err;
+  assign classd_phase2_cyc_wd = reg_wdata[31:0];
+
+  assign classd_phase3_cyc_we = addr_hit[56] & reg_we & ~wr_err;
+  assign classd_phase3_cyc_wd = reg_wdata[31:0];
+
+  assign classd_esc_cnt_re = addr_hit[57] && reg_re;
+
+  assign classd_state_re = addr_hit[58] && reg_re;
+
+  // Read data return
+  always_comb begin
+    reg_rdata_next = '0;
+    unique case (1'b1)
+      addr_hit[0]: begin
+        reg_rdata_next[0] = intr_state_classa_qs;
+        reg_rdata_next[1] = intr_state_classb_qs;
+        reg_rdata_next[2] = intr_state_classc_qs;
+        reg_rdata_next[3] = intr_state_classd_qs;
+      end
+
+      addr_hit[1]: begin
+        reg_rdata_next[0] = intr_enable_classa_qs;
+        reg_rdata_next[1] = intr_enable_classb_qs;
+        reg_rdata_next[2] = intr_enable_classc_qs;
+        reg_rdata_next[3] = intr_enable_classd_qs;
+      end
+
+      addr_hit[2]: begin
+        reg_rdata_next[0] = '0;
+        reg_rdata_next[1] = '0;
+        reg_rdata_next[2] = '0;
+        reg_rdata_next[3] = '0;
+      end
+
+      addr_hit[3]: begin
+        reg_rdata_next[0] = regen_qs;
+      end
+
+      addr_hit[4]: begin
+        reg_rdata_next[23:0] = ping_timeout_cyc_qs;
+      end
+
+      addr_hit[5]: begin
+        reg_rdata_next[0] = alert_en_qs;
+      end
+
+      addr_hit[6]: begin
+        reg_rdata_next[1:0] = alert_class_qs;
+      end
+
+      addr_hit[7]: begin
+        reg_rdata_next[0] = alert_cause_qs;
+      end
+
+      addr_hit[8]: begin
+        reg_rdata_next[0] = loc_alert_en_en_la0_qs;
+        reg_rdata_next[1] = loc_alert_en_en_la1_qs;
+        reg_rdata_next[2] = loc_alert_en_en_la2_qs;
+        reg_rdata_next[3] = loc_alert_en_en_la3_qs;
+      end
+
+      addr_hit[9]: begin
+        reg_rdata_next[1:0] = loc_alert_class_class_la0_qs;
+        reg_rdata_next[3:2] = loc_alert_class_class_la1_qs;
+        reg_rdata_next[5:4] = loc_alert_class_class_la2_qs;
+        reg_rdata_next[7:6] = loc_alert_class_class_la3_qs;
+      end
+
+      addr_hit[10]: begin
+        reg_rdata_next[0] = loc_alert_cause_la0_qs;
+        reg_rdata_next[1] = loc_alert_cause_la1_qs;
+        reg_rdata_next[2] = loc_alert_cause_la2_qs;
+        reg_rdata_next[3] = loc_alert_cause_la3_qs;
+      end
+
+      addr_hit[11]: begin
+        reg_rdata_next[0] = classa_ctrl_en_qs;
+        reg_rdata_next[1] = classa_ctrl_lock_qs;
+        reg_rdata_next[2] = classa_ctrl_en_e0_qs;
+        reg_rdata_next[3] = classa_ctrl_en_e1_qs;
+        reg_rdata_next[4] = classa_ctrl_en_e2_qs;
+        reg_rdata_next[5] = classa_ctrl_en_e3_qs;
+        reg_rdata_next[7:6] = classa_ctrl_map_e0_qs;
+        reg_rdata_next[9:8] = classa_ctrl_map_e1_qs;
+        reg_rdata_next[11:10] = classa_ctrl_map_e2_qs;
+        reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
+      end
+
+      addr_hit[12]: begin
+        reg_rdata_next[0] = classa_clren_qs;
+      end
+
+      addr_hit[13]: begin
+        reg_rdata_next[0] = '0;
+      end
+
+      addr_hit[14]: begin
+        reg_rdata_next[15:0] = classa_accum_cnt_qs;
+      end
+
+      addr_hit[15]: begin
+        reg_rdata_next[15:0] = classa_accum_thresh_qs;
+      end
+
+      addr_hit[16]: begin
+        reg_rdata_next[31:0] = classa_timeout_cyc_qs;
+      end
+
+      addr_hit[17]: begin
+        reg_rdata_next[31:0] = classa_phase0_cyc_qs;
+      end
+
+      addr_hit[18]: begin
+        reg_rdata_next[31:0] = classa_phase1_cyc_qs;
+      end
+
+      addr_hit[19]: begin
+        reg_rdata_next[31:0] = classa_phase2_cyc_qs;
+      end
+
+      addr_hit[20]: begin
+        reg_rdata_next[31:0] = classa_phase3_cyc_qs;
+      end
+
+      addr_hit[21]: begin
+        reg_rdata_next[31:0] = classa_esc_cnt_qs;
+      end
+
+      addr_hit[22]: begin
+        reg_rdata_next[2:0] = classa_state_qs;
+      end
+
+      addr_hit[23]: begin
+        reg_rdata_next[0] = classb_ctrl_en_qs;
+        reg_rdata_next[1] = classb_ctrl_lock_qs;
+        reg_rdata_next[2] = classb_ctrl_en_e0_qs;
+        reg_rdata_next[3] = classb_ctrl_en_e1_qs;
+        reg_rdata_next[4] = classb_ctrl_en_e2_qs;
+        reg_rdata_next[5] = classb_ctrl_en_e3_qs;
+        reg_rdata_next[7:6] = classb_ctrl_map_e0_qs;
+        reg_rdata_next[9:8] = classb_ctrl_map_e1_qs;
+        reg_rdata_next[11:10] = classb_ctrl_map_e2_qs;
+        reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
+      end
+
+      addr_hit[24]: begin
+        reg_rdata_next[0] = classb_clren_qs;
+      end
+
+      addr_hit[25]: begin
+        reg_rdata_next[0] = '0;
+      end
+
+      addr_hit[26]: begin
+        reg_rdata_next[15:0] = classb_accum_cnt_qs;
+      end
+
+      addr_hit[27]: begin
+        reg_rdata_next[15:0] = classb_accum_thresh_qs;
+      end
+
+      addr_hit[28]: begin
+        reg_rdata_next[31:0] = classb_timeout_cyc_qs;
+      end
+
+      addr_hit[29]: begin
+        reg_rdata_next[31:0] = classb_phase0_cyc_qs;
+      end
+
+      addr_hit[30]: begin
+        reg_rdata_next[31:0] = classb_phase1_cyc_qs;
+      end
+
+      addr_hit[31]: begin
+        reg_rdata_next[31:0] = classb_phase2_cyc_qs;
+      end
+
+      addr_hit[32]: begin
+        reg_rdata_next[31:0] = classb_phase3_cyc_qs;
+      end
+
+      addr_hit[33]: begin
+        reg_rdata_next[31:0] = classb_esc_cnt_qs;
+      end
+
+      addr_hit[34]: begin
+        reg_rdata_next[2:0] = classb_state_qs;
+      end
+
+      addr_hit[35]: begin
+        reg_rdata_next[0] = classc_ctrl_en_qs;
+        reg_rdata_next[1] = classc_ctrl_lock_qs;
+        reg_rdata_next[2] = classc_ctrl_en_e0_qs;
+        reg_rdata_next[3] = classc_ctrl_en_e1_qs;
+        reg_rdata_next[4] = classc_ctrl_en_e2_qs;
+        reg_rdata_next[5] = classc_ctrl_en_e3_qs;
+        reg_rdata_next[7:6] = classc_ctrl_map_e0_qs;
+        reg_rdata_next[9:8] = classc_ctrl_map_e1_qs;
+        reg_rdata_next[11:10] = classc_ctrl_map_e2_qs;
+        reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
+      end
+
+      addr_hit[36]: begin
+        reg_rdata_next[0] = classc_clren_qs;
+      end
+
+      addr_hit[37]: begin
+        reg_rdata_next[0] = '0;
+      end
+
+      addr_hit[38]: begin
+        reg_rdata_next[15:0] = classc_accum_cnt_qs;
+      end
+
+      addr_hit[39]: begin
+        reg_rdata_next[15:0] = classc_accum_thresh_qs;
+      end
+
+      addr_hit[40]: begin
+        reg_rdata_next[31:0] = classc_timeout_cyc_qs;
+      end
+
+      addr_hit[41]: begin
+        reg_rdata_next[31:0] = classc_phase0_cyc_qs;
+      end
+
+      addr_hit[42]: begin
+        reg_rdata_next[31:0] = classc_phase1_cyc_qs;
+      end
+
+      addr_hit[43]: begin
+        reg_rdata_next[31:0] = classc_phase2_cyc_qs;
+      end
+
+      addr_hit[44]: begin
+        reg_rdata_next[31:0] = classc_phase3_cyc_qs;
+      end
+
+      addr_hit[45]: begin
+        reg_rdata_next[31:0] = classc_esc_cnt_qs;
+      end
+
+      addr_hit[46]: begin
+        reg_rdata_next[2:0] = classc_state_qs;
+      end
+
+      addr_hit[47]: begin
+        reg_rdata_next[0] = classd_ctrl_en_qs;
+        reg_rdata_next[1] = classd_ctrl_lock_qs;
+        reg_rdata_next[2] = classd_ctrl_en_e0_qs;
+        reg_rdata_next[3] = classd_ctrl_en_e1_qs;
+        reg_rdata_next[4] = classd_ctrl_en_e2_qs;
+        reg_rdata_next[5] = classd_ctrl_en_e3_qs;
+        reg_rdata_next[7:6] = classd_ctrl_map_e0_qs;
+        reg_rdata_next[9:8] = classd_ctrl_map_e1_qs;
+        reg_rdata_next[11:10] = classd_ctrl_map_e2_qs;
+        reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
+      end
+
+      addr_hit[48]: begin
+        reg_rdata_next[0] = classd_clren_qs;
+      end
+
+      addr_hit[49]: begin
+        reg_rdata_next[0] = '0;
+      end
+
+      addr_hit[50]: begin
+        reg_rdata_next[15:0] = classd_accum_cnt_qs;
+      end
+
+      addr_hit[51]: begin
+        reg_rdata_next[15:0] = classd_accum_thresh_qs;
+      end
+
+      addr_hit[52]: begin
+        reg_rdata_next[31:0] = classd_timeout_cyc_qs;
+      end
+
+      addr_hit[53]: begin
+        reg_rdata_next[31:0] = classd_phase0_cyc_qs;
+      end
+
+      addr_hit[54]: begin
+        reg_rdata_next[31:0] = classd_phase1_cyc_qs;
+      end
+
+      addr_hit[55]: begin
+        reg_rdata_next[31:0] = classd_phase2_cyc_qs;
+      end
+
+      addr_hit[56]: begin
+        reg_rdata_next[31:0] = classd_phase3_cyc_qs;
+      end
+
+      addr_hit[57]: begin
+        reg_rdata_next[31:0] = classd_esc_cnt_qs;
+      end
+
+      addr_hit[58]: begin
+        reg_rdata_next[2:0] = classd_state_qs;
+      end
+
+      default: begin
+        reg_rdata_next = '1;
+      end
+    endcase
+  end
+
+  // Assertions for Register Interface
+  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
+
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+  // this is formulated as an assumption such that the FPV testbenches do disprove this
+  // property by mistake
+  `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
+
+endmodule
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
index b9d16ba..2106f27 100644
--- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@
     { name: "NumSrc",
       desc: "Number of interrupt sources",
       type: "int",
-      default: "55",
+      default: "63",
       local: "true"
     },
     { name: "NumTarget",
@@ -501,7 +501,71 @@
         { bits: "1:0" }
       ],
     }
-    { skipto: "256" }
+    { name: "PRIO55",
+      desc: "Interrupt Source 55 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO56",
+      desc: "Interrupt Source 56 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO57",
+      desc: "Interrupt Source 57 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO58",
+      desc: "Interrupt Source 58 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO59",
+      desc: "Interrupt Source 59 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO60",
+      desc: "Interrupt Source 60 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO61",
+      desc: "Interrupt Source 61 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO62",
+      desc: "Interrupt Source 62 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { skipto: "512" }
     { multireg: {
         name: "IE0",
         desc: "Interrupt Enable for Target 0",
@@ -523,7 +587,8 @@
       ],
     }
     { name: "CC0",
-      desc: "Claim interrupt by read, complete interrupt by write for Target 0. Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.",
+      desc: '''Claim interrupt by read, complete interrupt by write for Target 0.
+      Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
       swaccess: "rw",
       hwaccess: "hrw",
       hwext: "true",
@@ -534,7 +599,8 @@
       ],
     }
     { name: "MSIP0",
-      desc: "msip for Hart 0. Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear",
+      desc: '''msip for Hart 0.
+      Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''',
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index aae343c..28acb95 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -151,11 +151,19 @@
   assign prio[52] = reg2hw.prio52.q;
   assign prio[53] = reg2hw.prio53.q;
   assign prio[54] = reg2hw.prio54.q;
+  assign prio[55] = reg2hw.prio55.q;
+  assign prio[56] = reg2hw.prio56.q;
+  assign prio[57] = reg2hw.prio57.q;
+  assign prio[58] = reg2hw.prio58.q;
+  assign prio[59] = reg2hw.prio59.q;
+  assign prio[60] = reg2hw.prio60.q;
+  assign prio[61] = reg2hw.prio61.q;
+  assign prio[62] = reg2hw.prio62.q;
 
   //////////////////////
   // Interrupt Enable //
   //////////////////////
-  for (genvar s = 0; s < 55; s++) begin : gen_ie0
+  for (genvar s = 0; s < 63; s++) begin : gen_ie0
     assign ie[0][s] = reg2hw.ie0[s].q;
   end
 
@@ -181,7 +189,7 @@
   ////////
   // IP //
   ////////
-  for (genvar s = 0; s < 55; s++) begin : gen_ip
+  for (genvar s = 0; s < 63; s++) begin : gen_ip
     assign hw2reg.ip[s].de = 1'b1; // Always write
     assign hw2reg.ip[s].d  = ip[s];
   end
@@ -189,7 +197,7 @@
   ///////////////////////////////////
   // Detection:: 0: Level, 1: Edge //
   ///////////////////////////////////
-  for (genvar s = 0; s < 55; s++) begin : gen_le
+  for (genvar s = 0; s < 63; s++) begin : gen_le
     assign le[s] = reg2hw.le[s].q;
   end
 
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
index 6a52203..dabca79 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,7 +7,7 @@
 package rv_plic_reg_pkg;
 
   // Param list
-  localparam int NumSrc = 55;
+  localparam int NumSrc = 63;
   localparam int NumTarget = 1;
 
   ////////////////////////////
@@ -238,6 +238,38 @@
   } rv_plic_reg2hw_prio54_reg_t;
 
   typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio55_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio56_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio57_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio58_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio59_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio60_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio61_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio62_reg_t;
+
+  typedef struct packed {
     logic        q;
   } rv_plic_reg2hw_ie0_mreg_t;
 
@@ -270,63 +302,71 @@
   // Register to internal design logic //
   ///////////////////////////////////////
   typedef struct packed {
-    rv_plic_reg2hw_le_mreg_t [54:0] le; // [230:176]
-    rv_plic_reg2hw_prio0_reg_t prio0; // [175:174]
-    rv_plic_reg2hw_prio1_reg_t prio1; // [173:172]
-    rv_plic_reg2hw_prio2_reg_t prio2; // [171:170]
-    rv_plic_reg2hw_prio3_reg_t prio3; // [169:168]
-    rv_plic_reg2hw_prio4_reg_t prio4; // [167:166]
-    rv_plic_reg2hw_prio5_reg_t prio5; // [165:164]
-    rv_plic_reg2hw_prio6_reg_t prio6; // [163:162]
-    rv_plic_reg2hw_prio7_reg_t prio7; // [161:160]
-    rv_plic_reg2hw_prio8_reg_t prio8; // [159:158]
-    rv_plic_reg2hw_prio9_reg_t prio9; // [157:156]
-    rv_plic_reg2hw_prio10_reg_t prio10; // [155:154]
-    rv_plic_reg2hw_prio11_reg_t prio11; // [153:152]
-    rv_plic_reg2hw_prio12_reg_t prio12; // [151:150]
-    rv_plic_reg2hw_prio13_reg_t prio13; // [149:148]
-    rv_plic_reg2hw_prio14_reg_t prio14; // [147:146]
-    rv_plic_reg2hw_prio15_reg_t prio15; // [145:144]
-    rv_plic_reg2hw_prio16_reg_t prio16; // [143:142]
-    rv_plic_reg2hw_prio17_reg_t prio17; // [141:140]
-    rv_plic_reg2hw_prio18_reg_t prio18; // [139:138]
-    rv_plic_reg2hw_prio19_reg_t prio19; // [137:136]
-    rv_plic_reg2hw_prio20_reg_t prio20; // [135:134]
-    rv_plic_reg2hw_prio21_reg_t prio21; // [133:132]
-    rv_plic_reg2hw_prio22_reg_t prio22; // [131:130]
-    rv_plic_reg2hw_prio23_reg_t prio23; // [129:128]
-    rv_plic_reg2hw_prio24_reg_t prio24; // [127:126]
-    rv_plic_reg2hw_prio25_reg_t prio25; // [125:124]
-    rv_plic_reg2hw_prio26_reg_t prio26; // [123:122]
-    rv_plic_reg2hw_prio27_reg_t prio27; // [121:120]
-    rv_plic_reg2hw_prio28_reg_t prio28; // [119:118]
-    rv_plic_reg2hw_prio29_reg_t prio29; // [117:116]
-    rv_plic_reg2hw_prio30_reg_t prio30; // [115:114]
-    rv_plic_reg2hw_prio31_reg_t prio31; // [113:112]
-    rv_plic_reg2hw_prio32_reg_t prio32; // [111:110]
-    rv_plic_reg2hw_prio33_reg_t prio33; // [109:108]
-    rv_plic_reg2hw_prio34_reg_t prio34; // [107:106]
-    rv_plic_reg2hw_prio35_reg_t prio35; // [105:104]
-    rv_plic_reg2hw_prio36_reg_t prio36; // [103:102]
-    rv_plic_reg2hw_prio37_reg_t prio37; // [101:100]
-    rv_plic_reg2hw_prio38_reg_t prio38; // [99:98]
-    rv_plic_reg2hw_prio39_reg_t prio39; // [97:96]
-    rv_plic_reg2hw_prio40_reg_t prio40; // [95:94]
-    rv_plic_reg2hw_prio41_reg_t prio41; // [93:92]
-    rv_plic_reg2hw_prio42_reg_t prio42; // [91:90]
-    rv_plic_reg2hw_prio43_reg_t prio43; // [89:88]
-    rv_plic_reg2hw_prio44_reg_t prio44; // [87:86]
-    rv_plic_reg2hw_prio45_reg_t prio45; // [85:84]
-    rv_plic_reg2hw_prio46_reg_t prio46; // [83:82]
-    rv_plic_reg2hw_prio47_reg_t prio47; // [81:80]
-    rv_plic_reg2hw_prio48_reg_t prio48; // [79:78]
-    rv_plic_reg2hw_prio49_reg_t prio49; // [77:76]
-    rv_plic_reg2hw_prio50_reg_t prio50; // [75:74]
-    rv_plic_reg2hw_prio51_reg_t prio51; // [73:72]
-    rv_plic_reg2hw_prio52_reg_t prio52; // [71:70]
-    rv_plic_reg2hw_prio53_reg_t prio53; // [69:68]
-    rv_plic_reg2hw_prio54_reg_t prio54; // [67:66]
-    rv_plic_reg2hw_ie0_mreg_t [54:0] ie0; // [65:11]
+    rv_plic_reg2hw_le_mreg_t [62:0] le; // [262:200]
+    rv_plic_reg2hw_prio0_reg_t prio0; // [199:198]
+    rv_plic_reg2hw_prio1_reg_t prio1; // [197:196]
+    rv_plic_reg2hw_prio2_reg_t prio2; // [195:194]
+    rv_plic_reg2hw_prio3_reg_t prio3; // [193:192]
+    rv_plic_reg2hw_prio4_reg_t prio4; // [191:190]
+    rv_plic_reg2hw_prio5_reg_t prio5; // [189:188]
+    rv_plic_reg2hw_prio6_reg_t prio6; // [187:186]
+    rv_plic_reg2hw_prio7_reg_t prio7; // [185:184]
+    rv_plic_reg2hw_prio8_reg_t prio8; // [183:182]
+    rv_plic_reg2hw_prio9_reg_t prio9; // [181:180]
+    rv_plic_reg2hw_prio10_reg_t prio10; // [179:178]
+    rv_plic_reg2hw_prio11_reg_t prio11; // [177:176]
+    rv_plic_reg2hw_prio12_reg_t prio12; // [175:174]
+    rv_plic_reg2hw_prio13_reg_t prio13; // [173:172]
+    rv_plic_reg2hw_prio14_reg_t prio14; // [171:170]
+    rv_plic_reg2hw_prio15_reg_t prio15; // [169:168]
+    rv_plic_reg2hw_prio16_reg_t prio16; // [167:166]
+    rv_plic_reg2hw_prio17_reg_t prio17; // [165:164]
+    rv_plic_reg2hw_prio18_reg_t prio18; // [163:162]
+    rv_plic_reg2hw_prio19_reg_t prio19; // [161:160]
+    rv_plic_reg2hw_prio20_reg_t prio20; // [159:158]
+    rv_plic_reg2hw_prio21_reg_t prio21; // [157:156]
+    rv_plic_reg2hw_prio22_reg_t prio22; // [155:154]
+    rv_plic_reg2hw_prio23_reg_t prio23; // [153:152]
+    rv_plic_reg2hw_prio24_reg_t prio24; // [151:150]
+    rv_plic_reg2hw_prio25_reg_t prio25; // [149:148]
+    rv_plic_reg2hw_prio26_reg_t prio26; // [147:146]
+    rv_plic_reg2hw_prio27_reg_t prio27; // [145:144]
+    rv_plic_reg2hw_prio28_reg_t prio28; // [143:142]
+    rv_plic_reg2hw_prio29_reg_t prio29; // [141:140]
+    rv_plic_reg2hw_prio30_reg_t prio30; // [139:138]
+    rv_plic_reg2hw_prio31_reg_t prio31; // [137:136]
+    rv_plic_reg2hw_prio32_reg_t prio32; // [135:134]
+    rv_plic_reg2hw_prio33_reg_t prio33; // [133:132]
+    rv_plic_reg2hw_prio34_reg_t prio34; // [131:130]
+    rv_plic_reg2hw_prio35_reg_t prio35; // [129:128]
+    rv_plic_reg2hw_prio36_reg_t prio36; // [127:126]
+    rv_plic_reg2hw_prio37_reg_t prio37; // [125:124]
+    rv_plic_reg2hw_prio38_reg_t prio38; // [123:122]
+    rv_plic_reg2hw_prio39_reg_t prio39; // [121:120]
+    rv_plic_reg2hw_prio40_reg_t prio40; // [119:118]
+    rv_plic_reg2hw_prio41_reg_t prio41; // [117:116]
+    rv_plic_reg2hw_prio42_reg_t prio42; // [115:114]
+    rv_plic_reg2hw_prio43_reg_t prio43; // [113:112]
+    rv_plic_reg2hw_prio44_reg_t prio44; // [111:110]
+    rv_plic_reg2hw_prio45_reg_t prio45; // [109:108]
+    rv_plic_reg2hw_prio46_reg_t prio46; // [107:106]
+    rv_plic_reg2hw_prio47_reg_t prio47; // [105:104]
+    rv_plic_reg2hw_prio48_reg_t prio48; // [103:102]
+    rv_plic_reg2hw_prio49_reg_t prio49; // [101:100]
+    rv_plic_reg2hw_prio50_reg_t prio50; // [99:98]
+    rv_plic_reg2hw_prio51_reg_t prio51; // [97:96]
+    rv_plic_reg2hw_prio52_reg_t prio52; // [95:94]
+    rv_plic_reg2hw_prio53_reg_t prio53; // [93:92]
+    rv_plic_reg2hw_prio54_reg_t prio54; // [91:90]
+    rv_plic_reg2hw_prio55_reg_t prio55; // [89:88]
+    rv_plic_reg2hw_prio56_reg_t prio56; // [87:86]
+    rv_plic_reg2hw_prio57_reg_t prio57; // [85:84]
+    rv_plic_reg2hw_prio58_reg_t prio58; // [83:82]
+    rv_plic_reg2hw_prio59_reg_t prio59; // [81:80]
+    rv_plic_reg2hw_prio60_reg_t prio60; // [79:78]
+    rv_plic_reg2hw_prio61_reg_t prio61; // [77:76]
+    rv_plic_reg2hw_prio62_reg_t prio62; // [75:74]
+    rv_plic_reg2hw_ie0_mreg_t [62:0] ie0; // [73:11]
     rv_plic_reg2hw_threshold0_reg_t threshold0; // [10:9]
     rv_plic_reg2hw_cc0_reg_t cc0; // [8:1]
     rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
@@ -336,75 +376,83 @@
   // Internal design logic to register //
   ///////////////////////////////////////
   typedef struct packed {
-    rv_plic_hw2reg_ip_mreg_t [54:0] ip; // [115:6]
+    rv_plic_hw2reg_ip_mreg_t [62:0] ip; // [131:6]
     rv_plic_hw2reg_cc0_reg_t cc0; // [5:-2]
   } rv_plic_hw2reg_t;
 
   // Register Address
-  parameter RV_PLIC_IP0_OFFSET = 9'h 0;
-  parameter RV_PLIC_IP1_OFFSET = 9'h 4;
-  parameter RV_PLIC_LE0_OFFSET = 9'h 8;
-  parameter RV_PLIC_LE1_OFFSET = 9'h c;
-  parameter RV_PLIC_PRIO0_OFFSET = 9'h 10;
-  parameter RV_PLIC_PRIO1_OFFSET = 9'h 14;
-  parameter RV_PLIC_PRIO2_OFFSET = 9'h 18;
-  parameter RV_PLIC_PRIO3_OFFSET = 9'h 1c;
-  parameter RV_PLIC_PRIO4_OFFSET = 9'h 20;
-  parameter RV_PLIC_PRIO5_OFFSET = 9'h 24;
-  parameter RV_PLIC_PRIO6_OFFSET = 9'h 28;
-  parameter RV_PLIC_PRIO7_OFFSET = 9'h 2c;
-  parameter RV_PLIC_PRIO8_OFFSET = 9'h 30;
-  parameter RV_PLIC_PRIO9_OFFSET = 9'h 34;
-  parameter RV_PLIC_PRIO10_OFFSET = 9'h 38;
-  parameter RV_PLIC_PRIO11_OFFSET = 9'h 3c;
-  parameter RV_PLIC_PRIO12_OFFSET = 9'h 40;
-  parameter RV_PLIC_PRIO13_OFFSET = 9'h 44;
-  parameter RV_PLIC_PRIO14_OFFSET = 9'h 48;
-  parameter RV_PLIC_PRIO15_OFFSET = 9'h 4c;
-  parameter RV_PLIC_PRIO16_OFFSET = 9'h 50;
-  parameter RV_PLIC_PRIO17_OFFSET = 9'h 54;
-  parameter RV_PLIC_PRIO18_OFFSET = 9'h 58;
-  parameter RV_PLIC_PRIO19_OFFSET = 9'h 5c;
-  parameter RV_PLIC_PRIO20_OFFSET = 9'h 60;
-  parameter RV_PLIC_PRIO21_OFFSET = 9'h 64;
-  parameter RV_PLIC_PRIO22_OFFSET = 9'h 68;
-  parameter RV_PLIC_PRIO23_OFFSET = 9'h 6c;
-  parameter RV_PLIC_PRIO24_OFFSET = 9'h 70;
-  parameter RV_PLIC_PRIO25_OFFSET = 9'h 74;
-  parameter RV_PLIC_PRIO26_OFFSET = 9'h 78;
-  parameter RV_PLIC_PRIO27_OFFSET = 9'h 7c;
-  parameter RV_PLIC_PRIO28_OFFSET = 9'h 80;
-  parameter RV_PLIC_PRIO29_OFFSET = 9'h 84;
-  parameter RV_PLIC_PRIO30_OFFSET = 9'h 88;
-  parameter RV_PLIC_PRIO31_OFFSET = 9'h 8c;
-  parameter RV_PLIC_PRIO32_OFFSET = 9'h 90;
-  parameter RV_PLIC_PRIO33_OFFSET = 9'h 94;
-  parameter RV_PLIC_PRIO34_OFFSET = 9'h 98;
-  parameter RV_PLIC_PRIO35_OFFSET = 9'h 9c;
-  parameter RV_PLIC_PRIO36_OFFSET = 9'h a0;
-  parameter RV_PLIC_PRIO37_OFFSET = 9'h a4;
-  parameter RV_PLIC_PRIO38_OFFSET = 9'h a8;
-  parameter RV_PLIC_PRIO39_OFFSET = 9'h ac;
-  parameter RV_PLIC_PRIO40_OFFSET = 9'h b0;
-  parameter RV_PLIC_PRIO41_OFFSET = 9'h b4;
-  parameter RV_PLIC_PRIO42_OFFSET = 9'h b8;
-  parameter RV_PLIC_PRIO43_OFFSET = 9'h bc;
-  parameter RV_PLIC_PRIO44_OFFSET = 9'h c0;
-  parameter RV_PLIC_PRIO45_OFFSET = 9'h c4;
-  parameter RV_PLIC_PRIO46_OFFSET = 9'h c8;
-  parameter RV_PLIC_PRIO47_OFFSET = 9'h cc;
-  parameter RV_PLIC_PRIO48_OFFSET = 9'h d0;
-  parameter RV_PLIC_PRIO49_OFFSET = 9'h d4;
-  parameter RV_PLIC_PRIO50_OFFSET = 9'h d8;
-  parameter RV_PLIC_PRIO51_OFFSET = 9'h dc;
-  parameter RV_PLIC_PRIO52_OFFSET = 9'h e0;
-  parameter RV_PLIC_PRIO53_OFFSET = 9'h e4;
-  parameter RV_PLIC_PRIO54_OFFSET = 9'h e8;
-  parameter RV_PLIC_IE00_OFFSET = 9'h 100;
-  parameter RV_PLIC_IE01_OFFSET = 9'h 104;
-  parameter RV_PLIC_THRESHOLD0_OFFSET = 9'h 108;
-  parameter RV_PLIC_CC0_OFFSET = 9'h 10c;
-  parameter RV_PLIC_MSIP0_OFFSET = 9'h 110;
+  parameter RV_PLIC_IP0_OFFSET = 10'h 0;
+  parameter RV_PLIC_IP1_OFFSET = 10'h 4;
+  parameter RV_PLIC_LE0_OFFSET = 10'h 8;
+  parameter RV_PLIC_LE1_OFFSET = 10'h c;
+  parameter RV_PLIC_PRIO0_OFFSET = 10'h 10;
+  parameter RV_PLIC_PRIO1_OFFSET = 10'h 14;
+  parameter RV_PLIC_PRIO2_OFFSET = 10'h 18;
+  parameter RV_PLIC_PRIO3_OFFSET = 10'h 1c;
+  parameter RV_PLIC_PRIO4_OFFSET = 10'h 20;
+  parameter RV_PLIC_PRIO5_OFFSET = 10'h 24;
+  parameter RV_PLIC_PRIO6_OFFSET = 10'h 28;
+  parameter RV_PLIC_PRIO7_OFFSET = 10'h 2c;
+  parameter RV_PLIC_PRIO8_OFFSET = 10'h 30;
+  parameter RV_PLIC_PRIO9_OFFSET = 10'h 34;
+  parameter RV_PLIC_PRIO10_OFFSET = 10'h 38;
+  parameter RV_PLIC_PRIO11_OFFSET = 10'h 3c;
+  parameter RV_PLIC_PRIO12_OFFSET = 10'h 40;
+  parameter RV_PLIC_PRIO13_OFFSET = 10'h 44;
+  parameter RV_PLIC_PRIO14_OFFSET = 10'h 48;
+  parameter RV_PLIC_PRIO15_OFFSET = 10'h 4c;
+  parameter RV_PLIC_PRIO16_OFFSET = 10'h 50;
+  parameter RV_PLIC_PRIO17_OFFSET = 10'h 54;
+  parameter RV_PLIC_PRIO18_OFFSET = 10'h 58;
+  parameter RV_PLIC_PRIO19_OFFSET = 10'h 5c;
+  parameter RV_PLIC_PRIO20_OFFSET = 10'h 60;
+  parameter RV_PLIC_PRIO21_OFFSET = 10'h 64;
+  parameter RV_PLIC_PRIO22_OFFSET = 10'h 68;
+  parameter RV_PLIC_PRIO23_OFFSET = 10'h 6c;
+  parameter RV_PLIC_PRIO24_OFFSET = 10'h 70;
+  parameter RV_PLIC_PRIO25_OFFSET = 10'h 74;
+  parameter RV_PLIC_PRIO26_OFFSET = 10'h 78;
+  parameter RV_PLIC_PRIO27_OFFSET = 10'h 7c;
+  parameter RV_PLIC_PRIO28_OFFSET = 10'h 80;
+  parameter RV_PLIC_PRIO29_OFFSET = 10'h 84;
+  parameter RV_PLIC_PRIO30_OFFSET = 10'h 88;
+  parameter RV_PLIC_PRIO31_OFFSET = 10'h 8c;
+  parameter RV_PLIC_PRIO32_OFFSET = 10'h 90;
+  parameter RV_PLIC_PRIO33_OFFSET = 10'h 94;
+  parameter RV_PLIC_PRIO34_OFFSET = 10'h 98;
+  parameter RV_PLIC_PRIO35_OFFSET = 10'h 9c;
+  parameter RV_PLIC_PRIO36_OFFSET = 10'h a0;
+  parameter RV_PLIC_PRIO37_OFFSET = 10'h a4;
+  parameter RV_PLIC_PRIO38_OFFSET = 10'h a8;
+  parameter RV_PLIC_PRIO39_OFFSET = 10'h ac;
+  parameter RV_PLIC_PRIO40_OFFSET = 10'h b0;
+  parameter RV_PLIC_PRIO41_OFFSET = 10'h b4;
+  parameter RV_PLIC_PRIO42_OFFSET = 10'h b8;
+  parameter RV_PLIC_PRIO43_OFFSET = 10'h bc;
+  parameter RV_PLIC_PRIO44_OFFSET = 10'h c0;
+  parameter RV_PLIC_PRIO45_OFFSET = 10'h c4;
+  parameter RV_PLIC_PRIO46_OFFSET = 10'h c8;
+  parameter RV_PLIC_PRIO47_OFFSET = 10'h cc;
+  parameter RV_PLIC_PRIO48_OFFSET = 10'h d0;
+  parameter RV_PLIC_PRIO49_OFFSET = 10'h d4;
+  parameter RV_PLIC_PRIO50_OFFSET = 10'h d8;
+  parameter RV_PLIC_PRIO51_OFFSET = 10'h dc;
+  parameter RV_PLIC_PRIO52_OFFSET = 10'h e0;
+  parameter RV_PLIC_PRIO53_OFFSET = 10'h e4;
+  parameter RV_PLIC_PRIO54_OFFSET = 10'h e8;
+  parameter RV_PLIC_PRIO55_OFFSET = 10'h ec;
+  parameter RV_PLIC_PRIO56_OFFSET = 10'h f0;
+  parameter RV_PLIC_PRIO57_OFFSET = 10'h f4;
+  parameter RV_PLIC_PRIO58_OFFSET = 10'h f8;
+  parameter RV_PLIC_PRIO59_OFFSET = 10'h fc;
+  parameter RV_PLIC_PRIO60_OFFSET = 10'h 100;
+  parameter RV_PLIC_PRIO61_OFFSET = 10'h 104;
+  parameter RV_PLIC_PRIO62_OFFSET = 10'h 108;
+  parameter RV_PLIC_IE00_OFFSET = 10'h 200;
+  parameter RV_PLIC_IE01_OFFSET = 10'h 204;
+  parameter RV_PLIC_THRESHOLD0_OFFSET = 10'h 208;
+  parameter RV_PLIC_CC0_OFFSET = 10'h 20c;
+  parameter RV_PLIC_MSIP0_OFFSET = 10'h 210;
 
 
   // Register Index
@@ -468,6 +516,14 @@
     RV_PLIC_PRIO52,
     RV_PLIC_PRIO53,
     RV_PLIC_PRIO54,
+    RV_PLIC_PRIO55,
+    RV_PLIC_PRIO56,
+    RV_PLIC_PRIO57,
+    RV_PLIC_PRIO58,
+    RV_PLIC_PRIO59,
+    RV_PLIC_PRIO60,
+    RV_PLIC_PRIO61,
+    RV_PLIC_PRIO62,
     RV_PLIC_IE00,
     RV_PLIC_IE01,
     RV_PLIC_THRESHOLD0,
@@ -476,11 +532,11 @@
   } rv_plic_id_e;
 
   // Register width information to check illegal writes
-  localparam logic [3:0] RV_PLIC_PERMIT [64] = '{
+  localparam logic [3:0] RV_PLIC_PERMIT [72] = '{
     4'b 1111, // index[ 0] RV_PLIC_IP0
-    4'b 0111, // index[ 1] RV_PLIC_IP1
+    4'b 1111, // index[ 1] RV_PLIC_IP1
     4'b 1111, // index[ 2] RV_PLIC_LE0
-    4'b 0111, // index[ 3] RV_PLIC_LE1
+    4'b 1111, // index[ 3] RV_PLIC_LE1
     4'b 0001, // index[ 4] RV_PLIC_PRIO0
     4'b 0001, // index[ 5] RV_PLIC_PRIO1
     4'b 0001, // index[ 6] RV_PLIC_PRIO2
@@ -536,11 +592,19 @@
     4'b 0001, // index[56] RV_PLIC_PRIO52
     4'b 0001, // index[57] RV_PLIC_PRIO53
     4'b 0001, // index[58] RV_PLIC_PRIO54
-    4'b 1111, // index[59] RV_PLIC_IE00
-    4'b 0111, // index[60] RV_PLIC_IE01
-    4'b 0001, // index[61] RV_PLIC_THRESHOLD0
-    4'b 0001, // index[62] RV_PLIC_CC0
-    4'b 0001  // index[63] RV_PLIC_MSIP0
+    4'b 0001, // index[59] RV_PLIC_PRIO55
+    4'b 0001, // index[60] RV_PLIC_PRIO56
+    4'b 0001, // index[61] RV_PLIC_PRIO57
+    4'b 0001, // index[62] RV_PLIC_PRIO58
+    4'b 0001, // index[63] RV_PLIC_PRIO59
+    4'b 0001, // index[64] RV_PLIC_PRIO60
+    4'b 0001, // index[65] RV_PLIC_PRIO61
+    4'b 0001, // index[66] RV_PLIC_PRIO62
+    4'b 1111, // index[67] RV_PLIC_IE00
+    4'b 1111, // index[68] RV_PLIC_IE01
+    4'b 0001, // index[69] RV_PLIC_THRESHOLD0
+    4'b 0001, // index[70] RV_PLIC_CC0
+    4'b 0001  // index[71] RV_PLIC_MSIP0
   };
 endpackage
 
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index c91a113..f9138ae 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -21,7 +21,7 @@
 
   import rv_plic_reg_pkg::* ;
 
-  localparam AW = 9;
+  localparam AW = 10;
   localparam DW = 32;
   localparam DBW = DW/8;                    // Byte Width
 
@@ -124,6 +124,14 @@
   logic ip1_p52_qs;
   logic ip1_p53_qs;
   logic ip1_p54_qs;
+  logic ip1_p55_qs;
+  logic ip1_p56_qs;
+  logic ip1_p57_qs;
+  logic ip1_p58_qs;
+  logic ip1_p59_qs;
+  logic ip1_p60_qs;
+  logic ip1_p61_qs;
+  logic ip1_p62_qs;
   logic le0_le0_qs;
   logic le0_le0_wd;
   logic le0_le0_we;
@@ -289,6 +297,30 @@
   logic le1_le54_qs;
   logic le1_le54_wd;
   logic le1_le54_we;
+  logic le1_le55_qs;
+  logic le1_le55_wd;
+  logic le1_le55_we;
+  logic le1_le56_qs;
+  logic le1_le56_wd;
+  logic le1_le56_we;
+  logic le1_le57_qs;
+  logic le1_le57_wd;
+  logic le1_le57_we;
+  logic le1_le58_qs;
+  logic le1_le58_wd;
+  logic le1_le58_we;
+  logic le1_le59_qs;
+  logic le1_le59_wd;
+  logic le1_le59_we;
+  logic le1_le60_qs;
+  logic le1_le60_wd;
+  logic le1_le60_we;
+  logic le1_le61_qs;
+  logic le1_le61_wd;
+  logic le1_le61_we;
+  logic le1_le62_qs;
+  logic le1_le62_wd;
+  logic le1_le62_we;
   logic [1:0] prio0_qs;
   logic [1:0] prio0_wd;
   logic prio0_we;
@@ -454,6 +486,30 @@
   logic [1:0] prio54_qs;
   logic [1:0] prio54_wd;
   logic prio54_we;
+  logic [1:0] prio55_qs;
+  logic [1:0] prio55_wd;
+  logic prio55_we;
+  logic [1:0] prio56_qs;
+  logic [1:0] prio56_wd;
+  logic prio56_we;
+  logic [1:0] prio57_qs;
+  logic [1:0] prio57_wd;
+  logic prio57_we;
+  logic [1:0] prio58_qs;
+  logic [1:0] prio58_wd;
+  logic prio58_we;
+  logic [1:0] prio59_qs;
+  logic [1:0] prio59_wd;
+  logic prio59_we;
+  logic [1:0] prio60_qs;
+  logic [1:0] prio60_wd;
+  logic prio60_we;
+  logic [1:0] prio61_qs;
+  logic [1:0] prio61_wd;
+  logic prio61_we;
+  logic [1:0] prio62_qs;
+  logic [1:0] prio62_wd;
+  logic prio62_we;
   logic ie00_e0_qs;
   logic ie00_e0_wd;
   logic ie00_e0_we;
@@ -619,6 +675,30 @@
   logic ie01_e54_qs;
   logic ie01_e54_wd;
   logic ie01_e54_we;
+  logic ie01_e55_qs;
+  logic ie01_e55_wd;
+  logic ie01_e55_we;
+  logic ie01_e56_qs;
+  logic ie01_e56_wd;
+  logic ie01_e56_we;
+  logic ie01_e57_qs;
+  logic ie01_e57_wd;
+  logic ie01_e57_we;
+  logic ie01_e58_qs;
+  logic ie01_e58_wd;
+  logic ie01_e58_we;
+  logic ie01_e59_qs;
+  logic ie01_e59_wd;
+  logic ie01_e59_we;
+  logic ie01_e60_qs;
+  logic ie01_e60_wd;
+  logic ie01_e60_we;
+  logic ie01_e61_qs;
+  logic ie01_e61_wd;
+  logic ie01_e61_we;
+  logic ie01_e62_qs;
+  logic ie01_e62_wd;
+  logic ie01_e62_we;
   logic [1:0] threshold0_qs;
   logic [1:0] threshold0_wd;
   logic threshold0_we;
@@ -2013,6 +2093,206 @@
   );
 
 
+  // F[p55]: 23:23
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p55 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[55].de),
+    .d      (hw2reg.ip[55].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p55_qs)
+  );
+
+
+  // F[p56]: 24:24
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p56 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[56].de),
+    .d      (hw2reg.ip[56].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p56_qs)
+  );
+
+
+  // F[p57]: 25:25
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p57 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[57].de),
+    .d      (hw2reg.ip[57].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p57_qs)
+  );
+
+
+  // F[p58]: 26:26
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p58 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[58].de),
+    .d      (hw2reg.ip[58].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p58_qs)
+  );
+
+
+  // F[p59]: 27:27
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p59 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[59].de),
+    .d      (hw2reg.ip[59].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p59_qs)
+  );
+
+
+  // F[p60]: 28:28
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p60 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[60].de),
+    .d      (hw2reg.ip[60].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p60_qs)
+  );
+
+
+  // F[p61]: 29:29
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p61 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[61].de),
+    .d      (hw2reg.ip[61].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p61_qs)
+  );
+
+
+  // F[p62]: 30:30
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip1_p62 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[62].de),
+    .d      (hw2reg.ip[62].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip1_p62_qs)
+  );
+
+
 
 
   // Subregister 0 of Multireg le
@@ -3451,6 +3731,214 @@
   );
 
 
+  // F[le55]: 23:23
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le55 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le55_we),
+    .wd     (le1_le55_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[55].q ),
+
+    // to register interface (read)
+    .qs     (le1_le55_qs)
+  );
+
+
+  // F[le56]: 24:24
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le56 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le56_we),
+    .wd     (le1_le56_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[56].q ),
+
+    // to register interface (read)
+    .qs     (le1_le56_qs)
+  );
+
+
+  // F[le57]: 25:25
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le57 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le57_we),
+    .wd     (le1_le57_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[57].q ),
+
+    // to register interface (read)
+    .qs     (le1_le57_qs)
+  );
+
+
+  // F[le58]: 26:26
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le58 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le58_we),
+    .wd     (le1_le58_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[58].q ),
+
+    // to register interface (read)
+    .qs     (le1_le58_qs)
+  );
+
+
+  // F[le59]: 27:27
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le59 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le59_we),
+    .wd     (le1_le59_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[59].q ),
+
+    // to register interface (read)
+    .qs     (le1_le59_qs)
+  );
+
+
+  // F[le60]: 28:28
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le60 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le60_we),
+    .wd     (le1_le60_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[60].q ),
+
+    // to register interface (read)
+    .qs     (le1_le60_qs)
+  );
+
+
+  // F[le61]: 29:29
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le61 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le61_we),
+    .wd     (le1_le61_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[61].q ),
+
+    // to register interface (read)
+    .qs     (le1_le61_qs)
+  );
+
+
+  // F[le62]: 30:30
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le1_le62 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le1_le62_we),
+    .wd     (le1_le62_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[62].q ),
+
+    // to register interface (read)
+    .qs     (le1_le62_qs)
+  );
+
+
 
   // R[prio0]: V(False)
 
@@ -4937,6 +5425,222 @@
   );
 
 
+  // R[prio55]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio55 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio55_we),
+    .wd     (prio55_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio55.q ),
+
+    // to register interface (read)
+    .qs     (prio55_qs)
+  );
+
+
+  // R[prio56]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio56 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio56_we),
+    .wd     (prio56_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio56.q ),
+
+    // to register interface (read)
+    .qs     (prio56_qs)
+  );
+
+
+  // R[prio57]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio57 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio57_we),
+    .wd     (prio57_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio57.q ),
+
+    // to register interface (read)
+    .qs     (prio57_qs)
+  );
+
+
+  // R[prio58]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio58 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio58_we),
+    .wd     (prio58_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio58.q ),
+
+    // to register interface (read)
+    .qs     (prio58_qs)
+  );
+
+
+  // R[prio59]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio59 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio59_we),
+    .wd     (prio59_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio59.q ),
+
+    // to register interface (read)
+    .qs     (prio59_qs)
+  );
+
+
+  // R[prio60]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio60 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio60_we),
+    .wd     (prio60_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio60.q ),
+
+    // to register interface (read)
+    .qs     (prio60_qs)
+  );
+
+
+  // R[prio61]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio61 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio61_we),
+    .wd     (prio61_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio61.q ),
+
+    // to register interface (read)
+    .qs     (prio61_qs)
+  );
+
+
+  // R[prio62]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio62 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio62_we),
+    .wd     (prio62_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio62.q ),
+
+    // to register interface (read)
+    .qs     (prio62_qs)
+  );
+
+
 
   // Subregister 0 of Multireg ie0
   // R[ie00]: V(False)
@@ -6374,6 +7078,214 @@
   );
 
 
+  // F[e55]: 23:23
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e55 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e55_we),
+    .wd     (ie01_e55_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[55].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e55_qs)
+  );
+
+
+  // F[e56]: 24:24
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e56 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e56_we),
+    .wd     (ie01_e56_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[56].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e56_qs)
+  );
+
+
+  // F[e57]: 25:25
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e57 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e57_we),
+    .wd     (ie01_e57_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[57].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e57_qs)
+  );
+
+
+  // F[e58]: 26:26
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e58 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e58_we),
+    .wd     (ie01_e58_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[58].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e58_qs)
+  );
+
+
+  // F[e59]: 27:27
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e59 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e59_we),
+    .wd     (ie01_e59_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[59].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e59_qs)
+  );
+
+
+  // F[e60]: 28:28
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e60 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e60_we),
+    .wd     (ie01_e60_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[60].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e60_qs)
+  );
+
+
+  // F[e61]: 29:29
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e61 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e61_we),
+    .wd     (ie01_e61_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[61].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e61_qs)
+  );
+
+
+  // F[e62]: 30:30
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie01_e62 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie01_e62_we),
+    .wd     (ie01_e62_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[62].q ),
+
+    // to register interface (read)
+    .qs     (ie01_e62_qs)
+  );
+
+
 
   // R[threshold0]: V(False)
 
@@ -6447,7 +7359,7 @@
 
 
 
-  logic [63:0] addr_hit;
+  logic [71:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == RV_PLIC_IP0_OFFSET);
@@ -6509,11 +7421,19 @@
     addr_hit[56] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
     addr_hit[57] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
     addr_hit[58] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
-    addr_hit[59] = (reg_addr == RV_PLIC_IE00_OFFSET);
-    addr_hit[60] = (reg_addr == RV_PLIC_IE01_OFFSET);
-    addr_hit[61] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
-    addr_hit[62] = (reg_addr == RV_PLIC_CC0_OFFSET);
-    addr_hit[63] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+    addr_hit[59] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
+    addr_hit[60] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
+    addr_hit[61] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
+    addr_hit[62] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
+    addr_hit[63] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
+    addr_hit[64] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
+    addr_hit[65] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
+    addr_hit[66] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
+    addr_hit[67] = (reg_addr == RV_PLIC_IE00_OFFSET);
+    addr_hit[68] = (reg_addr == RV_PLIC_IE01_OFFSET);
+    addr_hit[69] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+    addr_hit[70] = (reg_addr == RV_PLIC_CC0_OFFSET);
+    addr_hit[71] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -6585,6 +7505,14 @@
     if (addr_hit[61] && reg_we && (RV_PLIC_PERMIT[61] != (RV_PLIC_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[62] && reg_we && (RV_PLIC_PERMIT[62] != (RV_PLIC_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[63] && reg_we && (RV_PLIC_PERMIT[63] != (RV_PLIC_PERMIT[63] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[64] && reg_we && (RV_PLIC_PERMIT[64] != (RV_PLIC_PERMIT[64] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[65] && reg_we && (RV_PLIC_PERMIT[65] != (RV_PLIC_PERMIT[65] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[66] && reg_we && (RV_PLIC_PERMIT[66] != (RV_PLIC_PERMIT[66] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[67] && reg_we && (RV_PLIC_PERMIT[67] != (RV_PLIC_PERMIT[67] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[68] && reg_we && (RV_PLIC_PERMIT[68] != (RV_PLIC_PERMIT[68] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[69] && reg_we && (RV_PLIC_PERMIT[69] != (RV_PLIC_PERMIT[69] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[70] && reg_we && (RV_PLIC_PERMIT[70] != (RV_PLIC_PERMIT[70] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[71] && reg_we && (RV_PLIC_PERMIT[71] != (RV_PLIC_PERMIT[71] & reg_be))) wr_err = 1'b1 ;
   end
 
 
@@ -6642,6 +7570,14 @@
 
 
 
+
+
+
+
+
+
+
+
   assign le0_le0_we = addr_hit[2] & reg_we & ~wr_err;
   assign le0_le0_wd = reg_wdata[0];
 
@@ -6807,6 +7743,30 @@
   assign le1_le54_we = addr_hit[3] & reg_we & ~wr_err;
   assign le1_le54_wd = reg_wdata[22];
 
+  assign le1_le55_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le55_wd = reg_wdata[23];
+
+  assign le1_le56_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le56_wd = reg_wdata[24];
+
+  assign le1_le57_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le57_wd = reg_wdata[25];
+
+  assign le1_le58_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le58_wd = reg_wdata[26];
+
+  assign le1_le59_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le59_wd = reg_wdata[27];
+
+  assign le1_le60_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le60_wd = reg_wdata[28];
+
+  assign le1_le61_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le61_wd = reg_wdata[29];
+
+  assign le1_le62_we = addr_hit[3] & reg_we & ~wr_err;
+  assign le1_le62_wd = reg_wdata[30];
+
   assign prio0_we = addr_hit[4] & reg_we & ~wr_err;
   assign prio0_wd = reg_wdata[1:0];
 
@@ -6972,179 +7932,227 @@
   assign prio54_we = addr_hit[58] & reg_we & ~wr_err;
   assign prio54_wd = reg_wdata[1:0];
 
-  assign ie00_e0_we = addr_hit[59] & reg_we & ~wr_err;
+  assign prio55_we = addr_hit[59] & reg_we & ~wr_err;
+  assign prio55_wd = reg_wdata[1:0];
+
+  assign prio56_we = addr_hit[60] & reg_we & ~wr_err;
+  assign prio56_wd = reg_wdata[1:0];
+
+  assign prio57_we = addr_hit[61] & reg_we & ~wr_err;
+  assign prio57_wd = reg_wdata[1:0];
+
+  assign prio58_we = addr_hit[62] & reg_we & ~wr_err;
+  assign prio58_wd = reg_wdata[1:0];
+
+  assign prio59_we = addr_hit[63] & reg_we & ~wr_err;
+  assign prio59_wd = reg_wdata[1:0];
+
+  assign prio60_we = addr_hit[64] & reg_we & ~wr_err;
+  assign prio60_wd = reg_wdata[1:0];
+
+  assign prio61_we = addr_hit[65] & reg_we & ~wr_err;
+  assign prio61_wd = reg_wdata[1:0];
+
+  assign prio62_we = addr_hit[66] & reg_we & ~wr_err;
+  assign prio62_wd = reg_wdata[1:0];
+
+  assign ie00_e0_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e0_wd = reg_wdata[0];
 
-  assign ie00_e1_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e1_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e1_wd = reg_wdata[1];
 
-  assign ie00_e2_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e2_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e2_wd = reg_wdata[2];
 
-  assign ie00_e3_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e3_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e3_wd = reg_wdata[3];
 
-  assign ie00_e4_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e4_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e4_wd = reg_wdata[4];
 
-  assign ie00_e5_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e5_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e5_wd = reg_wdata[5];
 
-  assign ie00_e6_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e6_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e6_wd = reg_wdata[6];
 
-  assign ie00_e7_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e7_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e7_wd = reg_wdata[7];
 
-  assign ie00_e8_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e8_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e8_wd = reg_wdata[8];
 
-  assign ie00_e9_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e9_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e9_wd = reg_wdata[9];
 
-  assign ie00_e10_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e10_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e10_wd = reg_wdata[10];
 
-  assign ie00_e11_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e11_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e11_wd = reg_wdata[11];
 
-  assign ie00_e12_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e12_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e12_wd = reg_wdata[12];
 
-  assign ie00_e13_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e13_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e13_wd = reg_wdata[13];
 
-  assign ie00_e14_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e14_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e14_wd = reg_wdata[14];
 
-  assign ie00_e15_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e15_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e15_wd = reg_wdata[15];
 
-  assign ie00_e16_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e16_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e16_wd = reg_wdata[16];
 
-  assign ie00_e17_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e17_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e17_wd = reg_wdata[17];
 
-  assign ie00_e18_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e18_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e18_wd = reg_wdata[18];
 
-  assign ie00_e19_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e19_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e19_wd = reg_wdata[19];
 
-  assign ie00_e20_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e20_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e20_wd = reg_wdata[20];
 
-  assign ie00_e21_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e21_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e21_wd = reg_wdata[21];
 
-  assign ie00_e22_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e22_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e22_wd = reg_wdata[22];
 
-  assign ie00_e23_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e23_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e23_wd = reg_wdata[23];
 
-  assign ie00_e24_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e24_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e24_wd = reg_wdata[24];
 
-  assign ie00_e25_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e25_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e25_wd = reg_wdata[25];
 
-  assign ie00_e26_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e26_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e26_wd = reg_wdata[26];
 
-  assign ie00_e27_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e27_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e27_wd = reg_wdata[27];
 
-  assign ie00_e28_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e28_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e28_wd = reg_wdata[28];
 
-  assign ie00_e29_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e29_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e29_wd = reg_wdata[29];
 
-  assign ie00_e30_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e30_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e30_wd = reg_wdata[30];
 
-  assign ie00_e31_we = addr_hit[59] & reg_we & ~wr_err;
+  assign ie00_e31_we = addr_hit[67] & reg_we & ~wr_err;
   assign ie00_e31_wd = reg_wdata[31];
 
-  assign ie01_e32_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e32_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e32_wd = reg_wdata[0];
 
-  assign ie01_e33_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e33_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e33_wd = reg_wdata[1];
 
-  assign ie01_e34_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e34_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e34_wd = reg_wdata[2];
 
-  assign ie01_e35_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e35_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e35_wd = reg_wdata[3];
 
-  assign ie01_e36_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e36_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e36_wd = reg_wdata[4];
 
-  assign ie01_e37_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e37_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e37_wd = reg_wdata[5];
 
-  assign ie01_e38_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e38_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e38_wd = reg_wdata[6];
 
-  assign ie01_e39_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e39_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e39_wd = reg_wdata[7];
 
-  assign ie01_e40_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e40_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e40_wd = reg_wdata[8];
 
-  assign ie01_e41_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e41_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e41_wd = reg_wdata[9];
 
-  assign ie01_e42_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e42_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e42_wd = reg_wdata[10];
 
-  assign ie01_e43_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e43_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e43_wd = reg_wdata[11];
 
-  assign ie01_e44_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e44_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e44_wd = reg_wdata[12];
 
-  assign ie01_e45_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e45_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e45_wd = reg_wdata[13];
 
-  assign ie01_e46_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e46_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e46_wd = reg_wdata[14];
 
-  assign ie01_e47_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e47_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e47_wd = reg_wdata[15];
 
-  assign ie01_e48_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e48_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e48_wd = reg_wdata[16];
 
-  assign ie01_e49_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e49_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e49_wd = reg_wdata[17];
 
-  assign ie01_e50_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e50_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e50_wd = reg_wdata[18];
 
-  assign ie01_e51_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e51_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e51_wd = reg_wdata[19];
 
-  assign ie01_e52_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e52_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e52_wd = reg_wdata[20];
 
-  assign ie01_e53_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e53_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e53_wd = reg_wdata[21];
 
-  assign ie01_e54_we = addr_hit[60] & reg_we & ~wr_err;
+  assign ie01_e54_we = addr_hit[68] & reg_we & ~wr_err;
   assign ie01_e54_wd = reg_wdata[22];
 
-  assign threshold0_we = addr_hit[61] & reg_we & ~wr_err;
+  assign ie01_e55_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e55_wd = reg_wdata[23];
+
+  assign ie01_e56_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e56_wd = reg_wdata[24];
+
+  assign ie01_e57_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e57_wd = reg_wdata[25];
+
+  assign ie01_e58_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e58_wd = reg_wdata[26];
+
+  assign ie01_e59_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e59_wd = reg_wdata[27];
+
+  assign ie01_e60_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e60_wd = reg_wdata[28];
+
+  assign ie01_e61_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e61_wd = reg_wdata[29];
+
+  assign ie01_e62_we = addr_hit[68] & reg_we & ~wr_err;
+  assign ie01_e62_wd = reg_wdata[30];
+
+  assign threshold0_we = addr_hit[69] & reg_we & ~wr_err;
   assign threshold0_wd = reg_wdata[1:0];
 
-  assign cc0_we = addr_hit[62] & reg_we & ~wr_err;
+  assign cc0_we = addr_hit[70] & reg_we & ~wr_err;
   assign cc0_wd = reg_wdata[5:0];
-  assign cc0_re = addr_hit[62] && reg_re;
+  assign cc0_re = addr_hit[70] && reg_re;
 
-  assign msip0_we = addr_hit[63] & reg_we & ~wr_err;
+  assign msip0_we = addr_hit[71] & reg_we & ~wr_err;
   assign msip0_wd = reg_wdata[0];
 
   // Read data return
@@ -7210,6 +8218,14 @@
         reg_rdata_next[20] = ip1_p52_qs;
         reg_rdata_next[21] = ip1_p53_qs;
         reg_rdata_next[22] = ip1_p54_qs;
+        reg_rdata_next[23] = ip1_p55_qs;
+        reg_rdata_next[24] = ip1_p56_qs;
+        reg_rdata_next[25] = ip1_p57_qs;
+        reg_rdata_next[26] = ip1_p58_qs;
+        reg_rdata_next[27] = ip1_p59_qs;
+        reg_rdata_next[28] = ip1_p60_qs;
+        reg_rdata_next[29] = ip1_p61_qs;
+        reg_rdata_next[30] = ip1_p62_qs;
       end
 
       addr_hit[2]: begin
@@ -7271,6 +8287,14 @@
         reg_rdata_next[20] = le1_le52_qs;
         reg_rdata_next[21] = le1_le53_qs;
         reg_rdata_next[22] = le1_le54_qs;
+        reg_rdata_next[23] = le1_le55_qs;
+        reg_rdata_next[24] = le1_le56_qs;
+        reg_rdata_next[25] = le1_le57_qs;
+        reg_rdata_next[26] = le1_le58_qs;
+        reg_rdata_next[27] = le1_le59_qs;
+        reg_rdata_next[28] = le1_le60_qs;
+        reg_rdata_next[29] = le1_le61_qs;
+        reg_rdata_next[30] = le1_le62_qs;
       end
 
       addr_hit[4]: begin
@@ -7494,6 +8518,38 @@
       end
 
       addr_hit[59]: begin
+        reg_rdata_next[1:0] = prio55_qs;
+      end
+
+      addr_hit[60]: begin
+        reg_rdata_next[1:0] = prio56_qs;
+      end
+
+      addr_hit[61]: begin
+        reg_rdata_next[1:0] = prio57_qs;
+      end
+
+      addr_hit[62]: begin
+        reg_rdata_next[1:0] = prio58_qs;
+      end
+
+      addr_hit[63]: begin
+        reg_rdata_next[1:0] = prio59_qs;
+      end
+
+      addr_hit[64]: begin
+        reg_rdata_next[1:0] = prio60_qs;
+      end
+
+      addr_hit[65]: begin
+        reg_rdata_next[1:0] = prio61_qs;
+      end
+
+      addr_hit[66]: begin
+        reg_rdata_next[1:0] = prio62_qs;
+      end
+
+      addr_hit[67]: begin
         reg_rdata_next[0] = ie00_e0_qs;
         reg_rdata_next[1] = ie00_e1_qs;
         reg_rdata_next[2] = ie00_e2_qs;
@@ -7528,7 +8584,7 @@
         reg_rdata_next[31] = ie00_e31_qs;
       end
 
-      addr_hit[60]: begin
+      addr_hit[68]: begin
         reg_rdata_next[0] = ie01_e32_qs;
         reg_rdata_next[1] = ie01_e33_qs;
         reg_rdata_next[2] = ie01_e34_qs;
@@ -7552,17 +8608,25 @@
         reg_rdata_next[20] = ie01_e52_qs;
         reg_rdata_next[21] = ie01_e53_qs;
         reg_rdata_next[22] = ie01_e54_qs;
+        reg_rdata_next[23] = ie01_e55_qs;
+        reg_rdata_next[24] = ie01_e56_qs;
+        reg_rdata_next[25] = ie01_e57_qs;
+        reg_rdata_next[26] = ie01_e58_qs;
+        reg_rdata_next[27] = ie01_e59_qs;
+        reg_rdata_next[28] = ie01_e60_qs;
+        reg_rdata_next[29] = ie01_e61_qs;
+        reg_rdata_next[30] = ie01_e62_qs;
       end
 
-      addr_hit[61]: begin
+      addr_hit[69]: begin
         reg_rdata_next[1:0] = threshold0_qs;
       end
 
-      addr_hit[62]: begin
+      addr_hit[70]: begin
         reg_rdata_next[5:0] = cc0_qs;
       end
 
-      addr_hit[63]: begin
+      addr_hit[71]: begin
         reg_rdata_next[0] = msip0_qs;
       end
 
diff --git a/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson
index 676f05c..e377830 100644
--- a/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson
@@ -41,6 +41,8 @@
       hmac
       rv_plic
       pinmux
+      alert_handler
+      nmi_gen
     ]
     dm_sba:
     [
@@ -56,6 +58,8 @@
       hmac
       rv_plic
       pinmux
+      alert_handler
+      nmi_gen
     ]
   }
   nodes:
@@ -214,6 +218,26 @@
       pipeline_byp: "false"
       pipeline: "true"
     }
+    {
+      name: alert_handler
+      type: device
+      clock: main
+      inst_type: alert_handler
+      pipeline_byp: "false"
+      base_addr: 0x40130000
+      size_byte: 0x1000
+      pipeline: "true"
+    }
+    {
+      name: nmi_gen
+      type: device
+      clock: main
+      inst_type: nmi_gen
+      pipeline_byp: "false"
+      base_addr: 0x40140000
+      size_byte: 0x1000
+      pipeline: "true"
+    }
   ]
   clock: main
   type: xbar
diff --git a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
index be3cd61..913f600 100644
--- a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
+++ b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
@@ -104,6 +104,18 @@
     .h2d    (tl_pinmux_o),
     .d2h    (tl_pinmux_i)
   );
+  bind xbar_main tlul_assert tlul_assert_device_alert_handler (
+    .clk_i  (clk_main_i),
+    .rst_ni (rst_main_ni),
+    .h2d    (tl_alert_handler_o),
+    .d2h    (tl_alert_handler_i)
+  );
+  bind xbar_main tlul_assert tlul_assert_device_nmi_gen (
+    .clk_i  (clk_main_i),
+    .rst_ni (rst_main_ni),
+    .h2d    (tl_nmi_gen_o),
+    .d2h    (tl_nmi_gen_i)
+  );
 
 endmodule
 
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
index 84b2a90..84a257b 100644
--- a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
@@ -6,36 +6,40 @@
 
 package tl_main_pkg;
 
-  localparam logic [31:0] ADDR_SPACE_ROM        = 32'h 00008000;
-  localparam logic [31:0] ADDR_SPACE_DEBUG_MEM  = 32'h 1a110000;
-  localparam logic [31:0] ADDR_SPACE_RAM_MAIN   = 32'h 10000000;
-  localparam logic [31:0] ADDR_SPACE_EFLASH     = 32'h 20000000;
-  localparam logic [31:0] ADDR_SPACE_UART       = 32'h 40000000;
-  localparam logic [31:0] ADDR_SPACE_GPIO       = 32'h 40010000;
-  localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40020000;
-  localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 40030000;
-  localparam logic [31:0] ADDR_SPACE_RV_TIMER   = 32'h 40080000;
-  localparam logic [31:0] ADDR_SPACE_HMAC       = 32'h 40120000;
-  localparam logic [31:0] ADDR_SPACE_AES        = 32'h 40110000;
-  localparam logic [31:0] ADDR_SPACE_RV_PLIC    = 32'h 40090000;
-  localparam logic [31:0] ADDR_SPACE_PINMUX     = 32'h 40070000;
+  localparam logic [31:0] ADDR_SPACE_ROM           = 32'h 00008000;
+  localparam logic [31:0] ADDR_SPACE_DEBUG_MEM     = 32'h 1a110000;
+  localparam logic [31:0] ADDR_SPACE_RAM_MAIN      = 32'h 10000000;
+  localparam logic [31:0] ADDR_SPACE_EFLASH        = 32'h 20000000;
+  localparam logic [31:0] ADDR_SPACE_UART          = 32'h 40000000;
+  localparam logic [31:0] ADDR_SPACE_GPIO          = 32'h 40010000;
+  localparam logic [31:0] ADDR_SPACE_SPI_DEVICE    = 32'h 40020000;
+  localparam logic [31:0] ADDR_SPACE_FLASH_CTRL    = 32'h 40030000;
+  localparam logic [31:0] ADDR_SPACE_RV_TIMER      = 32'h 40080000;
+  localparam logic [31:0] ADDR_SPACE_HMAC          = 32'h 40120000;
+  localparam logic [31:0] ADDR_SPACE_AES           = 32'h 40110000;
+  localparam logic [31:0] ADDR_SPACE_RV_PLIC       = 32'h 40090000;
+  localparam logic [31:0] ADDR_SPACE_PINMUX        = 32'h 40070000;
+  localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40130000;
+  localparam logic [31:0] ADDR_SPACE_NMI_GEN       = 32'h 40140000;
 
-  localparam logic [31:0] ADDR_MASK_ROM        = 32'h 00001fff;
-  localparam logic [31:0] ADDR_MASK_DEBUG_MEM  = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_RAM_MAIN   = 32'h 0000ffff;
-  localparam logic [31:0] ADDR_MASK_EFLASH     = 32'h 0007ffff;
-  localparam logic [31:0] ADDR_MASK_UART       = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_GPIO       = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_RV_TIMER   = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_HMAC       = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_AES        = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_RV_PLIC    = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_PINMUX     = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_ROM           = 32'h 00001fff;
+  localparam logic [31:0] ADDR_MASK_DEBUG_MEM     = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_RAM_MAIN      = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_EFLASH        = 32'h 0007ffff;
+  localparam logic [31:0] ADDR_MASK_UART          = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_GPIO          = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_SPI_DEVICE    = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_FLASH_CTRL    = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_RV_TIMER      = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_HMAC          = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_AES           = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_RV_PLIC       = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_PINMUX        = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_NMI_GEN       = 32'h 00000fff;
 
   localparam int N_HOST   = 3;
-  localparam int N_DEVICE = 13;
+  localparam int N_DEVICE = 15;
 
   typedef enum int {
     TlRom = 0,
@@ -50,7 +54,9 @@
     TlHmac = 9,
     TlAes = 10,
     TlRvPlic = 11,
-    TlPinmux = 12
+    TlPinmux = 12,
+    TlAlertHandler = 13,
+    TlNmiGen = 14
   } tl_device_e;
 
   typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
index 80c5a72..2d3d421 100644
--- a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
@@ -7,69 +7,77 @@
 //
 // Interconnect
 // corei
-//   -> s1n_16
-//     -> sm1_17
-//       -> rom
-//     -> sm1_18
-//       -> debug_mem
+//   -> s1n_18
 //     -> sm1_19
-//       -> ram_main
+//       -> rom
 //     -> sm1_20
+//       -> debug_mem
+//     -> sm1_21
+//       -> ram_main
+//     -> sm1_22
 //       -> eflash
 // cored
-//   -> s1n_21
-//     -> sm1_17
+//   -> s1n_23
+//     -> sm1_19
 //       -> rom
-//     -> sm1_18
+//     -> sm1_20
 //       -> debug_mem
-//     -> sm1_19
+//     -> sm1_21
 //       -> ram_main
-//     -> sm1_20
-//       -> eflash
 //     -> sm1_22
-//       -> uart
-//     -> sm1_23
-//       -> gpio
+//       -> eflash
 //     -> sm1_24
-//       -> spi_device
+//       -> uart
 //     -> sm1_25
-//       -> flash_ctrl
+//       -> gpio
 //     -> sm1_26
-//       -> rv_timer
+//       -> spi_device
 //     -> sm1_27
-//       -> aes
+//       -> flash_ctrl
 //     -> sm1_28
-//       -> hmac
+//       -> rv_timer
 //     -> sm1_29
-//       -> rv_plic
+//       -> aes
 //     -> sm1_30
+//       -> hmac
+//     -> sm1_31
+//       -> rv_plic
+//     -> sm1_32
 //       -> pinmux
+//     -> sm1_33
+//       -> alert_handler
+//     -> sm1_34
+//       -> nmi_gen
 // dm_sba
-//   -> s1n_31
-//     -> sm1_17
-//       -> rom
+//   -> s1n_35
 //     -> sm1_19
+//       -> rom
+//     -> sm1_21
 //       -> ram_main
-//     -> sm1_20
-//       -> eflash
 //     -> sm1_22
-//       -> uart
-//     -> sm1_23
-//       -> gpio
+//       -> eflash
 //     -> sm1_24
-//       -> spi_device
+//       -> uart
 //     -> sm1_25
-//       -> flash_ctrl
+//       -> gpio
 //     -> sm1_26
-//       -> rv_timer
+//       -> spi_device
 //     -> sm1_27
-//       -> aes
+//       -> flash_ctrl
 //     -> sm1_28
-//       -> hmac
+//       -> rv_timer
 //     -> sm1_29
-//       -> rv_plic
+//       -> aes
 //     -> sm1_30
+//       -> hmac
+//     -> sm1_31
+//       -> rv_plic
+//     -> sm1_32
 //       -> pinmux
+//     -> sm1_33
+//       -> alert_handler
+//     -> sm1_34
+//       -> nmi_gen
 
 module xbar_main (
   input clk_main_i,
@@ -110,6 +118,10 @@
   input  tlul_pkg::tl_d2h_t tl_rv_plic_i,
   output tlul_pkg::tl_h2d_t tl_pinmux_o,
   input  tlul_pkg::tl_d2h_t tl_pinmux_i,
+  output tlul_pkg::tl_h2d_t tl_alert_handler_o,
+  input  tlul_pkg::tl_d2h_t tl_alert_handler_i,
+  output tlul_pkg::tl_h2d_t tl_nmi_gen_o,
+  input  tlul_pkg::tl_d2h_t tl_nmi_gen_i,
 
   input scanmode_i
 );
@@ -122,29 +134,15 @@
   logic unused_scanmode;
   assign unused_scanmode = scanmode_i;
 
-  tl_h2d_t tl_s1n_16_us_h2d ;
-  tl_d2h_t tl_s1n_16_us_d2h ;
+  tl_h2d_t tl_s1n_18_us_h2d ;
+  tl_d2h_t tl_s1n_18_us_d2h ;
 
 
-  tl_h2d_t tl_s1n_16_ds_h2d [4];
-  tl_d2h_t tl_s1n_16_ds_d2h [4];
+  tl_h2d_t tl_s1n_18_ds_h2d [4];
+  tl_d2h_t tl_s1n_18_ds_d2h [4];
 
   // Create steering signal
-  logic [2:0] dev_sel_s1n_16;
-
-
-  tl_h2d_t tl_sm1_17_us_h2d [3];
-  tl_d2h_t tl_sm1_17_us_d2h [3];
-
-  tl_h2d_t tl_sm1_17_ds_h2d ;
-  tl_d2h_t tl_sm1_17_ds_d2h ;
-
-
-  tl_h2d_t tl_sm1_18_us_h2d [2];
-  tl_d2h_t tl_sm1_18_us_d2h [2];
-
-  tl_h2d_t tl_sm1_18_ds_h2d ;
-  tl_d2h_t tl_sm1_18_ds_d2h ;
+  logic [2:0] dev_sel_s1n_18;
 
 
   tl_h2d_t tl_sm1_19_us_h2d [3];
@@ -154,35 +152,35 @@
   tl_d2h_t tl_sm1_19_ds_d2h ;
 
 
-  tl_h2d_t tl_sm1_20_us_h2d [3];
-  tl_d2h_t tl_sm1_20_us_d2h [3];
+  tl_h2d_t tl_sm1_20_us_h2d [2];
+  tl_d2h_t tl_sm1_20_us_d2h [2];
 
   tl_h2d_t tl_sm1_20_ds_h2d ;
   tl_d2h_t tl_sm1_20_ds_d2h ;
 
-  tl_h2d_t tl_s1n_21_us_h2d ;
-  tl_d2h_t tl_s1n_21_us_d2h ;
+
+  tl_h2d_t tl_sm1_21_us_h2d [3];
+  tl_d2h_t tl_sm1_21_us_d2h [3];
+
+  tl_h2d_t tl_sm1_21_ds_h2d ;
+  tl_d2h_t tl_sm1_21_ds_d2h ;
 
 
-  tl_h2d_t tl_s1n_21_ds_h2d [13];
-  tl_d2h_t tl_s1n_21_ds_d2h [13];
-
-  // Create steering signal
-  logic [3:0] dev_sel_s1n_21;
-
-
-  tl_h2d_t tl_sm1_22_us_h2d [2];
-  tl_d2h_t tl_sm1_22_us_d2h [2];
+  tl_h2d_t tl_sm1_22_us_h2d [3];
+  tl_d2h_t tl_sm1_22_us_d2h [3];
 
   tl_h2d_t tl_sm1_22_ds_h2d ;
   tl_d2h_t tl_sm1_22_ds_d2h ;
 
+  tl_h2d_t tl_s1n_23_us_h2d ;
+  tl_d2h_t tl_s1n_23_us_d2h ;
 
-  tl_h2d_t tl_sm1_23_us_h2d [2];
-  tl_d2h_t tl_sm1_23_us_d2h [2];
 
-  tl_h2d_t tl_sm1_23_ds_h2d ;
-  tl_d2h_t tl_sm1_23_ds_d2h ;
+  tl_h2d_t tl_s1n_23_ds_h2d [15];
+  tl_d2h_t tl_s1n_23_ds_d2h [15];
+
+  // Create steering signal
+  logic [3:0] dev_sel_s1n_23;
 
 
   tl_h2d_t tl_sm1_24_us_h2d [2];
@@ -233,226 +231,280 @@
   tl_h2d_t tl_sm1_30_ds_h2d ;
   tl_d2h_t tl_sm1_30_ds_d2h ;
 
-  tl_h2d_t tl_s1n_31_us_h2d ;
-  tl_d2h_t tl_s1n_31_us_d2h ;
+
+  tl_h2d_t tl_sm1_31_us_h2d [2];
+  tl_d2h_t tl_sm1_31_us_d2h [2];
+
+  tl_h2d_t tl_sm1_31_ds_h2d ;
+  tl_d2h_t tl_sm1_31_ds_d2h ;
 
 
-  tl_h2d_t tl_s1n_31_ds_h2d [12];
-  tl_d2h_t tl_s1n_31_ds_d2h [12];
+  tl_h2d_t tl_sm1_32_us_h2d [2];
+  tl_d2h_t tl_sm1_32_us_d2h [2];
+
+  tl_h2d_t tl_sm1_32_ds_h2d ;
+  tl_d2h_t tl_sm1_32_ds_d2h ;
+
+
+  tl_h2d_t tl_sm1_33_us_h2d [2];
+  tl_d2h_t tl_sm1_33_us_d2h [2];
+
+  tl_h2d_t tl_sm1_33_ds_h2d ;
+  tl_d2h_t tl_sm1_33_ds_d2h ;
+
+
+  tl_h2d_t tl_sm1_34_us_h2d [2];
+  tl_d2h_t tl_sm1_34_us_d2h [2];
+
+  tl_h2d_t tl_sm1_34_ds_h2d ;
+  tl_d2h_t tl_sm1_34_ds_d2h ;
+
+  tl_h2d_t tl_s1n_35_us_h2d ;
+  tl_d2h_t tl_s1n_35_us_d2h ;
+
+
+  tl_h2d_t tl_s1n_35_ds_h2d [14];
+  tl_d2h_t tl_s1n_35_ds_d2h [14];
 
   // Create steering signal
-  logic [3:0] dev_sel_s1n_31;
+  logic [3:0] dev_sel_s1n_35;
 
 
 
-  assign tl_sm1_17_us_h2d[0] = tl_s1n_16_ds_h2d[0];
-  assign tl_s1n_16_ds_d2h[0] = tl_sm1_17_us_d2h[0];
+  assign tl_sm1_19_us_h2d[0] = tl_s1n_18_ds_h2d[0];
+  assign tl_s1n_18_ds_d2h[0] = tl_sm1_19_us_d2h[0];
 
-  assign tl_sm1_18_us_h2d[0] = tl_s1n_16_ds_h2d[1];
-  assign tl_s1n_16_ds_d2h[1] = tl_sm1_18_us_d2h[0];
+  assign tl_sm1_20_us_h2d[0] = tl_s1n_18_ds_h2d[1];
+  assign tl_s1n_18_ds_d2h[1] = tl_sm1_20_us_d2h[0];
 
-  assign tl_sm1_19_us_h2d[0] = tl_s1n_16_ds_h2d[2];
-  assign tl_s1n_16_ds_d2h[2] = tl_sm1_19_us_d2h[0];
+  assign tl_sm1_21_us_h2d[0] = tl_s1n_18_ds_h2d[2];
+  assign tl_s1n_18_ds_d2h[2] = tl_sm1_21_us_d2h[0];
 
-  assign tl_sm1_20_us_h2d[0] = tl_s1n_16_ds_h2d[3];
-  assign tl_s1n_16_ds_d2h[3] = tl_sm1_20_us_d2h[0];
+  assign tl_sm1_22_us_h2d[0] = tl_s1n_18_ds_h2d[3];
+  assign tl_s1n_18_ds_d2h[3] = tl_sm1_22_us_d2h[0];
 
-  assign tl_sm1_17_us_h2d[1] = tl_s1n_21_ds_h2d[0];
-  assign tl_s1n_21_ds_d2h[0] = tl_sm1_17_us_d2h[1];
+  assign tl_sm1_19_us_h2d[1] = tl_s1n_23_ds_h2d[0];
+  assign tl_s1n_23_ds_d2h[0] = tl_sm1_19_us_d2h[1];
 
-  assign tl_sm1_18_us_h2d[1] = tl_s1n_21_ds_h2d[1];
-  assign tl_s1n_21_ds_d2h[1] = tl_sm1_18_us_d2h[1];
+  assign tl_sm1_20_us_h2d[1] = tl_s1n_23_ds_h2d[1];
+  assign tl_s1n_23_ds_d2h[1] = tl_sm1_20_us_d2h[1];
 
-  assign tl_sm1_19_us_h2d[1] = tl_s1n_21_ds_h2d[2];
-  assign tl_s1n_21_ds_d2h[2] = tl_sm1_19_us_d2h[1];
+  assign tl_sm1_21_us_h2d[1] = tl_s1n_23_ds_h2d[2];
+  assign tl_s1n_23_ds_d2h[2] = tl_sm1_21_us_d2h[1];
 
-  assign tl_sm1_20_us_h2d[1] = tl_s1n_21_ds_h2d[3];
-  assign tl_s1n_21_ds_d2h[3] = tl_sm1_20_us_d2h[1];
+  assign tl_sm1_22_us_h2d[1] = tl_s1n_23_ds_h2d[3];
+  assign tl_s1n_23_ds_d2h[3] = tl_sm1_22_us_d2h[1];
 
-  assign tl_sm1_22_us_h2d[0] = tl_s1n_21_ds_h2d[4];
-  assign tl_s1n_21_ds_d2h[4] = tl_sm1_22_us_d2h[0];
+  assign tl_sm1_24_us_h2d[0] = tl_s1n_23_ds_h2d[4];
+  assign tl_s1n_23_ds_d2h[4] = tl_sm1_24_us_d2h[0];
 
-  assign tl_sm1_23_us_h2d[0] = tl_s1n_21_ds_h2d[5];
-  assign tl_s1n_21_ds_d2h[5] = tl_sm1_23_us_d2h[0];
+  assign tl_sm1_25_us_h2d[0] = tl_s1n_23_ds_h2d[5];
+  assign tl_s1n_23_ds_d2h[5] = tl_sm1_25_us_d2h[0];
 
-  assign tl_sm1_24_us_h2d[0] = tl_s1n_21_ds_h2d[6];
-  assign tl_s1n_21_ds_d2h[6] = tl_sm1_24_us_d2h[0];
+  assign tl_sm1_26_us_h2d[0] = tl_s1n_23_ds_h2d[6];
+  assign tl_s1n_23_ds_d2h[6] = tl_sm1_26_us_d2h[0];
 
-  assign tl_sm1_25_us_h2d[0] = tl_s1n_21_ds_h2d[7];
-  assign tl_s1n_21_ds_d2h[7] = tl_sm1_25_us_d2h[0];
+  assign tl_sm1_27_us_h2d[0] = tl_s1n_23_ds_h2d[7];
+  assign tl_s1n_23_ds_d2h[7] = tl_sm1_27_us_d2h[0];
 
-  assign tl_sm1_26_us_h2d[0] = tl_s1n_21_ds_h2d[8];
-  assign tl_s1n_21_ds_d2h[8] = tl_sm1_26_us_d2h[0];
+  assign tl_sm1_28_us_h2d[0] = tl_s1n_23_ds_h2d[8];
+  assign tl_s1n_23_ds_d2h[8] = tl_sm1_28_us_d2h[0];
 
-  assign tl_sm1_27_us_h2d[0] = tl_s1n_21_ds_h2d[9];
-  assign tl_s1n_21_ds_d2h[9] = tl_sm1_27_us_d2h[0];
+  assign tl_sm1_29_us_h2d[0] = tl_s1n_23_ds_h2d[9];
+  assign tl_s1n_23_ds_d2h[9] = tl_sm1_29_us_d2h[0];
 
-  assign tl_sm1_28_us_h2d[0] = tl_s1n_21_ds_h2d[10];
-  assign tl_s1n_21_ds_d2h[10] = tl_sm1_28_us_d2h[0];
+  assign tl_sm1_30_us_h2d[0] = tl_s1n_23_ds_h2d[10];
+  assign tl_s1n_23_ds_d2h[10] = tl_sm1_30_us_d2h[0];
 
-  assign tl_sm1_29_us_h2d[0] = tl_s1n_21_ds_h2d[11];
-  assign tl_s1n_21_ds_d2h[11] = tl_sm1_29_us_d2h[0];
+  assign tl_sm1_31_us_h2d[0] = tl_s1n_23_ds_h2d[11];
+  assign tl_s1n_23_ds_d2h[11] = tl_sm1_31_us_d2h[0];
 
-  assign tl_sm1_30_us_h2d[0] = tl_s1n_21_ds_h2d[12];
-  assign tl_s1n_21_ds_d2h[12] = tl_sm1_30_us_d2h[0];
+  assign tl_sm1_32_us_h2d[0] = tl_s1n_23_ds_h2d[12];
+  assign tl_s1n_23_ds_d2h[12] = tl_sm1_32_us_d2h[0];
 
-  assign tl_sm1_17_us_h2d[2] = tl_s1n_31_ds_h2d[0];
-  assign tl_s1n_31_ds_d2h[0] = tl_sm1_17_us_d2h[2];
+  assign tl_sm1_33_us_h2d[0] = tl_s1n_23_ds_h2d[13];
+  assign tl_s1n_23_ds_d2h[13] = tl_sm1_33_us_d2h[0];
 
-  assign tl_sm1_19_us_h2d[2] = tl_s1n_31_ds_h2d[1];
-  assign tl_s1n_31_ds_d2h[1] = tl_sm1_19_us_d2h[2];
+  assign tl_sm1_34_us_h2d[0] = tl_s1n_23_ds_h2d[14];
+  assign tl_s1n_23_ds_d2h[14] = tl_sm1_34_us_d2h[0];
 
-  assign tl_sm1_20_us_h2d[2] = tl_s1n_31_ds_h2d[2];
-  assign tl_s1n_31_ds_d2h[2] = tl_sm1_20_us_d2h[2];
+  assign tl_sm1_19_us_h2d[2] = tl_s1n_35_ds_h2d[0];
+  assign tl_s1n_35_ds_d2h[0] = tl_sm1_19_us_d2h[2];
 
-  assign tl_sm1_22_us_h2d[1] = tl_s1n_31_ds_h2d[3];
-  assign tl_s1n_31_ds_d2h[3] = tl_sm1_22_us_d2h[1];
+  assign tl_sm1_21_us_h2d[2] = tl_s1n_35_ds_h2d[1];
+  assign tl_s1n_35_ds_d2h[1] = tl_sm1_21_us_d2h[2];
 
-  assign tl_sm1_23_us_h2d[1] = tl_s1n_31_ds_h2d[4];
-  assign tl_s1n_31_ds_d2h[4] = tl_sm1_23_us_d2h[1];
+  assign tl_sm1_22_us_h2d[2] = tl_s1n_35_ds_h2d[2];
+  assign tl_s1n_35_ds_d2h[2] = tl_sm1_22_us_d2h[2];
 
-  assign tl_sm1_24_us_h2d[1] = tl_s1n_31_ds_h2d[5];
-  assign tl_s1n_31_ds_d2h[5] = tl_sm1_24_us_d2h[1];
+  assign tl_sm1_24_us_h2d[1] = tl_s1n_35_ds_h2d[3];
+  assign tl_s1n_35_ds_d2h[3] = tl_sm1_24_us_d2h[1];
 
-  assign tl_sm1_25_us_h2d[1] = tl_s1n_31_ds_h2d[6];
-  assign tl_s1n_31_ds_d2h[6] = tl_sm1_25_us_d2h[1];
+  assign tl_sm1_25_us_h2d[1] = tl_s1n_35_ds_h2d[4];
+  assign tl_s1n_35_ds_d2h[4] = tl_sm1_25_us_d2h[1];
 
-  assign tl_sm1_26_us_h2d[1] = tl_s1n_31_ds_h2d[7];
-  assign tl_s1n_31_ds_d2h[7] = tl_sm1_26_us_d2h[1];
+  assign tl_sm1_26_us_h2d[1] = tl_s1n_35_ds_h2d[5];
+  assign tl_s1n_35_ds_d2h[5] = tl_sm1_26_us_d2h[1];
 
-  assign tl_sm1_27_us_h2d[1] = tl_s1n_31_ds_h2d[8];
-  assign tl_s1n_31_ds_d2h[8] = tl_sm1_27_us_d2h[1];
+  assign tl_sm1_27_us_h2d[1] = tl_s1n_35_ds_h2d[6];
+  assign tl_s1n_35_ds_d2h[6] = tl_sm1_27_us_d2h[1];
 
-  assign tl_sm1_28_us_h2d[1] = tl_s1n_31_ds_h2d[9];
-  assign tl_s1n_31_ds_d2h[9] = tl_sm1_28_us_d2h[1];
+  assign tl_sm1_28_us_h2d[1] = tl_s1n_35_ds_h2d[7];
+  assign tl_s1n_35_ds_d2h[7] = tl_sm1_28_us_d2h[1];
 
-  assign tl_sm1_29_us_h2d[1] = tl_s1n_31_ds_h2d[10];
-  assign tl_s1n_31_ds_d2h[10] = tl_sm1_29_us_d2h[1];
+  assign tl_sm1_29_us_h2d[1] = tl_s1n_35_ds_h2d[8];
+  assign tl_s1n_35_ds_d2h[8] = tl_sm1_29_us_d2h[1];
 
-  assign tl_sm1_30_us_h2d[1] = tl_s1n_31_ds_h2d[11];
-  assign tl_s1n_31_ds_d2h[11] = tl_sm1_30_us_d2h[1];
+  assign tl_sm1_30_us_h2d[1] = tl_s1n_35_ds_h2d[9];
+  assign tl_s1n_35_ds_d2h[9] = tl_sm1_30_us_d2h[1];
 
-  assign tl_s1n_16_us_h2d = tl_corei_i;
-  assign tl_corei_o = tl_s1n_16_us_d2h;
+  assign tl_sm1_31_us_h2d[1] = tl_s1n_35_ds_h2d[10];
+  assign tl_s1n_35_ds_d2h[10] = tl_sm1_31_us_d2h[1];
 
-  assign tl_rom_o = tl_sm1_17_ds_h2d;
-  assign tl_sm1_17_ds_d2h = tl_rom_i;
+  assign tl_sm1_32_us_h2d[1] = tl_s1n_35_ds_h2d[11];
+  assign tl_s1n_35_ds_d2h[11] = tl_sm1_32_us_d2h[1];
 
-  assign tl_debug_mem_o = tl_sm1_18_ds_h2d;
-  assign tl_sm1_18_ds_d2h = tl_debug_mem_i;
+  assign tl_sm1_33_us_h2d[1] = tl_s1n_35_ds_h2d[12];
+  assign tl_s1n_35_ds_d2h[12] = tl_sm1_33_us_d2h[1];
 
-  assign tl_ram_main_o = tl_sm1_19_ds_h2d;
-  assign tl_sm1_19_ds_d2h = tl_ram_main_i;
+  assign tl_sm1_34_us_h2d[1] = tl_s1n_35_ds_h2d[13];
+  assign tl_s1n_35_ds_d2h[13] = tl_sm1_34_us_d2h[1];
 
-  assign tl_eflash_o = tl_sm1_20_ds_h2d;
-  assign tl_sm1_20_ds_d2h = tl_eflash_i;
+  assign tl_s1n_18_us_h2d = tl_corei_i;
+  assign tl_corei_o = tl_s1n_18_us_d2h;
 
-  assign tl_s1n_21_us_h2d = tl_cored_i;
-  assign tl_cored_o = tl_s1n_21_us_d2h;
+  assign tl_rom_o = tl_sm1_19_ds_h2d;
+  assign tl_sm1_19_ds_d2h = tl_rom_i;
 
-  assign tl_uart_o = tl_sm1_22_ds_h2d;
-  assign tl_sm1_22_ds_d2h = tl_uart_i;
+  assign tl_debug_mem_o = tl_sm1_20_ds_h2d;
+  assign tl_sm1_20_ds_d2h = tl_debug_mem_i;
 
-  assign tl_gpio_o = tl_sm1_23_ds_h2d;
-  assign tl_sm1_23_ds_d2h = tl_gpio_i;
+  assign tl_ram_main_o = tl_sm1_21_ds_h2d;
+  assign tl_sm1_21_ds_d2h = tl_ram_main_i;
 
-  assign tl_spi_device_o = tl_sm1_24_ds_h2d;
-  assign tl_sm1_24_ds_d2h = tl_spi_device_i;
+  assign tl_eflash_o = tl_sm1_22_ds_h2d;
+  assign tl_sm1_22_ds_d2h = tl_eflash_i;
 
-  assign tl_flash_ctrl_o = tl_sm1_25_ds_h2d;
-  assign tl_sm1_25_ds_d2h = tl_flash_ctrl_i;
+  assign tl_s1n_23_us_h2d = tl_cored_i;
+  assign tl_cored_o = tl_s1n_23_us_d2h;
 
-  assign tl_rv_timer_o = tl_sm1_26_ds_h2d;
-  assign tl_sm1_26_ds_d2h = tl_rv_timer_i;
+  assign tl_uart_o = tl_sm1_24_ds_h2d;
+  assign tl_sm1_24_ds_d2h = tl_uart_i;
 
-  assign tl_aes_o = tl_sm1_27_ds_h2d;
-  assign tl_sm1_27_ds_d2h = tl_aes_i;
+  assign tl_gpio_o = tl_sm1_25_ds_h2d;
+  assign tl_sm1_25_ds_d2h = tl_gpio_i;
 
-  assign tl_hmac_o = tl_sm1_28_ds_h2d;
-  assign tl_sm1_28_ds_d2h = tl_hmac_i;
+  assign tl_spi_device_o = tl_sm1_26_ds_h2d;
+  assign tl_sm1_26_ds_d2h = tl_spi_device_i;
 
-  assign tl_rv_plic_o = tl_sm1_29_ds_h2d;
-  assign tl_sm1_29_ds_d2h = tl_rv_plic_i;
+  assign tl_flash_ctrl_o = tl_sm1_27_ds_h2d;
+  assign tl_sm1_27_ds_d2h = tl_flash_ctrl_i;
 
-  assign tl_pinmux_o = tl_sm1_30_ds_h2d;
-  assign tl_sm1_30_ds_d2h = tl_pinmux_i;
+  assign tl_rv_timer_o = tl_sm1_28_ds_h2d;
+  assign tl_sm1_28_ds_d2h = tl_rv_timer_i;
 
-  assign tl_s1n_31_us_h2d = tl_dm_sba_i;
-  assign tl_dm_sba_o = tl_s1n_31_us_d2h;
+  assign tl_aes_o = tl_sm1_29_ds_h2d;
+  assign tl_sm1_29_ds_d2h = tl_aes_i;
+
+  assign tl_hmac_o = tl_sm1_30_ds_h2d;
+  assign tl_sm1_30_ds_d2h = tl_hmac_i;
+
+  assign tl_rv_plic_o = tl_sm1_31_ds_h2d;
+  assign tl_sm1_31_ds_d2h = tl_rv_plic_i;
+
+  assign tl_pinmux_o = tl_sm1_32_ds_h2d;
+  assign tl_sm1_32_ds_d2h = tl_pinmux_i;
+
+  assign tl_alert_handler_o = tl_sm1_33_ds_h2d;
+  assign tl_sm1_33_ds_d2h = tl_alert_handler_i;
+
+  assign tl_nmi_gen_o = tl_sm1_34_ds_h2d;
+  assign tl_sm1_34_ds_d2h = tl_nmi_gen_i;
+
+  assign tl_s1n_35_us_h2d = tl_dm_sba_i;
+  assign tl_dm_sba_o = tl_s1n_35_us_d2h;
 
   always_comb begin
     // default steering to generate error response if address is not within the range
-    dev_sel_s1n_16 = 3'd4;
-    if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
-      dev_sel_s1n_16 = 3'd0;
-    end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
-      dev_sel_s1n_16 = 3'd1;
-    end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
-      dev_sel_s1n_16 = 3'd2;
-    end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
-      dev_sel_s1n_16 = 3'd3;
+    dev_sel_s1n_18 = 3'd4;
+    if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+      dev_sel_s1n_18 = 3'd0;
+    end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+      dev_sel_s1n_18 = 3'd1;
+    end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+      dev_sel_s1n_18 = 3'd2;
+    end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+      dev_sel_s1n_18 = 3'd3;
     end
   end
 
   always_comb begin
     // default steering to generate error response if address is not within the range
-    dev_sel_s1n_21 = 4'd13;
-    if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
-      dev_sel_s1n_21 = 4'd0;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
-      dev_sel_s1n_21 = 4'd1;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
-      dev_sel_s1n_21 = 4'd2;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
-      dev_sel_s1n_21 = 4'd3;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
-      dev_sel_s1n_21 = 4'd4;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
-      dev_sel_s1n_21 = 4'd5;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
-      dev_sel_s1n_21 = 4'd6;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
-      dev_sel_s1n_21 = 4'd7;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
-      dev_sel_s1n_21 = 4'd8;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
-      dev_sel_s1n_21 = 4'd9;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
-      dev_sel_s1n_21 = 4'd10;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
-      dev_sel_s1n_21 = 4'd11;
-    end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
-      dev_sel_s1n_21 = 4'd12;
+    dev_sel_s1n_23 = 4'd15;
+    if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+      dev_sel_s1n_23 = 4'd0;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+      dev_sel_s1n_23 = 4'd1;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+      dev_sel_s1n_23 = 4'd2;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+      dev_sel_s1n_23 = 4'd3;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+      dev_sel_s1n_23 = 4'd4;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+      dev_sel_s1n_23 = 4'd5;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+      dev_sel_s1n_23 = 4'd6;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+      dev_sel_s1n_23 = 4'd7;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+      dev_sel_s1n_23 = 4'd8;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+      dev_sel_s1n_23 = 4'd9;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+      dev_sel_s1n_23 = 4'd10;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+      dev_sel_s1n_23 = 4'd11;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+      dev_sel_s1n_23 = 4'd12;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+      dev_sel_s1n_23 = 4'd13;
+    end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+      dev_sel_s1n_23 = 4'd14;
     end
   end
 
   always_comb begin
     // default steering to generate error response if address is not within the range
-    dev_sel_s1n_31 = 4'd12;
-    if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
-      dev_sel_s1n_31 = 4'd0;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
-      dev_sel_s1n_31 = 4'd1;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
-      dev_sel_s1n_31 = 4'd2;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
-      dev_sel_s1n_31 = 4'd3;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
-      dev_sel_s1n_31 = 4'd4;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
-      dev_sel_s1n_31 = 4'd5;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
-      dev_sel_s1n_31 = 4'd6;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
-      dev_sel_s1n_31 = 4'd7;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
-      dev_sel_s1n_31 = 4'd8;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
-      dev_sel_s1n_31 = 4'd9;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
-      dev_sel_s1n_31 = 4'd10;
-    end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
-      dev_sel_s1n_31 = 4'd11;
+    dev_sel_s1n_35 = 4'd14;
+    if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+      dev_sel_s1n_35 = 4'd0;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+      dev_sel_s1n_35 = 4'd1;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+      dev_sel_s1n_35 = 4'd2;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+      dev_sel_s1n_35 = 4'd3;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+      dev_sel_s1n_35 = 4'd4;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+      dev_sel_s1n_35 = 4'd5;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+      dev_sel_s1n_35 = 4'd6;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+      dev_sel_s1n_35 = 4'd7;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+      dev_sel_s1n_35 = 4'd8;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+      dev_sel_s1n_35 = 4'd9;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+      dev_sel_s1n_35 = 4'd10;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+      dev_sel_s1n_35 = 4'd11;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+      dev_sel_s1n_35 = 4'd12;
+    end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+      dev_sel_s1n_35 = 4'd13;
     end
   end
 
@@ -464,42 +516,14 @@
     .DReqDepth ({4{4'h0}}),
     .DRspDepth ({4{4'h0}}),
     .N         (4)
-  ) u_s1n_16 (
+  ) u_s1n_18 (
     .clk_i        (clk_main_i),
     .rst_ni       (rst_main_ni),
-    .tl_h_i       (tl_s1n_16_us_h2d),
-    .tl_h_o       (tl_s1n_16_us_d2h),
-    .tl_d_o       (tl_s1n_16_ds_h2d),
-    .tl_d_i       (tl_s1n_16_ds_d2h),
-    .dev_select   (dev_sel_s1n_16)
-  );
-  tlul_socket_m1 #(
-    .HReqDepth ({3{4'h0}}),
-    .HRspDepth ({3{4'h0}}),
-    .DReqDepth (4'h0),
-    .DRspDepth (4'h0),
-    .M         (3)
-  ) u_sm1_17 (
-    .clk_i        (clk_main_i),
-    .rst_ni       (rst_main_ni),
-    .tl_h_i       (tl_sm1_17_us_h2d),
-    .tl_h_o       (tl_sm1_17_us_d2h),
-    .tl_d_o       (tl_sm1_17_ds_h2d),
-    .tl_d_i       (tl_sm1_17_ds_d2h)
-  );
-  tlul_socket_m1 #(
-    .HReqPass  (2'h0),
-    .HRspPass  (2'h0),
-    .DReqPass  (1'b0),
-    .DRspPass  (1'b0),
-    .M         (2)
-  ) u_sm1_18 (
-    .clk_i        (clk_main_i),
-    .rst_ni       (rst_main_ni),
-    .tl_h_i       (tl_sm1_18_us_h2d),
-    .tl_h_o       (tl_sm1_18_us_d2h),
-    .tl_d_o       (tl_sm1_18_ds_h2d),
-    .tl_d_i       (tl_sm1_18_ds_d2h)
+    .tl_h_i       (tl_s1n_18_us_h2d),
+    .tl_h_o       (tl_s1n_18_us_d2h),
+    .tl_d_o       (tl_s1n_18_ds_h2d),
+    .tl_d_i       (tl_s1n_18_ds_d2h),
+    .dev_select   (dev_sel_s1n_18)
   );
   tlul_socket_m1 #(
     .HReqDepth ({3{4'h0}}),
@@ -516,11 +540,11 @@
     .tl_d_i       (tl_sm1_19_ds_d2h)
   );
   tlul_socket_m1 #(
-    .HReqDepth ({3{4'h0}}),
-    .HRspDepth ({3{4'h0}}),
-    .DReqDepth (4'h0),
-    .DRspDepth (4'h0),
-    .M         (3)
+    .HReqPass  (2'h0),
+    .HRspPass  (2'h0),
+    .DReqPass  (1'b0),
+    .DRspPass  (1'b0),
+    .M         (2)
   ) u_sm1_20 (
     .clk_i        (clk_main_i),
     .rst_ni       (rst_main_ni),
@@ -529,27 +553,26 @@
     .tl_d_o       (tl_sm1_20_ds_h2d),
     .tl_d_i       (tl_sm1_20_ds_d2h)
   );
-  tlul_socket_1n #(
-    .HReqDepth (4'h0),
-    .HRspDepth (4'h0),
-    .DReqDepth ({13{4'h0}}),
-    .DRspDepth ({13{4'h0}}),
-    .N         (13)
-  ) u_s1n_21 (
+  tlul_socket_m1 #(
+    .HReqDepth ({3{4'h0}}),
+    .HRspDepth ({3{4'h0}}),
+    .DReqDepth (4'h0),
+    .DRspDepth (4'h0),
+    .M         (3)
+  ) u_sm1_21 (
     .clk_i        (clk_main_i),
     .rst_ni       (rst_main_ni),
-    .tl_h_i       (tl_s1n_21_us_h2d),
-    .tl_h_o       (tl_s1n_21_us_d2h),
-    .tl_d_o       (tl_s1n_21_ds_h2d),
-    .tl_d_i       (tl_s1n_21_ds_d2h),
-    .dev_select   (dev_sel_s1n_21)
+    .tl_h_i       (tl_sm1_21_us_h2d),
+    .tl_h_o       (tl_sm1_21_us_d2h),
+    .tl_d_o       (tl_sm1_21_ds_h2d),
+    .tl_d_i       (tl_sm1_21_ds_d2h)
   );
   tlul_socket_m1 #(
-    .HReqPass  (2'h0),
-    .HRspPass  (2'h0),
-    .DReqPass  (1'b0),
-    .DRspPass  (1'b0),
-    .M         (2)
+    .HReqDepth ({3{4'h0}}),
+    .HRspDepth ({3{4'h0}}),
+    .DReqDepth (4'h0),
+    .DRspDepth (4'h0),
+    .M         (3)
   ) u_sm1_22 (
     .clk_i        (clk_main_i),
     .rst_ni       (rst_main_ni),
@@ -558,19 +581,20 @@
     .tl_d_o       (tl_sm1_22_ds_h2d),
     .tl_d_i       (tl_sm1_22_ds_d2h)
   );
-  tlul_socket_m1 #(
-    .HReqPass  (2'h0),
-    .HRspPass  (2'h0),
-    .DReqPass  (1'b0),
-    .DRspPass  (1'b0),
-    .M         (2)
-  ) u_sm1_23 (
+  tlul_socket_1n #(
+    .HReqDepth (4'h0),
+    .HRspDepth (4'h0),
+    .DReqDepth ({15{4'h0}}),
+    .DRspDepth ({15{4'h0}}),
+    .N         (15)
+  ) u_s1n_23 (
     .clk_i        (clk_main_i),
     .rst_ni       (rst_main_ni),
-    .tl_h_i       (tl_sm1_23_us_h2d),
-    .tl_h_o       (tl_sm1_23_us_d2h),
-    .tl_d_o       (tl_sm1_23_ds_h2d),
-    .tl_d_i       (tl_sm1_23_ds_d2h)
+    .tl_h_i       (tl_s1n_23_us_h2d),
+    .tl_h_o       (tl_s1n_23_us_d2h),
+    .tl_d_o       (tl_s1n_23_ds_h2d),
+    .tl_d_i       (tl_s1n_23_ds_d2h),
+    .dev_select   (dev_sel_s1n_23)
   );
   tlul_socket_m1 #(
     .HReqPass  (2'h0),
@@ -670,20 +694,76 @@
     .tl_d_o       (tl_sm1_30_ds_h2d),
     .tl_d_i       (tl_sm1_30_ds_d2h)
   );
+  tlul_socket_m1 #(
+    .HReqPass  (2'h0),
+    .HRspPass  (2'h0),
+    .DReqPass  (1'b0),
+    .DRspPass  (1'b0),
+    .M         (2)
+  ) u_sm1_31 (
+    .clk_i        (clk_main_i),
+    .rst_ni       (rst_main_ni),
+    .tl_h_i       (tl_sm1_31_us_h2d),
+    .tl_h_o       (tl_sm1_31_us_d2h),
+    .tl_d_o       (tl_sm1_31_ds_h2d),
+    .tl_d_i       (tl_sm1_31_ds_d2h)
+  );
+  tlul_socket_m1 #(
+    .HReqPass  (2'h0),
+    .HRspPass  (2'h0),
+    .DReqPass  (1'b0),
+    .DRspPass  (1'b0),
+    .M         (2)
+  ) u_sm1_32 (
+    .clk_i        (clk_main_i),
+    .rst_ni       (rst_main_ni),
+    .tl_h_i       (tl_sm1_32_us_h2d),
+    .tl_h_o       (tl_sm1_32_us_d2h),
+    .tl_d_o       (tl_sm1_32_ds_h2d),
+    .tl_d_i       (tl_sm1_32_ds_d2h)
+  );
+  tlul_socket_m1 #(
+    .HReqPass  (2'h0),
+    .HRspPass  (2'h0),
+    .DReqPass  (1'b0),
+    .DRspPass  (1'b0),
+    .M         (2)
+  ) u_sm1_33 (
+    .clk_i        (clk_main_i),
+    .rst_ni       (rst_main_ni),
+    .tl_h_i       (tl_sm1_33_us_h2d),
+    .tl_h_o       (tl_sm1_33_us_d2h),
+    .tl_d_o       (tl_sm1_33_ds_h2d),
+    .tl_d_i       (tl_sm1_33_ds_d2h)
+  );
+  tlul_socket_m1 #(
+    .HReqPass  (2'h0),
+    .HRspPass  (2'h0),
+    .DReqPass  (1'b0),
+    .DRspPass  (1'b0),
+    .M         (2)
+  ) u_sm1_34 (
+    .clk_i        (clk_main_i),
+    .rst_ni       (rst_main_ni),
+    .tl_h_i       (tl_sm1_34_us_h2d),
+    .tl_h_o       (tl_sm1_34_us_d2h),
+    .tl_d_o       (tl_sm1_34_ds_h2d),
+    .tl_d_i       (tl_sm1_34_ds_d2h)
+  );
   tlul_socket_1n #(
     .HReqPass  (1'b0),
     .HRspPass  (1'b0),
-    .DReqPass  (12'h0),
-    .DRspPass  (12'h0),
-    .N         (12)
-  ) u_s1n_31 (
+    .DReqPass  (14'h0),
+    .DRspPass  (14'h0),
+    .N         (14)
+  ) u_s1n_35 (
     .clk_i        (clk_main_i),
     .rst_ni       (rst_main_ni),
-    .tl_h_i       (tl_s1n_31_us_h2d),
-    .tl_h_o       (tl_s1n_31_us_d2h),
-    .tl_d_o       (tl_s1n_31_ds_h2d),
-    .tl_d_i       (tl_s1n_31_ds_d2h),
-    .dev_select   (dev_sel_s1n_31)
+    .tl_h_i       (tl_s1n_35_us_h2d),
+    .tl_h_o       (tl_s1n_35_us_d2h),
+    .tl_d_o       (tl_s1n_35_ds_h2d),
+    .tl_d_i       (tl_s1n_35_ds_d2h),
+    .dev_select   (dev_sel_s1n_35)
   );
 
 endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index dd3b616..0720b72 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -81,6 +81,10 @@
   tl_d2h_t  tl_rv_plic_d_d2h;
   tl_h2d_t  tl_pinmux_d_h2d;
   tl_d2h_t  tl_pinmux_d_d2h;
+  tl_h2d_t  tl_alert_handler_d_h2d;
+  tl_d2h_t  tl_alert_handler_d_d2h;
+  tl_h2d_t  tl_nmi_gen_d_h2d;
+  tl_d2h_t  tl_nmi_gen_d_d2h;
 
   tl_h2d_t tl_rom_d_h2d;
   tl_d2h_t tl_rom_d_d2h;
@@ -121,9 +125,11 @@
   // hmac
   // rv_plic
   // pinmux
+  // alert_handler
+  // nmi_gen
 
 
-  logic [54:0]  intr_vector;
+  logic [62:0]  intr_vector;
   // Interrupt source list
   logic intr_uart_tx_watermark;
   logic intr_uart_rx_watermark;
@@ -150,6 +156,15 @@
   logic intr_hmac_hmac_done;
   logic intr_hmac_fifo_full;
   logic intr_hmac_hmac_err;
+  logic intr_alert_handler_classa;
+  logic intr_alert_handler_classb;
+  logic intr_alert_handler_classc;
+  logic intr_alert_handler_classd;
+  logic intr_nmi_gen_esc0;
+  logic intr_nmi_gen_esc1;
+  logic intr_nmi_gen_esc2;
+  logic intr_nmi_gen_esc3;
+
 
   
   logic [0:0] irq_plic;
@@ -160,6 +175,14 @@
   // this avoids lint errors
   assign unused_irq_id = irq_id;
 
+  // Alert list
+  prim_pkg::alert_tx_t [alert_pkg::NAlerts-1:0]  alert_tx;
+  prim_pkg::alert_rx_t [alert_pkg::NAlerts-1:0]  alert_rx;
+  // Escalation outputs
+  prim_pkg::esc_tx_t [alert_pkg::N_ESC_SEV-1:0]  esc_tx;
+  prim_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0]  esc_rx;
+
+
   // clock assignments
   assign main_clk = clk_i;
 
@@ -389,6 +412,7 @@
   );
 
 
+
   uart uart (
       .tl_i (tl_uart_d_h2d),
       .tl_o (tl_uart_d_d2h),
@@ -452,7 +476,6 @@
       .intr_rxerr_o       (intr_spi_device_rxerr),
       .intr_rxoverflow_o  (intr_spi_device_rxoverflow),
       .intr_txunderflow_o (intr_spi_device_txunderflow),
-
       .scanmode_i   (scanmode_i),
 
       .clk_i (main_clk),
@@ -505,6 +528,10 @@
       .intr_hmac_done_o (intr_hmac_hmac_done),
       .intr_fifo_full_o (intr_hmac_fifo_full),
       .intr_hmac_err_o  (intr_hmac_hmac_err),
+      
+      // [0]: msg_push_sha_disabled 
+      .alert_tx_o  ( alert_tx[0:0] ),
+      .alert_rx_i  ( alert_rx[0:0] ),
 
       .clk_i (main_clk),
       .rst_ni (sys_rst_n)
@@ -539,8 +566,57 @@
       .rst_ni (sys_rst_n)
   );
 
+  alert_handler alert_handler (
+      .tl_i (tl_alert_handler_d_h2d),
+      .tl_o (tl_alert_handler_d_d2h),
+
+      // Interrupt
+      .intr_classa_o (intr_alert_handler_classa),
+      .intr_classb_o (intr_alert_handler_classb),
+      .intr_classc_o (intr_alert_handler_classc),
+      .intr_classd_o (intr_alert_handler_classd),
+      // TODO: wire this to hardware debug circuit
+      .crashdump_o (          ),
+      // TODO: wire this to TRNG
+      .entropy_i   ( 1'b0     ),
+      // alert signals
+      .alert_rx_o  ( alert_rx ),
+      .alert_tx_i  ( alert_tx ),
+      // escalation outputs
+      .esc_rx_i    ( esc_rx   ),
+      .esc_tx_o    ( esc_tx   ),
+
+      .clk_i (main_clk),
+      .rst_ni (sys_rst_n)
+  );
+
+  nmi_gen nmi_gen (
+      .tl_i (tl_nmi_gen_d_h2d),
+      .tl_o (tl_nmi_gen_d_d2h),
+
+      // Interrupt
+      .intr_esc0_o (intr_nmi_gen_esc0),
+      .intr_esc1_o (intr_nmi_gen_esc1),
+      .intr_esc2_o (intr_nmi_gen_esc2),
+      .intr_esc3_o (intr_nmi_gen_esc3),
+      // escalation signal inputs
+      .esc_rx_o    ( esc_rx   ),
+      .esc_tx_i    ( esc_tx   ),
+
+      .clk_i (main_clk),
+      .rst_ni (sys_rst_n)
+  );
+
   // interrupt assignments
   assign intr_vector = {
+      intr_nmi_gen_esc3,
+      intr_nmi_gen_esc2,
+      intr_nmi_gen_esc1,
+      intr_nmi_gen_esc0,
+      intr_alert_handler_classd,
+      intr_alert_handler_classc,
+      intr_alert_handler_classb,
+      intr_alert_handler_classa,
       intr_hmac_hmac_err,
       intr_hmac_fifo_full,
       intr_hmac_hmac_done,
@@ -571,38 +647,42 @@
   xbar_main u_xbar_main (
     .clk_main_i (main_clk),
     .rst_main_ni (sys_rst_n),
-    .tl_corei_i      (tl_corei_h_h2d),
-    .tl_corei_o      (tl_corei_h_d2h),
-    .tl_cored_i      (tl_cored_h_h2d),
-    .tl_cored_o      (tl_cored_h_d2h),
-    .tl_dm_sba_i     (tl_dm_sba_h_h2d),
-    .tl_dm_sba_o     (tl_dm_sba_h_d2h),
-    .tl_rom_o        (tl_rom_d_h2d),
-    .tl_rom_i        (tl_rom_d_d2h),
-    .tl_debug_mem_o  (tl_debug_mem_d_h2d),
-    .tl_debug_mem_i  (tl_debug_mem_d_d2h),
-    .tl_ram_main_o   (tl_ram_main_d_h2d),
-    .tl_ram_main_i   (tl_ram_main_d_d2h),
-    .tl_eflash_o     (tl_eflash_d_h2d),
-    .tl_eflash_i     (tl_eflash_d_d2h),
-    .tl_uart_o       (tl_uart_d_h2d),
-    .tl_uart_i       (tl_uart_d_d2h),
-    .tl_gpio_o       (tl_gpio_d_h2d),
-    .tl_gpio_i       (tl_gpio_d_d2h),
-    .tl_spi_device_o (tl_spi_device_d_h2d),
-    .tl_spi_device_i (tl_spi_device_d_d2h),
-    .tl_flash_ctrl_o (tl_flash_ctrl_d_h2d),
-    .tl_flash_ctrl_i (tl_flash_ctrl_d_d2h),
-    .tl_rv_timer_o   (tl_rv_timer_d_h2d),
-    .tl_rv_timer_i   (tl_rv_timer_d_d2h),
-    .tl_hmac_o       (tl_hmac_d_h2d),
-    .tl_hmac_i       (tl_hmac_d_d2h),
-    .tl_aes_o        (tl_aes_d_h2d),
-    .tl_aes_i        (tl_aes_d_d2h),
-    .tl_rv_plic_o    (tl_rv_plic_d_h2d),
-    .tl_rv_plic_i    (tl_rv_plic_d_d2h),
-    .tl_pinmux_o     (tl_pinmux_d_h2d),
-    .tl_pinmux_i     (tl_pinmux_d_d2h),
+    .tl_corei_i         (tl_corei_h_h2d),
+    .tl_corei_o         (tl_corei_h_d2h),
+    .tl_cored_i         (tl_cored_h_h2d),
+    .tl_cored_o         (tl_cored_h_d2h),
+    .tl_dm_sba_i        (tl_dm_sba_h_h2d),
+    .tl_dm_sba_o        (tl_dm_sba_h_d2h),
+    .tl_rom_o           (tl_rom_d_h2d),
+    .tl_rom_i           (tl_rom_d_d2h),
+    .tl_debug_mem_o     (tl_debug_mem_d_h2d),
+    .tl_debug_mem_i     (tl_debug_mem_d_d2h),
+    .tl_ram_main_o      (tl_ram_main_d_h2d),
+    .tl_ram_main_i      (tl_ram_main_d_d2h),
+    .tl_eflash_o        (tl_eflash_d_h2d),
+    .tl_eflash_i        (tl_eflash_d_d2h),
+    .tl_uart_o          (tl_uart_d_h2d),
+    .tl_uart_i          (tl_uart_d_d2h),
+    .tl_gpio_o          (tl_gpio_d_h2d),
+    .tl_gpio_i          (tl_gpio_d_d2h),
+    .tl_spi_device_o    (tl_spi_device_d_h2d),
+    .tl_spi_device_i    (tl_spi_device_d_d2h),
+    .tl_flash_ctrl_o    (tl_flash_ctrl_d_h2d),
+    .tl_flash_ctrl_i    (tl_flash_ctrl_d_d2h),
+    .tl_rv_timer_o      (tl_rv_timer_d_h2d),
+    .tl_rv_timer_i      (tl_rv_timer_d_d2h),
+    .tl_hmac_o          (tl_hmac_d_h2d),
+    .tl_hmac_i          (tl_hmac_d_d2h),
+    .tl_aes_o           (tl_aes_d_h2d),
+    .tl_aes_i           (tl_aes_d_d2h),
+    .tl_rv_plic_o       (tl_rv_plic_d_h2d),
+    .tl_rv_plic_i       (tl_rv_plic_d_d2h),
+    .tl_pinmux_o        (tl_pinmux_d_h2d),
+    .tl_pinmux_i        (tl_pinmux_d_d2h),
+    .tl_alert_handler_o (tl_alert_handler_d_h2d),
+    .tl_alert_handler_i (tl_alert_handler_d_d2h),
+    .tl_nmi_gen_o       (tl_nmi_gen_d_h2d),
+    .tl_nmi_gen_i       (tl_nmi_gen_d_d2h),
 
     .scanmode_i
   );
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 40d5374..ff5b396 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -22,6 +22,7 @@
       - lowrisc:prim:flash
       - lowrisc:ip:flash_ctrl:0.1
       - lowrisc:constants:top_pkg
+      - lowrisc:ip:nmi_gen
     files:
       - ip/xbar/rtl/autogen/tl_main_pkg.sv
       - ip/xbar/rtl/autogen/xbar_main.sv
@@ -31,6 +32,15 @@
       - ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
       - ip/pinmux/rtl/autogen/pinmux_reg_top.sv
       - ../ip/pinmux/rtl/pinmux.sv
+      - ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+      - ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+      - ../ip/alert_handler/rtl/alert_pkg.sv
+      - ../ip/alert_handler/rtl/alert_handler_reg_wrap.sv
+      - ../ip/alert_handler/rtl/alert_handler_class.sv
+      - ../ip/alert_handler/rtl/alert_handler_ping_timer.sv
+      - ../ip/alert_handler/rtl/alert_handler_esc_timer.sv
+      - ../ip/alert_handler/rtl/alert_handler_accu.sv
+      - ../ip/alert_handler/rtl/alert_handler.sv
       - rtl/padctl.sv
       - rtl/autogen/top_earlgrey.sv
     file_type: systemVerilogSource
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 4ffbaf4..8986d15 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -303,7 +303,7 @@
     'no_auto_intr_regs': ['s', "Set to true to suppress automatic "\
                           "generation of interrupt registers. " \
                           "Defaults to false if not present."],
-    'alert_list': ['ln', "list of peripheral alerts"],
+    'alert_list': ['lnw', "list of peripheral alerts"],
     'regwidth': ['d', "width of registers in bits (default 32)"],
     'param_list': ['lp', "list of parameters of the IP"],
     'scan': ['pb', 'Indicates the module have `scanmode_i`'],
diff --git a/util/topgen.py b/util/topgen.py
index a60f983..5ce2270 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -19,7 +19,7 @@
 from topgen import get_hjsonobj_xbars, merge_top, search_ips, validate_top
 
 # Filter from IP list but adding generated hjson
-filter_list = ['rv_plic', 'alert_h', 'pinmux']
+filter_list = ['rv_plic', 'pinmux']
 
 # Common header for generated files
 genhdr = '''// Copyright lowRISC contributors.
@@ -85,6 +85,103 @@
         with bind_filepath.open(mode='w', encoding='UTF-8') as fout:
             fout.write(out_bind)
 
+def generate_alert_handler(top, out_path):
+    # default values
+    esc_cnt_dw=32
+    accu_cnt_dw=16
+    lfsr_seed=2**31-1
+    async_on="'0"
+    # leave this constant
+    n_classes=4
+
+    # check if there are any params to be passed through reggen and placed into
+    # the generated package
+    ip_list_in_top = [x["name"].lower() for x in top["module"]]
+    ah_idx = ip_list_in_top.index("alert_handler")
+    if 'localparam' in top['module'][ah_idx]:
+        if 'EscCntDw' in top['module'][ah_idx]['localparam']:
+            esc_cnt_dw = int(top['module'][ah_idx]['localparam']['EscCntDw'])
+        if 'AccuCntDw' in top['module'][ah_idx]['localparam']:
+            accu_cnt_dw = int(top['module'][ah_idx]['localparam']['AccuCntDw'])
+        if 'LfsrSeed' in top['module'][ah_idx]['localparam']:
+            lfsr_seed = int(top['module'][ah_idx]['localparam']['LfsrSeed'], 0)
+
+    if esc_cnt_dw < 1:
+        log.error("EscCntDw must be larger than 0")
+    if accu_cnt_dw < 1:
+        log.error("AccuCntDw must be larger than 0")
+    if (lfsr_seed & 0xFFFFFFFF) == 0 or lfsr_seed > 2**32:
+        log.error("LFSR seed out of range or zero")
+
+    # Count number of interrupts
+    n_alerts = sum([x["width"] if "width" in x else 1 for x in top["alert"]])
+
+    if n_alerts < 1:
+        # set number of alerts to 1 such that the config is still valid
+        # that input will be tied off
+        n_alerts = 1
+        log.warning("no alerts are defined in the system");
+    else:
+        async_on = ""
+        for alert in top['alert']:
+            async_on = str(alert['async']) + async_on
+        async_on = ("%d'b" % n_alerts) + async_on
+
+    log.info("alert handler parameterization:")
+    log.info("NAlerts   = %d" % n_alerts)
+    log.info("EscCntDw  = %d" % esc_cnt_dw)
+    log.info("AccuCntDw = %d" % accu_cnt_dw)
+    log.info("LfsrSeed  = %d" % lfsr_seed)
+    log.info("AsyncOn   = %s" % async_on)
+
+
+    # Define target path
+    rtl_path = out_path / 'ip/alert_handler/rtl/autogen'
+    rtl_path.mkdir(parents=True, exist_ok=True)
+    doc_path = out_path / 'ip/alert_handler/data/autogen'
+    doc_path.mkdir(parents=True, exist_ok=True)
+
+    # Generating IP top module script is not generalized yet.
+    # So, topgen reads template files from alert_handler directory directly.
+    tpl_path = out_path / '../ip/alert_handler/data'
+    hjson_tpl_path = tpl_path / 'alert_handler.hjson.tpl'
+
+    # Generate Register Package and RTLs
+    out = StringIO()
+    with hjson_tpl_path.open(mode='r', encoding='UTF-8') as fin:
+        hjson_tpl = Template(fin.read())
+        try:
+            out = hjson_tpl.render(n_alerts=n_alerts,
+                                   esc_cnt_dw=esc_cnt_dw,
+                                   accu_cnt_dw=accu_cnt_dw,
+                                   lfsr_seed=lfsr_seed,
+                                   async_on=async_on,
+                                   n_classes=n_classes)
+        except:
+            log.error(exceptions.text_error_template().render())
+        log.info("alert_handler hjson: %s" % out)
+
+    if out == "":
+        log.error("Cannot generate alert_handler config file")
+        return
+
+    hjson_gen_path = doc_path / "alert_handler.hjson"
+    gencmd = (
+        "// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --alert-handler-only "
+        "-o hw/top_earlgrey/\n\n")
+    with hjson_gen_path.open(mode='w', encoding='UTF-8') as fout:
+        fout.write(genhdr + gencmd + out)
+
+    # Generate register RTLs (currently using shell execute)
+    # TODO: More secure way to gneerate RTL
+    hjson_obj = hjson.loads(out,
+                            use_decimal=True,
+                            object_pairs_hook=validate.checking_dict)
+    validate.validate(hjson_obj)
+    gen_rtl.gen_rtl(hjson_obj, str(rtl_path))
+
+
+
 
 def generate_plic(top, out_path):
     # Count number of interrupts
@@ -99,7 +196,7 @@
     #   data: rv_plic.hjson
     rtl_path = out_path / 'ip/rv_plic/rtl/autogen'
     rtl_path.mkdir(parents=True, exist_ok=True)
-    doc_path = out_path / 'ip/rv_plic/doc/autogen'
+    doc_path = out_path / 'ip/rv_plic/data/autogen'
     doc_path.mkdir(parents=True, exist_ok=True)
     hjson_path = out_path / 'ip/rv_plic/data/autogen'
     hjson_path.mkdir(parents=True, exist_ok=True)
@@ -312,6 +409,10 @@
         action='store_true',
         help="If defined, the tool generates RV_PLIC RTL and Hjson only")
     parser.add_argument(
+        '--alert-handler-only',
+        action='store_true',
+        help="If defined, the tool generates alert handler hjson only")
+    parser.add_argument(
         '--hjson-only',
         action='store_true',
         help="If defined, the tool generates complete Hjson only")
@@ -335,12 +436,12 @@
 
     if (args.no_top or args.no_xbar or
             args.no_plic) and (args.top_only or args.xbar_only or
-                               args.plic_only):
+                               args.plic_only or args.alert_handler_only):
         log.error(
             "'no' series options cannot be used with 'only' series options")
         raise SystemExit(sys.exc_info()[1])
 
-    if not args.hjson_only and not args.tpl:
+    if not (args.hjson_only or args.plic_only or args.alert_handler_only or args.tpl):
         log.error(
             "Template file can be omitted only if '--hjson-only' is true")
         raise SystemExit(sys.exc_info()[1])
@@ -446,8 +547,18 @@
             raise SystemExit(sys.exc_info()[1])
 
     # Generate PLIC
-    if not args.no_plic or args.plic_only:
+    if not args.no_plic            and \
+       not args.alert_handler_only and \
+       not args.xbar_only:
         generate_plic(completecfg, out_path)
+        if args.plic_only:
+            sys.exit()
+
+    # Generate Alert Handler
+    if not args.xbar_only:
+        generate_alert_handler(completecfg, out_path)
+        if args.alert_handler_only:
+            sys.exit()
 
     generate_pinmux(completecfg, out_path)
 
diff --git a/util/topgen/merge.py b/util/topgen/merge.py
index 86c91b5..64cda8f 100644
--- a/util/topgen/merge.py
+++ b/util/topgen/merge.py
@@ -24,7 +24,7 @@
         - available_output_list: empty list if doesn't exist
         - available_inout_list: empty list if doesn't exist
         - interrupt_list: empty list if doesn't exist
-        - (TBD) alert_list: empty list if doesn't exist
+        - alert_list: empty list if doesn't exist
     """
     ip_list_in_top = [x["name"].lower() for x in top["module"]]
     ipname = ip["name"].lower()
@@ -34,6 +34,8 @@
 
     # Find index of the IP
     ip_idx = ip_list_in_top.index(ipname)
+    # Needed to detect async alert transitions below
+    ah_idx = ip_list_in_top.index("alert_handler")
 
     ip_module = top["module"][ip_idx]
 
@@ -90,7 +92,21 @@
     else:
         ip_module["interrupt_list"] = []
 
-    # (TBD) alert_list
+    # alert_list
+    if "alert_list" in ip:
+        ip_module["alert_list"] = ip["alert_list"]
+        for i in ip_module["alert_list"]:
+            i.pop('desc', None)
+            i["type"] = "alert"
+            i["width"] = int(i["width"])
+            # automatically insert asynchronous transition if necessary
+            if ip_module["clock_connections"]["clk_i"] == \
+               top["module"][ah_idx]["clock_connections"]["clk_i"]:
+                i["async"] = 0
+            else:
+                i["async"] = 1
+    else:
+        ip_module["alert_list"] = []
 
     # scan
     if "scan" in ip:
@@ -291,6 +307,26 @@
             map(partial(add_prefix_to_signal, prefix=m.lower()),
                 ip[0]["interrupt_list"]))
 
+def amend_alert(top):
+    """Check interrupt_module if exists, or just use all modules
+    """
+    if not "alert_module" in top:
+        top["alert_module"] = [x["name"] for x in top["module"]]
+
+    if not "alert" in top or top["alert"] == "":
+        top["alert"] = []
+
+    for m in top["alert_module"]:
+        ip = list(filter(lambda module: module["name"] == m, top["module"]))
+        if len(ip) == 0:
+            log.warning(
+                "Cannot find IP %s which is used in the alert_module" % m)
+            continue
+
+        log.info("Adding alert from module %s" % ip[0]["name"])
+        top["alert"] += list(
+            map(partial(add_prefix_to_signal, prefix=m.lower()),
+                ip[0]["alert_list"]))
 
 def amend_pinmux_io(top):
     """ Check dio_modules/ mio_modules. If not exists, add all modules to mio
@@ -422,6 +458,9 @@
     # Combine the interrupt (should be processed prior to xbar)
     amend_interrupt(gencfg)
 
+    # Combine the alert (should be processed prior to xbar)
+    amend_alert(gencfg)
+
     # Creates input/output list in the pinmux
     log.info("Processing PINMUX")
     amend_pinmux_io(gencfg)
diff --git a/util/topgen/validate.py b/util/topgen/validate.py
index 6c13472..2e1f447 100644
--- a/util/topgen/validate.py
+++ b/util/topgen/validate.py
@@ -50,6 +50,9 @@
 top_optional = {
     'interrupt_modules': ['l', 'list of the modules that connects to rv_plic'],
     'interrupt': ['lnw', 'interrupts (generated)'],
+    'alert_modules': ['l', 'list of the modules that connects to alert_handler'],
+    'alert': ['lnw', 'alerts (generated)'],
+    'alert_async': ['l', 'async alerts (generated)'],
     'pinmux': ['g', 'pinmux definition if doesn\'t exist, tool uses defaults'],
     'padctrl':
     ['g', 'PADS instantiation, if doesn\'t exist, tool creates direct output'],